2024年3月22日发(作者：子车泰鸿)

EN057 (v1.3) March 31, 2009

00

Errata Notification

Introduction

Although Xilinx has made every effort to ensure the highest possible quality, these Virtex®-5 FPGA engineering samples

(ES) are subject to the limitations described in the following errata.

Devices

These errata apply to the Virtex-5 devices, as shown in Table1.

Table 1: Virtex-5 Devices Affected by These Errata

Devices

XC5VFX30T CES

XC5VFX70T CES

XC5VFX100T CES

XC5VFX130T CES

XC5VFX200T CES

PackagesAll

Speed Grades

-1, -2, -3

-1, -2, -3

-1, -2, -3

-1, -2, -3

-1, -2

JTAG ID (Revision Code)

6

6

2

2

0

Hardware Errata Details

This section provides a detailed description of each hardware issue known at the release time of this document.

GTX Transceivers

Clock Correction

The Clock Correction feature of the Virtex-5 FPGA GTX transceiver can cause data corruption on the receiver when a clock

correction sequence is skipped or added. See UG198

, Virtex-5 FPGA RocketIO GTX Transceiver User Guide for more

detailed information about the Clock Correction feature.

This issue can occur when all of the following conditions are true:

•Asynchronous operation: When the local reference clock of the Virtex-5 FPGA GTX transceiver is driven from a

different oscillator than the far-end transceiver. This introduces a parts per million (PPM) offset in frequency between

the operation of the transceivers, requiring clock correction to skip or add clock correction sequences on a periodic

basis. This also implies that the RXUSRCLK and RXUSRCLK2 ports of the Virtex-5 FPGA GTX transceiver are derived

from the local oscillator and not the RXRECCLK port.

Clock Correction is enabled.

-CLK_CORRECT_USE_0/1 attribute is set to TRUE.

The length of the clock correction sequence is 1 or 3 Bytes.

-CLK_COR_ADJ_LEN_0/1 attribute is set to 1 or 3.

•

•

When the conditions described above are met, one of the multiple work-around options described below shall be used to

mitigate this issue. XAUI, PCIe®, SRIO, and Infiniband are the most common protocols affected but only when used in asyn-

chronous operation.

EN057 (v1.3) March 31, 2009

Errata Notification

Work-around

If the application permits, implement one of the following work-around options:

•Use synchronous clocking

•Convert to 2byte or 4byte clock correction sequence

•If the application does not permit one of these options, see Answer Record 32164.

All versions of UG198

, Virtex-5 FPGA RocketIO GTX Transceiver User Guide subsequent to the current version, v2.1, will

properly reflect the Clock Correction behavior described herein.

PowerPC 440 Processor

Branch History Table

The Branch History Table (BHT) must be disabled for deterministic execution latency.

Auxiliary Processor Unit

There are two errata for the Auxiliary Processor Unit (APU):

•

•

After a Translation Look-aside Buffer (TLB) miss caused by an instruction fetch, in a very specific combination of

events, the Auxiliary Processor Unit (APU) can lock up or corrupt the data.

When the floating-point execution is disabled in the PowerPC

®

440 processor but enabled in the APU controller, and an

FPU instruction is executed, the processor can generate a spurious program exception instead of an FPU-unavailable

exception.

Additional Information

For more details, including work-arounds for the processor errata, refer to answer record 30529.

Operational Guidelines

Design Software Requirements

CORE Generator™ software must be used to correctly configure the GTX transceivers.

The devices listed in Table1, unless otherwise specified, require the following Xilinx development software installations.

•Speed specification v1.59 (or later), Xilinx ISE™ Design Suite 10.1 (or later).

-For -3 speed grade, the minimum software requirement is Xilinx ISE Design Suite 10.1 with Service Pack 2 (or

later).

The stepping should not be set, but if set, it must be set to zero in the user constraint file (UCF):

CONFIG STEPPING = “0”;

•

EN057 (v1.3) March 31, 2009

Errata Notification

Traceability

The XC5VFX30T CES is marked as shown in Figure1. The other devices listed in Table1 are marked similarly.

TM

Device Type

Package

Speed Grade

XC5VFX30T

TM

FF665IGUXXXX

DxxxxxxxA

1C

-ES

Date Code

Lot Code

Engineering Sample

Operating Range

EN057_01_031808

EN057 (v1.3) March 31, 2009

2024年3月22日发(作者：子车泰鸿)

EN057 (v1.3) March 31, 2009

00

Errata Notification

Introduction

Although Xilinx has made every effort to ensure the highest possible quality, these Virtex®-5 FPGA engineering samples

(ES) are subject to the limitations described in the following errata.

Devices

These errata apply to the Virtex-5 devices, as shown in Table1.

Table 1: Virtex-5 Devices Affected by These Errata

Devices

XC5VFX30T CES

XC5VFX70T CES

XC5VFX100T CES

XC5VFX130T CES

XC5VFX200T CES

PackagesAll

Speed Grades

-1, -2, -3

-1, -2, -3

-1, -2, -3

-1, -2, -3

-1, -2

JTAG ID (Revision Code)

6

6

2

2

0

Hardware Errata Details

This section provides a detailed description of each hardware issue known at the release time of this document.

GTX Transceivers

Clock Correction

The Clock Correction feature of the Virtex-5 FPGA GTX transceiver can cause data corruption on the receiver when a clock

correction sequence is skipped or added. See UG198

, Virtex-5 FPGA RocketIO GTX Transceiver User Guide for more

detailed information about the Clock Correction feature.

This issue can occur when all of the following conditions are true:

•Asynchronous operation: When the local reference clock of the Virtex-5 FPGA GTX transceiver is driven from a

different oscillator than the far-end transceiver. This introduces a parts per million (PPM) offset in frequency between

the operation of the transceivers, requiring clock correction to skip or add clock correction sequences on a periodic

basis. This also implies that the RXUSRCLK and RXUSRCLK2 ports of the Virtex-5 FPGA GTX transceiver are derived

from the local oscillator and not the RXRECCLK port.

Clock Correction is enabled.

-CLK_CORRECT_USE_0/1 attribute is set to TRUE.

The length of the clock correction sequence is 1 or 3 Bytes.

-CLK_COR_ADJ_LEN_0/1 attribute is set to 1 or 3.

•

•

When the conditions described above are met, one of the multiple work-around options described below shall be used to

mitigate this issue. XAUI, PCIe®, SRIO, and Infiniband are the most common protocols affected but only when used in asyn-

chronous operation.

EN057 (v1.3) March 31, 2009

Errata Notification

Work-around

If the application permits, implement one of the following work-around options:

•Use synchronous clocking

•Convert to 2byte or 4byte clock correction sequence

•If the application does not permit one of these options, see Answer Record 32164.

All versions of UG198

, Virtex-5 FPGA RocketIO GTX Transceiver User Guide subsequent to the current version, v2.1, will

properly reflect the Clock Correction behavior described herein.

PowerPC 440 Processor

Branch History Table

The Branch History Table (BHT) must be disabled for deterministic execution latency.

Auxiliary Processor Unit

There are two errata for the Auxiliary Processor Unit (APU):

•

•

After a Translation Look-aside Buffer (TLB) miss caused by an instruction fetch, in a very specific combination of

events, the Auxiliary Processor Unit (APU) can lock up or corrupt the data.

When the floating-point execution is disabled in the PowerPC

®

440 processor but enabled in the APU controller, and an

FPU instruction is executed, the processor can generate a spurious program exception instead of an FPU-unavailable

exception.

Additional Information

For more details, including work-arounds for the processor errata, refer to answer record 30529.

Operational Guidelines

Design Software Requirements

CORE Generator™ software must be used to correctly configure the GTX transceivers.

The devices listed in Table1, unless otherwise specified, require the following Xilinx development software installations.

•Speed specification v1.59 (or later), Xilinx ISE™ Design Suite 10.1 (or later).

-For -3 speed grade, the minimum software requirement is Xilinx ISE Design Suite 10.1 with Service Pack 2 (or

later).

The stepping should not be set, but if set, it must be set to zero in the user constraint file (UCF):

CONFIG STEPPING = “0”;

•

EN057 (v1.3) March 31, 2009

Errata Notification

Traceability

The XC5VFX30T CES is marked as shown in Figure1. The other devices listed in Table1 are marked similarly.

TM

Device Type

Package

Speed Grade

XC5VFX30T

TM

FF665IGUXXXX

DxxxxxxxA

1C

-ES

Date Code

Lot Code

Engineering Sample

Operating Range

EN057_01_031808

EN057 (v1.3) March 31, 2009