2024年3月22日发(作者：府秋珊)
Input/Output Delay Switching Characteristics
Table 64:Input/Output Delay Switching Characteristics
Symbol
IDELAYCTRL
T
IDELAYCTRLCO_RDY
F
IDELAYCTRL_REF
T
IDELAYCTRL_RPW
IODELAY
T
IDELAYRESOLUTION
IODELAY Chain Delay Resolution
Pattern dependent period jitter in delay chain for clock
pattern
Pattern dependent period jitter in delay chain for
random data pattern (PRBS 23)
Maximum frequency of CLK input to IODELAY
CE pin Setup/Hold with respect to CK
INC pin Setup/Hold with respect to CK
RST pin Setup/Hold with respect to CK
TSCONTROL delay to MUXE/MUXF switching and
through IODELAY
Propagation delay through IODELAY
Propagation delay through IODELAY
0
±5
250
0.34
–0.06
0.20
0.04
0.28
–0.12
Note3
Note3
Note3
1/(64xF
REF
x1e
6
)
(1)
0
±5
250
0.42
–0.06
0.24
0.06
0.33
–0.12
Note3
Note3
Note3
0
±5
250
0.42
–0.06
0.24
0.06
0.33
–0.12
Note3
Note3
Note3
ps
Note2
Note2
MHz
ns
ns
ns
Reset to Ready for IDELAYCTRL
REFCLK frequency
Minimum Reset pulse width
3.00
200.00
±10
50.00
3.00
200.00
±10
50.00
3.00
200.00
±10
50.00
µs
MHz
MHz
ns
Description
Speed Grade
-2I-1I-1M
Units
IDELAYCTRL_REF_PRECISIONREFCLK precision
T
IDELAYPAT_JIT
T
IODELAY_CLK_MAX
T
IODCCK_CE
/ T
IODCKC_CE
T
IODCK_INC
/ T
IODCKC_INC
T
IODCK_RST
/ T
IODCKC_RST
T
IODDO_T
T
IODDO_IDATAIN
T
IODDO_ODATAIN
Symbol
Combinatorial Delays
T
ILO
Description
Speed Grade
-2I
0.09
0.22
0.35
0.77
0.44
0.52
0.36
0.62
0.41
-1I
0.10
0.25
0.40
0.90
0.53
0.61
0.42
0.73
0.48
-1M
0.10
0.25
0.40
0.90
0.53
0.61
0.42
0.73
0.48
Units
An–Dn LUT address to A
An–Dn LUT address to AMUX/CMUX
An–Dn LUT address to BMUX_A
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
T
ITO
T
AXA
T
AXB
T
AXC
T
AXD
T
BXB
An–Dn inputs to A–D Q outputs
AX inputs to AMUX output
AX inputs to BMUX output
AX inputs to CMUX output
AX inputs to DMUX output
BX inputs to BMUX output
DS714 (v2.2) January 17, 2011
Product Specification
Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics
Block RAM and FIFO Switching Characteristics
Table 68:Block RAM and FIFO Switching Characteristics
Symbol
Block RAM and FIFO Clock to Out Delays
T
RCKO_DO
and T
RCKO_DOR
(1)
Clock CLK to DOUT output (without output register)
(2)(3)
Clock CLK to DOUT output (with output register)
(4)(5)
Clock CLK to DOUT output with ECC (without output
register)
(2)(3)
Clock CLK to DOUT output with ECC (with output
register)
(4)(5)
Clock CLK to DOUT output with Cascade (without output
register)
(2)
Clock CLK to DOUT output with Cascade (with output
register)
(4)
T
RCKO_FLAGS
T
RCKO_POINTERS
T
RCKO_ECCR
T
RCKO_ECC
Clock CLK to FIFO flags outputs
(6)
Clock CLK to FIFO pointer outputs
(7)
Clock CLK to BITERR (with output register)
Clock CLK to BITERR (without output register)
Clock CLK to ECCPARITY in standard ECC mode
Clock CLK to ECCPARITY in ECC encode only mode
1.92
0.69
3.03
0.77
2.44
1.07
0.87
1.26
0.77
2.85
1.47
0.89
2.19
0.82
3.61
0.93
2.94
1.30
1.02
1.48
0.93
3.41
1.74
1.05
2.19
0.82
3.61
0.93
2.94
1.30
1.02
1.48
0.93
3.41
1.74
1.05
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
Description
Speed Grade
-2I-1I-1M
Units
Setup and Hold Times Before/After Clock CLK
T
RCCK_ADDR
/T
RCKC_ADDR
T
RDCK_DI
/T
RCKD_DI
ADDR inputs
(8)
DIN inputs
(9)
DIN inputs with ECC in standard mode
(9)
T
RDCK_DI_ECC
/T
RCKD_DI_ECC
DIN inputs with ECC encode only
(9)
T
RCCK_EN
/T
RCKC_EN
T
RCCK_REGCE
/T
RCKC_REGCE
T
RCCK_SSR
/T
RCKC_SSR
T
RCCK_WE
/T
RCKC_WE
T
RCCK_WREN
/T
RCKC_WREN
Block RAM Enable (EN) input
CE input of output register
Synchronous Set/ Reset (SSR) input
Write Enable (WE) input
WREN/RDEN FIFO inputs
(10)
0.40
0.32
0.30
0.28
0.37
0.33
0.72
0.33
0.36
0.15
0.16
0.24
0.21
0.25
0.51
0.17
0.41
0.34
0.48
0.36
0.35
0.29
0.42
0.36
0.77
0.36
0.42
0.15
0.18
0.27
0.26
0.28
0.63
0.18
0.48
0.40
0.48
0.36
0.35
0.29
0.42
0.47
0.77
0.47
0.42
0.15
0.18
0.27
0.26
0.28
0.63
0.18
0.48
0.40
ns, Min
ns, Min
ns, Min
ns, Min
ns, Min
ns, Min
ns, Min
ns, Min
ns, Min
Reset Delays
T
RCO_FLAGS
Reset RST to FIFO Flags/Pointers
(11)
1.261.481.48ns, Max
DS714 (v2.2) January 17, 2011
Product Specification
2024年3月22日发(作者：府秋珊)
Input/Output Delay Switching Characteristics
Table 64:Input/Output Delay Switching Characteristics
Symbol
IDELAYCTRL
T
IDELAYCTRLCO_RDY
F
IDELAYCTRL_REF
T
IDELAYCTRL_RPW
IODELAY
T
IDELAYRESOLUTION
IODELAY Chain Delay Resolution
Pattern dependent period jitter in delay chain for clock
pattern
Pattern dependent period jitter in delay chain for
random data pattern (PRBS 23)
Maximum frequency of CLK input to IODELAY
CE pin Setup/Hold with respect to CK
INC pin Setup/Hold with respect to CK
RST pin Setup/Hold with respect to CK
TSCONTROL delay to MUXE/MUXF switching and
through IODELAY
Propagation delay through IODELAY
Propagation delay through IODELAY
0
±5
250
0.34
–0.06
0.20
0.04
0.28
–0.12
Note3
Note3
Note3
1/(64xF
REF
x1e
6
)
(1)
0
±5
250
0.42
–0.06
0.24
0.06
0.33
–0.12
Note3
Note3
Note3
0
±5
250
0.42
–0.06
0.24
0.06
0.33
–0.12
Note3
Note3
Note3
ps
Note2
Note2
MHz
ns
ns
ns
Reset to Ready for IDELAYCTRL
REFCLK frequency
Minimum Reset pulse width
3.00
200.00
±10
50.00
3.00
200.00
±10
50.00
3.00
200.00
±10
50.00
µs
MHz
MHz
ns
Description
Speed Grade
-2I-1I-1M
Units
IDELAYCTRL_REF_PRECISIONREFCLK precision
T
IDELAYPAT_JIT
T
IODELAY_CLK_MAX
T
IODCCK_CE
/ T
IODCKC_CE
T
IODCK_INC
/ T
IODCKC_INC
T
IODCK_RST
/ T
IODCKC_RST
T
IODDO_T
T
IODDO_IDATAIN
T
IODDO_ODATAIN
Symbol
Combinatorial Delays
T
ILO
Description
Speed Grade
-2I
0.09
0.22
0.35
0.77
0.44
0.52
0.36
0.62
0.41
-1I
0.10
0.25
0.40
0.90
0.53
0.61
0.42
0.73
0.48
-1M
0.10
0.25
0.40
0.90
0.53
0.61
0.42
0.73
0.48
Units
An–Dn LUT address to A
An–Dn LUT address to AMUX/CMUX
An–Dn LUT address to BMUX_A
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
T
ITO
T
AXA
T
AXB
T
AXC
T
AXD
T
BXB
An–Dn inputs to A–D Q outputs
AX inputs to AMUX output
AX inputs to BMUX output
AX inputs to CMUX output
AX inputs to DMUX output
BX inputs to BMUX output
DS714 (v2.2) January 17, 2011
Product Specification
Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics
Block RAM and FIFO Switching Characteristics
Table 68:Block RAM and FIFO Switching Characteristics
Symbol
Block RAM and FIFO Clock to Out Delays
T
RCKO_DO
and T
RCKO_DOR
(1)
Clock CLK to DOUT output (without output register)
(2)(3)
Clock CLK to DOUT output (with output register)
(4)(5)
Clock CLK to DOUT output with ECC (without output
register)
(2)(3)
Clock CLK to DOUT output with ECC (with output
register)
(4)(5)
Clock CLK to DOUT output with Cascade (without output
register)
(2)
Clock CLK to DOUT output with Cascade (with output
register)
(4)
T
RCKO_FLAGS
T
RCKO_POINTERS
T
RCKO_ECCR
T
RCKO_ECC
Clock CLK to FIFO flags outputs
(6)
Clock CLK to FIFO pointer outputs
(7)
Clock CLK to BITERR (with output register)
Clock CLK to BITERR (without output register)
Clock CLK to ECCPARITY in standard ECC mode
Clock CLK to ECCPARITY in ECC encode only mode
1.92
0.69
3.03
0.77
2.44
1.07
0.87
1.26
0.77
2.85
1.47
0.89
2.19
0.82
3.61
0.93
2.94
1.30
1.02
1.48
0.93
3.41
1.74
1.05
2.19
0.82
3.61
0.93
2.94
1.30
1.02
1.48
0.93
3.41
1.74
1.05
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
Description
Speed Grade
-2I-1I-1M
Units
Setup and Hold Times Before/After Clock CLK
T
RCCK_ADDR
/T
RCKC_ADDR
T
RDCK_DI
/T
RCKD_DI
ADDR inputs
(8)
DIN inputs
(9)
DIN inputs with ECC in standard mode
(9)
T
RDCK_DI_ECC
/T
RCKD_DI_ECC
DIN inputs with ECC encode only
(9)
T
RCCK_EN
/T
RCKC_EN
T
RCCK_REGCE
/T
RCKC_REGCE
T
RCCK_SSR
/T
RCKC_SSR
T
RCCK_WE
/T
RCKC_WE
T
RCCK_WREN
/T
RCKC_WREN
Block RAM Enable (EN) input
CE input of output register
Synchronous Set/ Reset (SSR) input
Write Enable (WE) input
WREN/RDEN FIFO inputs
(10)
0.40
0.32
0.30
0.28
0.37
0.33
0.72
0.33
0.36
0.15
0.16
0.24
0.21
0.25
0.51
0.17
0.41
0.34
0.48
0.36
0.35
0.29
0.42
0.36
0.77
0.36
0.42
0.15
0.18
0.27
0.26
0.28
0.63
0.18
0.48
0.40
0.48
0.36
0.35
0.29
0.42
0.47
0.77
0.47
0.42
0.15
0.18
0.27
0.26
0.28
0.63
0.18
0.48
0.40
ns, Min
ns, Min
ns, Min
ns, Min
ns, Min
ns, Min
ns, Min
ns, Min
ns, Min
Reset Delays
T
RCO_FLAGS
Reset RST to FIFO Flags/Pointers
(11)
1.261.481.48ns, Max
DS714 (v2.2) January 17, 2011
Product Specification