2024年3月31日发(作者：福秋荷)
4-16译码器
一， 设计思路
1，4-16译码器功能表（真值表）
Inputs输入
G1
G2
d
c
b
a
L
L
L
L
L
L
L
L
L
L
L
H
L
L
L
L
H
L
L
L
L
L
H
H
L
L
L
H
L
L
L
L
L
H
L
H
L
L
L
H
H
L
L
L
L
H
H
H
L
L
H
L
L
L
L
L
H
L
L
H
L
L
H
L
H
L
L
L
H
L
H
H
L
L
H
H
L
L
L
L
H
H
L
H
L
L
H
H
H
L
L
L
H
H
H
H
L
H
X
X
X
X
H
L
X
X
X
X
H
H
X
X
X
X
Outputs输出
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
1-11 13-17 ：输出端。（outputs (active LOW)）
12：Gnd电源地 （ground (0 V)）
18-19：使能输入端 (enable inputs (active LOW))
20-23地址输入端 (address inputs)
2,程序设计过程：
将a,b,c,d设置成四个输入口，用s表示a,b,c,d表示的四位二进
制数。如a=0,b=0,c=0,d=0,则s=0000.再根据4-16译码器的真值
表，使得在输入0000时，y=11110；当输入0001
时，y=11101；依次类推
。
24：VCC电源正 (positive supply voltage)
二， 设计流程图
三， 程序
library ieee;
use _logic_;
entity hou2 is
port(a,b,c,d,G1,G2:in std_logic;
y:out std_logic_vector(15 downto 0));
end entity hou2;
architecture a of hou2 is
signal s:std_logic_vector(3 downto 0);
begin
s<=a&b&c&d;
process(s,G1,G2)is
begin
if(G1='1'AND G2='0')then
case s is
when"0000"=>y<="11110";
when"0001"=>y<="11101";
when"0010"=>y<="11011";
when"0011"=>y<="10111";
when"0100"=>y<="01111";
when"0101"=>y<="11111";
when"0110"=>y<="11111";
when"0111"=>y<="11111";
when"1000"=>y<="11111";
when"1001"=>y<="111111";
when"1010"=>y<="11111";
when"1011"=>y<="1111";
when"1100"=>y<="1111";
when"1101"=>y<="1111";
when"1110"=>y<="1111";
when"1111"=>y<="1111";
when others=>y<="XXXXXXXXXXXXXXXX";
end case;
else
y<="11111";
end if;
end process;
end architecture a;
四， 仿真波形
2024年3月31日发(作者：福秋荷)
4-16译码器
一， 设计思路
1，4-16译码器功能表（真值表）
Inputs输入
G1
G2
d
c
b
a
L
L
L
L
L
L
L
L
L
L
L
H
L
L
L
L
H
L
L
L
L
L
H
H
L
L
L
H
L
L
L
L
L
H
L
H
L
L
L
H
H
L
L
L
L
H
H
H
L
L
H
L
L
L
L
L
H
L
L
H
L
L
H
L
H
L
L
L
H
L
H
H
L
L
H
H
L
L
L
L
H
H
L
H
L
L
H
H
H
L
L
L
H
H
H
H
L
H
X
X
X
X
H
L
X
X
X
X
H
H
X
X
X
X
Outputs输出
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
1-11 13-17 ：输出端。（outputs (active LOW)）
12：Gnd电源地 （ground (0 V)）
18-19：使能输入端 (enable inputs (active LOW))
20-23地址输入端 (address inputs)
2,程序设计过程：
将a,b,c,d设置成四个输入口，用s表示a,b,c,d表示的四位二进
制数。如a=0,b=0,c=0,d=0,则s=0000.再根据4-16译码器的真值
表，使得在输入0000时，y=11110；当输入0001
时，y=11101；依次类推
。
24：VCC电源正 (positive supply voltage)
二， 设计流程图
三， 程序
library ieee;
use _logic_;
entity hou2 is
port(a,b,c,d,G1,G2:in std_logic;
y:out std_logic_vector(15 downto 0));
end entity hou2;
architecture a of hou2 is
signal s:std_logic_vector(3 downto 0);
begin
s<=a&b&c&d;
process(s,G1,G2)is
begin
if(G1='1'AND G2='0')then
case s is
when"0000"=>y<="11110";
when"0001"=>y<="11101";
when"0010"=>y<="11011";
when"0011"=>y<="10111";
when"0100"=>y<="01111";
when"0101"=>y<="11111";
when"0110"=>y<="11111";
when"0111"=>y<="11111";
when"1000"=>y<="11111";
when"1001"=>y<="111111";
when"1010"=>y<="11111";
when"1011"=>y<="1111";
when"1100"=>y<="1111";
when"1101"=>y<="1111";
when"1110"=>y<="1111";
when"1111"=>y<="1111";
when others=>y<="XXXXXXXXXXXXXXXX";
end case;
else
y<="11111";
end if;
end process;
end architecture a;
四， 仿真波形