2024年4月3日发(作者：车山菡)
捷多邦，您值得信赖的PCB打样专家！
MAX 3000A
®
Programmable Logic
Device Family
Data SheetJune 2002, ver. 3.0
■
■
■
■
■
■
■
■
■
■
High–performance, low–cost CMOS EEPROM–based programmable
logic devices (PLDs) built on a MAX
®
architecture (see Table1)
3.3-V in-system programmability (ISP) through the built–in
IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface with
advanced pin-locking capability
–ISP circuitry compliant with IEEE Std. 1532
Built–in boundary-scan test (BST) circuitry compliant with
IEEE Std. 1149.1-1990
Enhanced ISP features:
–Enhanced ISP algorithm for faster programming
–ISP_Done bit to ensure complete programming
–Pull-up resistor on I/O pins during in–system programming
High–density PLDs ranging from 600 to 10,000 usable gates
4.5–ns pin–to–pin logic delays with counter frequencies of up to
227.3MHz
MultiVolt
TM
I/O interface enabling the device core to run at 3.3 V,
while I/O pins are compatible with 5.0–V, 3.3–V, and 2.5–V logic
levels
Pin counts ranging from 44 to 256 in a variety of thin quad flat pack
(TQFP), plastic quad flat pack (PQFP), plastic J–lead chip carrier
(PLCC), and FineLine BGA
TM
packages
Hot–socketing support
Programmable interconnect array (PIA) continuous routing structure
for fast, predictable performance
Table 3000A Device Features
Feature
Usable gates
Macrocells
Logic array blocks
Maximum user I/O
pins
t
PD
(ns)
t
SU
(ns)
t
CO1
(ns)
f
CNT
(MHz)
EPM3032A
600
32
2
34
4.5
2.9
3.0
227.3
EPM3064A
1,250
64
4
66
4.5
2.8
3.1
222.2
EPM3128A
2,500
128
8
96
5.0
3.3
3.4
192.3
EPM3256A
5,000
256
16
158
5.5
3.9
3.5
172.4
EPM3512A
10,000
512
32
208
7.5
5.6
4.7
116.3
Altera Corporation
DS-M3000A-3.0
1
MAX 3000A Programmable Logic Device Family Data Sheet
...and More
Features
General
Description
2
■
PCI compatible
■
Bus–friendly architecture including programmable slew–rate control
■
Open–drain output option
■
Programmable macrocell flipflops with individual clear, preset,
clock, and clock enable controls
■
Programmable power–saving mode for a power reduction of over
50% in each macrocell
■
Configurable expander product–term distribution, allowing up to
32 product terms per macrocell
■
Programmable security bit for protection of proprietary designs
■
Enhanced architectural features, including:
–6 or 10 pin– or logic–driven output enable signals
–Two global clock signals with optional inversion
–Enhanced interconnect resources for improved routability
–Programmable output slew–rate control
■
Software design support and automatic place–and–route provided
by Altera’s development systems for Windows–based PCs and Sun
SPARCstations, and HP 9000 Series 700/800 workstations
■
Additional design entry and simulation support provided by EDIF
2 0 0 and 3 0 0 netlist files, library of parameterized modules (LPM),
Verilog HDL, VHDL, and other interfaces to popular EDA tools from
third–party manufacturers such as Cadence, Exemplar Logic, Mentor
Graphics, OrCAD, Synopsys, Synplicity, and VeriBest
■
Programming support with the Altera master programming unit
(MPU), MasterBlaster
TM
communications cable, ByteBlasterMV
TM
parallel port download cable, BitBlaster
TM
serial download cable as
well as programming hardware from third–party manufacturers and
any in–circuit tester that supports Jam
TM
Standard Test and
Programming Language (STAPL) Files (.jam), Jam STAPL Byte-Code
Files (.jbc), or Serial Vector Format Files (.svf)
MAX3000A devices are low–cost, high–performance devices based on the
Altera MAX architecture. Fabricated with advanced CMOS technology,
the EEPROM–based MAX3000A devices operate with a 3.3-V supply
voltage and provide 600 to 10,000 usable gates, ISP, pin-to-pin delays as
fast as 4.5 ns, and counter speeds of up to 227.3MHz. MAX3000A devices
in the –4, –5, –6, –7, and –10 speed grades are compatible with the timing
requirements of the PCI Special Interest Group (PCI SIG) PCILocal Bus
Specification, Revision2.2. See Table2.
Altera Corporation
2024年4月3日发(作者：车山菡)
捷多邦，您值得信赖的PCB打样专家！
MAX 3000A
®
Programmable Logic
Device Family
Data SheetJune 2002, ver. 3.0
■
■
■
■
■
■
■
■
■
■
High–performance, low–cost CMOS EEPROM–based programmable
logic devices (PLDs) built on a MAX
®
architecture (see Table1)
3.3-V in-system programmability (ISP) through the built–in
IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface with
advanced pin-locking capability
–ISP circuitry compliant with IEEE Std. 1532
Built–in boundary-scan test (BST) circuitry compliant with
IEEE Std. 1149.1-1990
Enhanced ISP features:
–Enhanced ISP algorithm for faster programming
–ISP_Done bit to ensure complete programming
–Pull-up resistor on I/O pins during in–system programming
High–density PLDs ranging from 600 to 10,000 usable gates
4.5–ns pin–to–pin logic delays with counter frequencies of up to
227.3MHz
MultiVolt
TM
I/O interface enabling the device core to run at 3.3 V,
while I/O pins are compatible with 5.0–V, 3.3–V, and 2.5–V logic
levels
Pin counts ranging from 44 to 256 in a variety of thin quad flat pack
(TQFP), plastic quad flat pack (PQFP), plastic J–lead chip carrier
(PLCC), and FineLine BGA
TM
packages
Hot–socketing support
Programmable interconnect array (PIA) continuous routing structure
for fast, predictable performance
Table 3000A Device Features
Feature
Usable gates
Macrocells
Logic array blocks
Maximum user I/O
pins
t
PD
(ns)
t
SU
(ns)
t
CO1
(ns)
f
CNT
(MHz)
EPM3032A
600
32
2
34
4.5
2.9
3.0
227.3
EPM3064A
1,250
64
4
66
4.5
2.8
3.1
222.2
EPM3128A
2,500
128
8
96
5.0
3.3
3.4
192.3
EPM3256A
5,000
256
16
158
5.5
3.9
3.5
172.4
EPM3512A
10,000
512
32
208
7.5
5.6
4.7
116.3
Altera Corporation
DS-M3000A-3.0
1
MAX 3000A Programmable Logic Device Family Data Sheet
...and More
Features
General
Description
2
■
PCI compatible
■
Bus–friendly architecture including programmable slew–rate control
■
Open–drain output option
■
Programmable macrocell flipflops with individual clear, preset,
clock, and clock enable controls
■
Programmable power–saving mode for a power reduction of over
50% in each macrocell
■
Configurable expander product–term distribution, allowing up to
32 product terms per macrocell
■
Programmable security bit for protection of proprietary designs
■
Enhanced architectural features, including:
–6 or 10 pin– or logic–driven output enable signals
–Two global clock signals with optional inversion
–Enhanced interconnect resources for improved routability
–Programmable output slew–rate control
■
Software design support and automatic place–and–route provided
by Altera’s development systems for Windows–based PCs and Sun
SPARCstations, and HP 9000 Series 700/800 workstations
■
Additional design entry and simulation support provided by EDIF
2 0 0 and 3 0 0 netlist files, library of parameterized modules (LPM),
Verilog HDL, VHDL, and other interfaces to popular EDA tools from
third–party manufacturers such as Cadence, Exemplar Logic, Mentor
Graphics, OrCAD, Synopsys, Synplicity, and VeriBest
■
Programming support with the Altera master programming unit
(MPU), MasterBlaster
TM
communications cable, ByteBlasterMV
TM
parallel port download cable, BitBlaster
TM
serial download cable as
well as programming hardware from third–party manufacturers and
any in–circuit tester that supports Jam
TM
Standard Test and
Programming Language (STAPL) Files (.jam), Jam STAPL Byte-Code
Files (.jbc), or Serial Vector Format Files (.svf)
MAX3000A devices are low–cost, high–performance devices based on the
Altera MAX architecture. Fabricated with advanced CMOS technology,
the EEPROM–based MAX3000A devices operate with a 3.3-V supply
voltage and provide 600 to 10,000 usable gates, ISP, pin-to-pin delays as
fast as 4.5 ns, and counter speeds of up to 227.3MHz. MAX3000A devices
in the –4, –5, –6, –7, and –10 speed grades are compatible with the timing
requirements of the PCI Special Interest Group (PCI SIG) PCILocal Bus
Specification, Revision2.2. See Table2.
Altera Corporation