2024年4月4日发(作者：方从阳)

DC Characteristics

This section lists the input pin capacitances, on-chip termination tolerance, and

hot- socketing specifications.

Supply Current

Standby current is the current the device draws after the device is configured with no

inputs/outputs toggling and no activity in the device. Since these currents vary

largely with the resources used, use the Excel-based Early Power Estimator (EPE) to

get supply current estimates for your design.

Table1–4 lists supply current specifications for V

CC_CLKIN

and V

CCPGM

. Use the EPE to get

supply current estimates for remaining power supplies.

Table1– Current Specifications for V

CC_CLKIN

and V

CCPGM

Symbol

I

CLKIN

I

PGM

Parameter

V

CC_CLKIN

current specifications

V

CCPGM

current specifications

Min

0

0

Max

250

250

Unit

mA

mA

I/O Pin Leakage Current

Table1–5 defines StratixIII I/O Pin leakage current specifications.

Table1–xIII I/O Pin Leakage Current (Note1), (2)

Symbol

I

I

I

OZ

Parameter

Input Pin Leakage Current

Tri-stated I/O Pin Leakage

Current

Conditions

V

I

= V

CCIOMAX

to 0 V

V

O

= V

CCIOMAX

to 0 V

Min

-10

-10

Typ

—

—

Max

10

10

Unit

A

A

Notes to Table1–5:

(1)This value is specified for normal device operation. The value may vary during power-up. This applies for all V

CCIO

settings (3.3, 3.0, 2.5, 1.8, 1.5, and 1.2 V).

(2)10-A I/O leakage current limit is applicable when the internal clamping diode is off. A higher current can be

observed when the diode is on.

Bus Hold Specifications

Table1–7 shows the StratixIII device family bus hold specifications.

Table1– Hold Parameters(Part 1 of 2)

V

CCIO

ParameterSymbolConditions

1.2V

Min

Low sustaining

current

High sustaining

current

Low overdrive

current

I

SUSL

I

SUSH

I

ODL

V

IN

>V

IL

(maximum)

V

IN

IH

(minimum)

0V

IN

CCIO

Max

1.5V

MinMax

1.8V

MinMax

2.5V

MinMax

3.0V/3.3V

MinMax

µA

µA

µA

Unit

22.5 —

-22.5 —

—120

25.0 —

-25.0 —

—160

30.0 —

-30.0 —

—200

50.0 —

-50.0 —

—300

70.0 —

-70.0 —

—500

Stratix III Device Handbook, Volume 2

Chapter 1:StratixIII Device Data Sheet: DC and Switching Characteristics

Switching Characteristics

DLL and DQS Logic Block Specifications

Table1–32 describes the DLL frequency range specifications for StratixIII devices.

Table1–xIII DLL Frequency Range Specifications

Frequency

Mode

0

1

2

3

4

5

6

7

Frequency Range (MHz)

C2

90 – 150

120 – 200

150 – 240

180 – 300

240 – 370

290 – 450

360 – 560

470 – 740

C3, I3

90 – 140

120 – 190

150 – 230

180 – 290

240 – 350

290 – 420

360 – 530

470 – 700

C4, I4

90 – 120

120 – 170

150 – 200

180 – 250

240 – 310

290 – 370

360 – 460

470 – 610

C4L, I4L

90 – 120

120 – 170

150 – 200

180 – 250

240 – 310

290 – 370

360 – 460

470 – 610

Available Phase Shift

22.5°, 45°, 67.5°, 90°

30°, 60°, 90°, 120°

36°, 72°, 108°, 144°

45°, 90°,135°, 180°

30°, 60°, 90°,120°

36°, 72°, 108°, 144°

45°, 90°, 135°, 180°

60°, 120°, 180°, 240°

Number of

Delay Chains

16

12

10

8

12

10

8

6

DQS Delay

Buffer Mode (1)

Low

Low

Low

Low

High

High

High

High

Note to Table1–32:

(1)Low indicates 6-bit DQS delay setting, high indicates 5-bit DQS delay setting.

Table1–33 describes the average DQS phase offset delay per setting for StratixIII

devices.

Table1–e DQS Phase Offset Delay per Setting (Note1), (2), (3)

Speed Grade

C2

C3, I3

C4, I4

C4L, I4L

Notes to Table1–33:

(1)The valid settings for phase offset are -64 to +63 for frequency modes 0 to 3 and -32 to +31 for frequency modes

4 to 6.

(2)The typical value equals the average of the minimum and maximum values.

(3)The delay settings are linear with a cumulative delay variation of ±20ps for all speed grades. For example, when

using a C2 speed grade and applying 10° phase offset settings to a 90° phase shift at 400 MHz, the expected

minimum cumulative delay is [625 ps + (10*7 ps) - 20 ps] = 675 ps.

Min

7

7

7

7

Typ

10

11

11.5

11.5

Max

13

15

16

16

Unit

ps

ps

ps

ps

Table1–xIII DQS Phase Shift Error Specification for DLL-Delayed Clock (tDQS_PSERR) (Note1)

Number of DQS Delay

Buffer

1

2

3

4

Note to Table1–34:

(1)This error specification is the absolute maximum and minimum error. For example, skew on 3 DQS delay buffer in a C2 speed grade is ±39ps.

C2

±13

±26

±39

±52

C3, I3

±14

±28

±42

±56

C4, C4L, I4, I4L

±15

±30

±45

±60

Unit

ps

ps

ps

ps

Stratix III Device Handbook, Volume 2

2024年4月4日发(作者：方从阳)

DC Characteristics

This section lists the input pin capacitances, on-chip termination tolerance, and

hot- socketing specifications.

Supply Current

Standby current is the current the device draws after the device is configured with no

inputs/outputs toggling and no activity in the device. Since these currents vary

largely with the resources used, use the Excel-based Early Power Estimator (EPE) to

get supply current estimates for your design.

Table1–4 lists supply current specifications for V

CC_CLKIN

and V

CCPGM

. Use the EPE to get

supply current estimates for remaining power supplies.

Table1– Current Specifications for V

CC_CLKIN

and V

CCPGM

Symbol

I

CLKIN

I

PGM

Parameter

V

CC_CLKIN

current specifications

V

CCPGM

current specifications

Min

0

0

Max

250

250

Unit

mA

mA

I/O Pin Leakage Current

Table1–5 defines StratixIII I/O Pin leakage current specifications.

Table1–xIII I/O Pin Leakage Current (Note1), (2)

Symbol

I

I

I

OZ

Parameter

Input Pin Leakage Current

Tri-stated I/O Pin Leakage

Current

Conditions

V

I

= V

CCIOMAX

to 0 V

V

O

= V

CCIOMAX

to 0 V

Min

-10

-10

Typ

—

—

Max

10

10

Unit

A

A

Notes to Table1–5:

(1)This value is specified for normal device operation. The value may vary during power-up. This applies for all V

CCIO

settings (3.3, 3.0, 2.5, 1.8, 1.5, and 1.2 V).

(2)10-A I/O leakage current limit is applicable when the internal clamping diode is off. A higher current can be

observed when the diode is on.

Bus Hold Specifications

Table1–7 shows the StratixIII device family bus hold specifications.

Table1– Hold Parameters(Part 1 of 2)

V

CCIO

ParameterSymbolConditions

1.2V

Min

Low sustaining

current

High sustaining

current

Low overdrive

current

I

SUSL

I

SUSH

I

ODL

V

IN

>V

IL

(maximum)

V

IN

IH

(minimum)

0V

IN

CCIO

Max

1.5V

MinMax

1.8V

MinMax

2.5V

MinMax

3.0V/3.3V

MinMax

µA

µA

µA

Unit

22.5 —

-22.5 —

—120

25.0 —

-25.0 —

—160

30.0 —

-30.0 —

—200

50.0 —

-50.0 —

—300

70.0 —

-70.0 —

—500

Stratix III Device Handbook, Volume 2

Chapter 1:StratixIII Device Data Sheet: DC and Switching Characteristics

Switching Characteristics

DLL and DQS Logic Block Specifications

Table1–32 describes the DLL frequency range specifications for StratixIII devices.

Table1–xIII DLL Frequency Range Specifications

Frequency

Mode

0

1

2

3

4

5

6

7

Frequency Range (MHz)

C2

90 – 150

120 – 200

150 – 240

180 – 300

240 – 370

290 – 450

360 – 560

470 – 740

C3, I3

90 – 140

120 – 190

150 – 230

180 – 290

240 – 350

290 – 420

360 – 530

470 – 700

C4, I4

90 – 120

120 – 170

150 – 200

180 – 250

240 – 310

290 – 370

360 – 460

470 – 610

C4L, I4L

90 – 120

120 – 170

150 – 200

180 – 250

240 – 310

290 – 370

360 – 460

470 – 610

Available Phase Shift

22.5°, 45°, 67.5°, 90°

30°, 60°, 90°, 120°

36°, 72°, 108°, 144°

45°, 90°,135°, 180°

30°, 60°, 90°,120°

36°, 72°, 108°, 144°

45°, 90°, 135°, 180°

60°, 120°, 180°, 240°

Number of

Delay Chains

16

12

10

8

12

10

8

6

DQS Delay

Buffer Mode (1)

Low

Low

Low

Low

High

High

High

High

Note to Table1–32:

(1)Low indicates 6-bit DQS delay setting, high indicates 5-bit DQS delay setting.

Table1–33 describes the average DQS phase offset delay per setting for StratixIII

devices.

Table1–e DQS Phase Offset Delay per Setting (Note1), (2), (3)

Speed Grade

C2

C3, I3

C4, I4

C4L, I4L

Notes to Table1–33:

(1)The valid settings for phase offset are -64 to +63 for frequency modes 0 to 3 and -32 to +31 for frequency modes

4 to 6.

(2)The typical value equals the average of the minimum and maximum values.

(3)The delay settings are linear with a cumulative delay variation of ±20ps for all speed grades. For example, when

using a C2 speed grade and applying 10° phase offset settings to a 90° phase shift at 400 MHz, the expected

minimum cumulative delay is [625 ps + (10*7 ps) - 20 ps] = 675 ps.

Min

7

7

7

7

Typ

10

11

11.5

11.5

Max

13

15

16

16

Unit

ps

ps

ps

ps

Table1–xIII DQS Phase Shift Error Specification for DLL-Delayed Clock (tDQS_PSERR) (Note1)

Number of DQS Delay

Buffer

1

2

3

4

Note to Table1–34:

(1)This error specification is the absolute maximum and minimum error. For example, skew on 3 DQS delay buffer in a C2 speed grade is ±39ps.

C2

±13

±26

±39

±52

C3, I3

±14

±28

±42

±56

C4, C4L, I4, I4L

±15

±30

±45

±60

Unit

ps

ps

ps

ps

Stratix III Device Handbook, Volume 2