2024年4月6日发(作者：箕雁风)
Performance Characteristics
This section provides the performance characteristics of some common functions and designs implemented in
Virtex-5 devices. The numbers reported here are worst-case values; they have all been fully characterized. These values are
subject to the same guidelines as the Switching Characteristics, page30. Table52 shows internal (register-to-register)
performance.
Table 52:Register-to-Register Performance
Register-to-Register (with I/O Delays)
Description
-3
Basic Functions
16:1 Multiplexer
32:1 Multiplexer
64:1 Multiplexer
9x9 Logic Multiplier with 4 pipe stages
9x9 Logic Multiplier with 5 pipe stages
16-bit Adder
32-bit Adder
64-bit Adder
Register to LUT to Register
16-bit Counter
32-bit Counter
64-bit Counter
Memory
Cascaded block RAM (64K)
Block RAM Pipelined
Single-Port 512x36 bits
Single-Port 4096x4 bits
Dual-Port A: 4096x4 bits and B: 1024x18 bits
Distributed RAM
Single-Port 16x8
Single-Port 32x8
Single-Port 64x8
Dual-Port 16x8
Shift Register Chain
16-bit
32-bit
64-bit
550
550
550
500
500
500
450
450
438
MHz
MHz
MHz
550
550
550
500
500
500
450
450
450
MHz
MHz
MHz
MHz
550
550
550
500
500
500
450
450
450
MHz
MHz
MHz
500450400MHz
550
550
511
468
550
550
550
423
550
550
550
428
500
500
467
438
500
500
500
377
500
500
500
381
450
450
407
428
428
450
447
323
450
450
450
333
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
SpeedGrade
-2-1
Units
DS202 (v5.5) June 17, 2016
Product Specification
Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
I/O Standard Adjustment Measurement Methodology
Input Delay Measurements
Table58 shows the test setup parameters used for measuring input delay.
Table 58:Input Delay Measurement Methodology
DS202 (v5.5) June 17, 2016
Product Specification
Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
Output Delay Measurements
Output delays are measured using a Tektronix P6245
TDS500/600 probe (<1pF) across approximately 4” of FR4
microstrip trace. Standard termination was used for all
testing. The propagation delay of the 4” trace is
characterized separately and subtracted from the final
measurement, and is therefore not included in the
generalized test setups shown in Figure11 and Figure12.
FPGA Output
+
C
REF
R
REF
V
MEAS
–
ds202_12_042808
V
REF
Figure 12:Differential Test Setup
Measurements and test conditions are reflected in the IBIS
models except where the IBIS format precludes it.
Parameters V
REF
, R
REF
, C
REF
, and V
MEAS
fully describe
the test conditions for each I/O standard. The most accurate
prediction of propagation delay in any given application can
be obtained through IBIS simulation, using the following
method:
te the output driver of choice into the generalized
test setup, using values from
Table59.
the time to V
MEAS
.
te the output driver of choice into the actual PCB
trace and load, using the appropriate IBIS model or
capacitance value to represent the load.
the time to V
MEAS
.
e the results of steps 2 and 4. The increase or
decrease in delay yields the actual propagation delay of
the PCB trace.
FPGA Output
R
REF
V
MEAS
(voltage level when taking
delay measurement)
C
REF
(probe capacitance)
DS202_06_111608
Figure 11:Single Ended Test Setup
Table 59:Output Delay Measurement Methodology
Description
LVTTL (Low-Voltage Transistor-Transistor Logic)
LVCMOS (Low-Voltage CMOS), 3.3V
LVCMOS, 2.5V
LVCMOS, 1.8V
LVCMOS, 1.5V
LVCMOS, 1.2V
PCI (Peripheral Component Interface), 33 MHz, 3.3V
PCI, 66 MHz, 3.3V
PCI-X, 133 MHz, 3.3V
GTL (Gunning Transceiver Logic)
GTL Plus
HSTL (High-Speed Transceiver Logic), Class I
HSTL, Class II
HSTL, Class III
DS202 (v5.5) June 17, 2016
Product Specification
I/O Standard
Attribute
LVTTL (all)
LVCMOS33
LVCMOS25
LVCMOS18
LVCMOS15
LVCMOS12
PCI33_3 (rising edge)
PCI33_3 (falling edge)
PCI66_3 (rising edge)
PCI66_3 (falling edge)
PCIX (rising edge)
PCIX (falling edge
GTL
GTLP
HSTL_I
HSTL_II
HSTL_III
R
REF
(Ω)
1M
1M
1M
1M
1M
1M
25
25
25
25
25
25
25
25
50
25
50
C
REF
(1)
(pF)
0
0
0
0
0
0
10
(2)
10
(2)
10
(2)
10
(2)
10
(3)
10
(3)
0
0
0
0
0
V
MEAS
(V)
1.4
1.65
1.25
0.9
0.75
0.6
0.94
2.03
0.94
2.03
0.94
2.03
0.8
1.0
V
REF
V
REF
0.9
V
REF
(V)
0
0
0
0
0
0
0
3.3
0
3.3
3.3
1.2
1.5
0.75
0.75
1.5
Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
Output Clock Jitter
Table 79:Output Clock Jitter
Symbol
Clock Synthesis Period Jitter
T
PERJITT_0
T
PERJITT_90
T
PERJITT_180
T
PERJITT_270
T
PERJITT_2X
T
PERJITT_DV1
T
PERJITT_DV2
T
PERJITT_FX
Notes:
for this parameter are available in the Architecture Wizard.
DescriptionConstraints
Speed Grade
-3
±120
±120
±120
±120
±200
±150
±300
Note 1
-2
±120
±120
±120
±120
±200
±150
±300
Note 1
-1
±120
±120
±120
±120
±230
±180
±345
Note 1
Units
CLK0
CLK90
CLK180
CLK270
CLK2X, CLK2X180
CLKDV (integer division)
CLKDV (non-integer division)
CLKFX, CLKFX180
ps
ps
ps
ps
ps
ps
ps
ps
Output Clock Phase Alignment
Table 80:Output Clock Phase Alignment
Symbol
Phase Offset Between CLKIN and CLKFB
T
IN_FB_OFFSET
T
OUT_OFFSET_1X
T
OUT_OFFSET_2X
T
OUT_OFFSET_FX
Duty Cycle Precision
(2)
T
DUTY_CYC_DLL
T
DUTY_CYC_FX
Notes:
1.
2.
3.
4.
All phase offsets are in respect to group CLK1X.
CLKOUT_DUTY_CYCLE_DLL applies to the 1X clock outputs (CLK0, CLK90, CLK180, and CLK270) only if
DUTY_CYCLE_CORRECTION=TRUE. The duty cycle distortion includes the global clock tree (BUFG).
DLL Outputs are used in these instances to describe the outputs: CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, and CLKDV.
DFS Outputs are used in these instances to describe the outputs: CLKFX and CLKFX180.
DescriptionConstraints
Speed Grade
-3
±50
±140
±150
±160
±150
±150
-2
±50
±140
±150
±160
±150
±150
-1
±60
±160
±200
±220
±180
±180
Units
CLKIN/CLKFB
CLK0, CLK90, CLK180, CLK270
CLK2X, CLK2X180, CLKDV
CLKFX, CLKFX180
DLL outputs
(3)
DFS outputs
(4)
ps
ps
ps
ps
ps
ps
Phase Offset Between Any DCM Outputs
(1)
DS202 (v5.5) June 17, 2016
Product Specification
Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
Table 81:Miscellaneous Timing Parameters
Symbol
Time Required to Achieve LOCK
T
DLL_240
T
DLL_120_240
T
DLL_60_120
T
DLL_50_60
T
DLL_40_50
T
DLL_30_40
T
DLL_24_30
T
DLL_30
T
FX_MIN
T
FX_MAX
T
DLL_FINE_SHIFT
Fine Phase Shifting
T
RANGE_MS
T
RANGE_MR
Delay Lines
T
TAP_MS_MIN
T
TAP_MS_MAX
T
TAP_MR_MIN
T
TAP_MR_MAX
Notes:
1.
2.
Description
Speed Grade
-3
80.00
250.00
900.00
1300.00
2000.00
3600.00
5000.00
5000.00
10.00
10.00
2.00
7.00
10.00
7.00
30.00
10.00
40.00
-2
80.00
250.00
900.00
1300.00
2000.00
3600.00
5000.00
5000.00
10.00
10.00
2.00
7.00
10.00
7.00
30.00
10.00
40.00
-1
80.00
250.00
900.00
1300.00
2000.00
3600.00
5000.00
5000.00
10.00
10.00
2.00
7.00
10.00
7.00
30.00
10.00
40.00
Units
µs
µs
µs
µs
µs
µs
µs
µs
ms
ms
DLL output – Frequency range > 240MHz
(1)
DLL output – Frequency range 120 - 240MHz
(1)
DLL output – Frequency range 60 - 120MHz
(1)
DLL output – Frequency range 50 - 60MHz
(1)
DLL output – Frequency range 40 - 50MHz
(1)
DLL output – Frequency range 30 - 40MHz
(1)
DLL output – Frequency range 24 - 30MHz
(1)
DLL output – Frequency range < 30MHz
(1)
DFS outputs
(2)
Multiplication factor for DLL lock time with Fine Shift
Absolute shifting range in maximum speed mode
Absolute shifting range in maximum range mode
Tap delay resolution (Min) in maximum speed mode
Tap delay resolution (Max) in maximum speed mode
Tap delay resolution (Min) in maximum range mode
Tap delay resolution (Max) in maximum range mode
ns
ns
ps
ps
ps
ps
DLL Outputs are used in these instances to describe the outputs: CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, and CLKDV.
DFS Outputs are used in these instances to describe the outputs: CLKFX and CLKFX180.
Table 82:Frequency Synthesis
Attribute
CLKFX_MULTIPLY
CLKFX_DIVIDE
Min
2
1
Max
33
32
Table 83:DCM Switching Characteristics
Symbol
T
DMCCK_PSEN
/ T
DMCKC_PSEN
T
DMCCK_PSINCDEC
/ T
DMCKC_PSINCDEC
T
DMCKO_PSDONE
Description
PSEN Setup/Hold
PSINCDEC Setup/Hold
Clock to out of PSDONE
Speed Grade
-3
1.20
0.00
1.20
0.00
1.00
-2
1.35
0.00
1.35
0.00
1.12
-1
1.56
0.00
1.56
0.00
1.30
Units
ns
ns
ns
DS202 (v5.5) June 17, 2016
Product Specification
2024年4月6日发(作者：箕雁风)
Performance Characteristics
This section provides the performance characteristics of some common functions and designs implemented in
Virtex-5 devices. The numbers reported here are worst-case values; they have all been fully characterized. These values are
subject to the same guidelines as the Switching Characteristics, page30. Table52 shows internal (register-to-register)
performance.
Table 52:Register-to-Register Performance
Register-to-Register (with I/O Delays)
Description
-3
Basic Functions
16:1 Multiplexer
32:1 Multiplexer
64:1 Multiplexer
9x9 Logic Multiplier with 4 pipe stages
9x9 Logic Multiplier with 5 pipe stages
16-bit Adder
32-bit Adder
64-bit Adder
Register to LUT to Register
16-bit Counter
32-bit Counter
64-bit Counter
Memory
Cascaded block RAM (64K)
Block RAM Pipelined
Single-Port 512x36 bits
Single-Port 4096x4 bits
Dual-Port A: 4096x4 bits and B: 1024x18 bits
Distributed RAM
Single-Port 16x8
Single-Port 32x8
Single-Port 64x8
Dual-Port 16x8
Shift Register Chain
16-bit
32-bit
64-bit
550
550
550
500
500
500
450
450
438
MHz
MHz
MHz
550
550
550
500
500
500
450
450
450
MHz
MHz
MHz
MHz
550
550
550
500
500
500
450
450
450
MHz
MHz
MHz
500450400MHz
550
550
511
468
550
550
550
423
550
550
550
428
500
500
467
438
500
500
500
377
500
500
500
381
450
450
407
428
428
450
447
323
450
450
450
333
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
SpeedGrade
-2-1
Units
DS202 (v5.5) June 17, 2016
Product Specification
Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
I/O Standard Adjustment Measurement Methodology
Input Delay Measurements
Table58 shows the test setup parameters used for measuring input delay.
Table 58:Input Delay Measurement Methodology
DS202 (v5.5) June 17, 2016
Product Specification
Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
Output Delay Measurements
Output delays are measured using a Tektronix P6245
TDS500/600 probe (<1pF) across approximately 4” of FR4
microstrip trace. Standard termination was used for all
testing. The propagation delay of the 4” trace is
characterized separately and subtracted from the final
measurement, and is therefore not included in the
generalized test setups shown in Figure11 and Figure12.
FPGA Output
+
C
REF
R
REF
V
MEAS
–
ds202_12_042808
V
REF
Figure 12:Differential Test Setup
Measurements and test conditions are reflected in the IBIS
models except where the IBIS format precludes it.
Parameters V
REF
, R
REF
, C
REF
, and V
MEAS
fully describe
the test conditions for each I/O standard. The most accurate
prediction of propagation delay in any given application can
be obtained through IBIS simulation, using the following
method:
te the output driver of choice into the generalized
test setup, using values from
Table59.
the time to V
MEAS
.
te the output driver of choice into the actual PCB
trace and load, using the appropriate IBIS model or
capacitance value to represent the load.
the time to V
MEAS
.
e the results of steps 2 and 4. The increase or
decrease in delay yields the actual propagation delay of
the PCB trace.
FPGA Output
R
REF
V
MEAS
(voltage level when taking
delay measurement)
C
REF
(probe capacitance)
DS202_06_111608
Figure 11:Single Ended Test Setup
Table 59:Output Delay Measurement Methodology
Description
LVTTL (Low-Voltage Transistor-Transistor Logic)
LVCMOS (Low-Voltage CMOS), 3.3V
LVCMOS, 2.5V
LVCMOS, 1.8V
LVCMOS, 1.5V
LVCMOS, 1.2V
PCI (Peripheral Component Interface), 33 MHz, 3.3V
PCI, 66 MHz, 3.3V
PCI-X, 133 MHz, 3.3V
GTL (Gunning Transceiver Logic)
GTL Plus
HSTL (High-Speed Transceiver Logic), Class I
HSTL, Class II
HSTL, Class III
DS202 (v5.5) June 17, 2016
Product Specification
I/O Standard
Attribute
LVTTL (all)
LVCMOS33
LVCMOS25
LVCMOS18
LVCMOS15
LVCMOS12
PCI33_3 (rising edge)
PCI33_3 (falling edge)
PCI66_3 (rising edge)
PCI66_3 (falling edge)
PCIX (rising edge)
PCIX (falling edge
GTL
GTLP
HSTL_I
HSTL_II
HSTL_III
R
REF
(Ω)
1M
1M
1M
1M
1M
1M
25
25
25
25
25
25
25
25
50
25
50
C
REF
(1)
(pF)
0
0
0
0
0
0
10
(2)
10
(2)
10
(2)
10
(2)
10
(3)
10
(3)
0
0
0
0
0
V
MEAS
(V)
1.4
1.65
1.25
0.9
0.75
0.6
0.94
2.03
0.94
2.03
0.94
2.03
0.8
1.0
V
REF
V
REF
0.9
V
REF
(V)
0
0
0
0
0
0
0
3.3
0
3.3
3.3
1.2
1.5
0.75
0.75
1.5
Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
Output Clock Jitter
Table 79:Output Clock Jitter
Symbol
Clock Synthesis Period Jitter
T
PERJITT_0
T
PERJITT_90
T
PERJITT_180
T
PERJITT_270
T
PERJITT_2X
T
PERJITT_DV1
T
PERJITT_DV2
T
PERJITT_FX
Notes:
for this parameter are available in the Architecture Wizard.
DescriptionConstraints
Speed Grade
-3
±120
±120
±120
±120
±200
±150
±300
Note 1
-2
±120
±120
±120
±120
±200
±150
±300
Note 1
-1
±120
±120
±120
±120
±230
±180
±345
Note 1
Units
CLK0
CLK90
CLK180
CLK270
CLK2X, CLK2X180
CLKDV (integer division)
CLKDV (non-integer division)
CLKFX, CLKFX180
ps
ps
ps
ps
ps
ps
ps
ps
Output Clock Phase Alignment
Table 80:Output Clock Phase Alignment
Symbol
Phase Offset Between CLKIN and CLKFB
T
IN_FB_OFFSET
T
OUT_OFFSET_1X
T
OUT_OFFSET_2X
T
OUT_OFFSET_FX
Duty Cycle Precision
(2)
T
DUTY_CYC_DLL
T
DUTY_CYC_FX
Notes:
1.
2.
3.
4.
All phase offsets are in respect to group CLK1X.
CLKOUT_DUTY_CYCLE_DLL applies to the 1X clock outputs (CLK0, CLK90, CLK180, and CLK270) only if
DUTY_CYCLE_CORRECTION=TRUE. The duty cycle distortion includes the global clock tree (BUFG).
DLL Outputs are used in these instances to describe the outputs: CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, and CLKDV.
DFS Outputs are used in these instances to describe the outputs: CLKFX and CLKFX180.
DescriptionConstraints
Speed Grade
-3
±50
±140
±150
±160
±150
±150
-2
±50
±140
±150
±160
±150
±150
-1
±60
±160
±200
±220
±180
±180
Units
CLKIN/CLKFB
CLK0, CLK90, CLK180, CLK270
CLK2X, CLK2X180, CLKDV
CLKFX, CLKFX180
DLL outputs
(3)
DFS outputs
(4)
ps
ps
ps
ps
ps
ps
Phase Offset Between Any DCM Outputs
(1)
DS202 (v5.5) June 17, 2016
Product Specification
Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
Table 81:Miscellaneous Timing Parameters
Symbol
Time Required to Achieve LOCK
T
DLL_240
T
DLL_120_240
T
DLL_60_120
T
DLL_50_60
T
DLL_40_50
T
DLL_30_40
T
DLL_24_30
T
DLL_30
T
FX_MIN
T
FX_MAX
T
DLL_FINE_SHIFT
Fine Phase Shifting
T
RANGE_MS
T
RANGE_MR
Delay Lines
T
TAP_MS_MIN
T
TAP_MS_MAX
T
TAP_MR_MIN
T
TAP_MR_MAX
Notes:
1.
2.
Description
Speed Grade
-3
80.00
250.00
900.00
1300.00
2000.00
3600.00
5000.00
5000.00
10.00
10.00
2.00
7.00
10.00
7.00
30.00
10.00
40.00
-2
80.00
250.00
900.00
1300.00
2000.00
3600.00
5000.00
5000.00
10.00
10.00
2.00
7.00
10.00
7.00
30.00
10.00
40.00
-1
80.00
250.00
900.00
1300.00
2000.00
3600.00
5000.00
5000.00
10.00
10.00
2.00
7.00
10.00
7.00
30.00
10.00
40.00
Units
µs
µs
µs
µs
µs
µs
µs
µs
ms
ms
DLL output – Frequency range > 240MHz
(1)
DLL output – Frequency range 120 - 240MHz
(1)
DLL output – Frequency range 60 - 120MHz
(1)
DLL output – Frequency range 50 - 60MHz
(1)
DLL output – Frequency range 40 - 50MHz
(1)
DLL output – Frequency range 30 - 40MHz
(1)
DLL output – Frequency range 24 - 30MHz
(1)
DLL output – Frequency range < 30MHz
(1)
DFS outputs
(2)
Multiplication factor for DLL lock time with Fine Shift
Absolute shifting range in maximum speed mode
Absolute shifting range in maximum range mode
Tap delay resolution (Min) in maximum speed mode
Tap delay resolution (Max) in maximum speed mode
Tap delay resolution (Min) in maximum range mode
Tap delay resolution (Max) in maximum range mode
ns
ns
ps
ps
ps
ps
DLL Outputs are used in these instances to describe the outputs: CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, and CLKDV.
DFS Outputs are used in these instances to describe the outputs: CLKFX and CLKFX180.
Table 82:Frequency Synthesis
Attribute
CLKFX_MULTIPLY
CLKFX_DIVIDE
Min
2
1
Max
33
32
Table 83:DCM Switching Characteristics
Symbol
T
DMCCK_PSEN
/ T
DMCKC_PSEN
T
DMCCK_PSINCDEC
/ T
DMCKC_PSINCDEC
T
DMCKO_PSDONE
Description
PSEN Setup/Hold
PSINCDEC Setup/Hold
Clock to out of PSDONE
Speed Grade
-3
1.20
0.00
1.20
0.00
1.00
-2
1.35
0.00
1.35
0.00
1.12
-1
1.56
0.00
1.56
0.00
1.30
Units
ns
ns
ns
DS202 (v5.5) June 17, 2016
Product Specification