FPGA可编程逻辑器件芯片EP1S60F1020I6N中文规格书-USB迷|专注于互联网分享

2024年10月31日发(作者：望雪卉)

MultiTrack

Interconnect

Clear and Preset Logic Control

LAB-wide signals control the logic for the register’s clear and load/preset

signals. The ALM directly supports an asynchronous clear and preset

function. The register preset is achieved through the asynchronous load

of a logic high. The direct asynchronous preset does not require a NOT

gate push-back technique. Stratix II GX devices support simultaneous

asynchronous load/preset and clear signals. An asynchronous clear

signal takes precedence if both signals are asserted simultaneously. Each

LAB supports up to two clears and one load/preset signal.

In addition to the clear and load/preset ports, Stratix II GX devices

provide a device-wide reset pin (DEV_CLRn) that resets all registers in the

device. An option set before compilation in the Quartus II software

controls this pin. This device-wide reset overrides all other control

signals.

In the Stratix II GX architecture, the MultiTrack interconnect structure

with DirectDrive technology provides connections between ALMs,

TriMatrix memory, DSP blocks, and device I/O pins. The MultiTrack

interconnect consists of continuous, performance-optimized routing lines

of different lengths and speeds used for inter- and intra-design block

connectivity. The Quartus II Compiler automatically places critical design

paths on faster interconnects to improve design performance.

DirectDrive technology is a deterministic routing technology that ensures

identical routing resource usage for any function regardless of placement

in the device. The MultiTrack interconnect and DirectDrive technology

simplify the integration stage of block-based designing by eliminating the

re-optimization cycles that typically follow design changes and

additions.

The MultiTrack interconnect consists of row and column interconnects

that span fixed distances. A routing structure with fixed length resources

for all devices allows predictable and repeatable performance when

migrating through different device densities. Dedicated row

interconnects route signals to and from LABs, DSP blocks, and TriMatrix

memory in the same row.

These row resources include:

■

Direct link interconnects between LABs and adjacent blocks

■

R4 interconnects traversing four blocks to the right or left

■

R24 row interconnects for high-speed access across the length of the

device

Stratix II GX Device Handbook, Volume 1

TriMatrix Memory

Table2–rix Memory Features(Part 2 of2)

Memory Feature

Simple dual-port memory

mixed width support

True dual-port memory

mixed width support

Power-up conditions

Mixed-port read-during-write

Configurations

Outputs cleared

Output registers

512 × 1

256 × 2

128 × 4

64 × 8

64 × 9

32 × 16

32 × 18

M512 RAM Block

(32×18 Bits)

M4K RAM Block

(128×36 Bits)

Outputs cleared

Output registers

4K × 1

2K × 2

1K × 4

512 × 8

512 × 9

256 × 16

256 × 18

128 × 32

128 × 36

M-RAM Block

(4K×144Bits)

Outputs unknown

Output registers

Unknown output

64K × 8

64K × 9

32K × 16

32K × 18

16K × 32

16K × 36

8K × 64

8K × 72

4K × 128

4K × 144

Unknown output/old dataUnknown output/old data

Note to Table2–19:

(1)Violating the setup or hold time on the memory block address registers could corrupt memory contents. This

applies to both read and write operations.

TriMatrix memory provides three different memory sizes for efficient

application support. The Quartus II software automatically partitions the

user-defined memory into the embedded memory blocks using the most

efficient size combinations. You can also manually assign the memory to

a specific block size or a mixture of block sizes.

M512 RAM Block

The M512 RAM block is a simple dual-port memory block and is useful

for implementing small FIFO buffers, DSP, and clock domain transfer

applications. Each block contains 576 RAM bits (including parity bits).

M512 RAM blocks can be configured in the following modes:

■

Simple dual-port RAM

Single-port RAM

FIFO

ROM

Shift register

When configured as RAM or ROM, you can use an initialization file to

pre-load the memory contents.

Stratix II GX Device Handbook, Volume 1

Stratix II GX Architecture

Stratix II GX Device Handbook, Volume 1

Stratix II GX Architecture

Stratix II GX Device Handbook, Volume 1

PLLs and Clock Networks

Figure2–2SGX60, EP2SGX90 and EP2SGX130 Device I/O Clock Groups

IO_CLKA[7..0]IO_CLKB[7..0]

IO_CLKC[7..0]IO_CLKD[7..0]

8888

I/O Clock Regions

IO_CLKP[7..0]

24 Clocks in the

Quadrant

24 Clocks in the

Quadrant

IO_CLKE[7..0]

IO_CLKO[7..0]

IO_CLKF[7..0]

IO_CLKN[7..0]

24 Clocks in the

Quadrant

24 Clocks in the

Quadrant

IO_CLKG[7..0]

IO_CLKM[7..0]

IO_CLKH[7..0]

8888

IO_CLKL[7..0]IO_CLKK[7..0]IO_CLKJ[7..0]IO_CLKI[7..0]

You can use the Quartus II software to control whether a clock input pin

drives either a global, regional, or dual-regional clock network. The

Quartus II software automatically selects the clocking resources if not

specified.

Clock Control Block

Each global clock, regional clock, and PLL external clock output has its

own clock control block. The control block has two functions:

■

Clock source selection (dynamic selection for global clocks)

Clock power-down (dynamic clock enable or disable)