2024年4月13日发(作者：泉晴雪)
DS890 (v3.13) July 21, 2020Product Specification
General Description
Xilinx® UltraScale™ architecture comprises high-performance FPGA, MPSoC, and RFSoC families that address a vast spectrum of
system requirements with a focus on lowering total power consumption through numerous innovative technological
advancements.
Kintex® UltraScale FPGAs: High-performance FPGAs with a focus on price/performance, using both monolithic and
next-generation stacked silicon interconnect (SSI) technology. High DSP and blockRAM-to-logic ratios and next-generation
transceivers, combined with low-cost packaging, enable an optimum blend of capability and cost.
Kintex UltraScale+™ FPGAs: Increased performance and on-chip UltraRAM memory to reduce BOM cost. The ideal mix of
high-performance peripherals and cost-effective system implementation. Kintex UltraScale+ FPGAs have numerous power
options that deliver the optimal balance between the required system performance and the smallest power envelope.
Virtex® UltraScale FPGAs: High-capacity, high-performance FPGAs enabled using both monolithic and next-generation SSI
technology. Virtex UltraScale devices achieve the highest system capacity, bandwidth, and performance to address key market and
application requirements through integration of various system-level functions.
Virtex UltraScale+ FPGAs: The highest transceiver bandwidth, highest DSP count, and highest on-chip and in-package memory
available in the UltraScale architecture. Virtex UltraScale+ FPGAs also provide numerous power options that deliver the optimal
balance between the required system performance and the smallest power envelope.
Zynq® UltraScale+ MPSoCs: Combine the Arm® v8-based Cortex®-A53 high-performance energy-efficient 64-bit application
processor with the Arm Cortex-R5F real-time processor and the UltraScale architecture to create the industry's first
programmable MPSoCs. Provide unprecedented power savings, heterogeneous processing, and programmable acceleration.
Zynq® UltraScale+ RFSoCs: Combine RF data converter subsystem and forward error correction with industry-leading
programmable logic and heterogeneous processing capability. Integrated RF-ADCs, RF-DACs, and soft-decision FECs (SD-FEC)
provide the key subsystems for multiband, multi-mode cellular radios and cable infrastructure.
Family Comparisons
Table 1:Device Resources
Kintex
UltraScale
FPGA
MPSoC Processing System
RF-ADC/DAC
SD-FEC
System Logic Cells (K)
Block Memory (Mb)
UltraRAM (Mb)
HBM DRAM (GB)
DSP (Slices)
DSP Performance (GMAC/s)
Transceivers
Max. Transceiver Speed (Gb/s)
Max. Serial Bandwidth (full duplex) (Gb/s)
Memory Interface Performance (Mb/s)
I/O Pins
768–5,520
8,180
12–64
16.3
2,086
2,400
312–832
1,368–3,528
6,287
16–76
32.75
3,268
2,666
280–668
600–2,880
4,268
36–120
30.5
5,616
2,400
338–1,456
318–1,451
12.7–75.9
356–1,843
12.7–60.8
0–81
783–5,541
44.3–132.9
862–8,938
23.6–94.5
90–360
0–16
1,320–12,288
21,897
32–128
58.0
8,384
2,666
208–2,072
240–3,528
6,287
0–72
32.75
3,268
2,666
82–668
3,145–4,272
7,613
8–16
32.75
1,048
2,666
280–408
103–1,143
4.5–34.6
0–36
Kintex
UltraScale+
FPGA
Virtex
UltraScale
FPGA
Virtex
UltraScale+
FPGA
Zynq
UltraScale+
MPSoC
✓
Zynq
UltraScale+
RFSoC
✓
✓
✓
678–930
27.8–38.0
13.5–22.5
DS890 (v3.13) July 21, 2020
Product Specification
UltraScale Architecture and Product Data Sheet: Overview
VirtexUltraScale Device-Package Combinations and Maximum I/Os
Table 8:VirtexUltraScale Device-Package Combinations and Maximum I/Os
Package
(1)(2)(3)
Package
Dimensions
(mm)
40x40
40x40
40x40
42.5x42.5
42.5x42.5
47.5x47.5
47.5x47.5
47.5x47.5
47.5x47.5
47.5x47.5
47.5x47.5
47.5x47.5
47.5x47.5
50x50
52.5x52.5
55x55
0, 448
60, 60
52, 1404
48, 0
52, 364
32, 32
52, 364
40,40
52, 364
52,52
52, 364
52, 52
52, 1248
36, 0
52, 650
32,32
52, 650
32,32
52, 650
40,36
52, 650
40,36
52, 650
40, 36
52, 780
28, 24
52, 780
28,24
52, 780
28,24
52, 650
32,16
52, 650
32,16
52, 650
36,16
VU065
HR, HP
GTH, GTY
52, 468
20,20
VU080
HR, HP
GTH, GTY
52, 468
20,20
52, 286
32,32
VU095
HR, HP
GTH, GTY
52, 468
20,20
52, 286
32,32
52, 286
40, 32
VU125
HR, HP
GTH, GTY
VU160
HR, HP
GTH, GTY
VU190
HR, HP
GTH, GTY
VU440
HR, HP
GTH, GTY
FFVC1517
FFVD1517
FLVD1517
FFVB1760
FLVB1760
FFVA2104
FLVA2104
FFVB2104
FLVB2104
FLGB2104
FFVC2104
FLVC2104
FLGC2104
FLGB2377
FLGA2577
FLGA2892
Notes:
1.
2.
3.
Go to Ordering Information for package designation details.
All packages have 1.0mm ball pitch.
Packages with the same last letter and number sequence, e.g., A2104, are footprint compatible with all other UltraScale
architecture-based devices with the same sequence. The footprint compatible devices within this family are
outlined. See the
UltraScale Architecture Product Selection Guide
for details on inter-family migration.
DS890 (v3.13) July 21, 2020
Product Specification
2024年4月13日发(作者：泉晴雪)
DS890 (v3.13) July 21, 2020Product Specification
General Description
Xilinx® UltraScale™ architecture comprises high-performance FPGA, MPSoC, and RFSoC families that address a vast spectrum of
system requirements with a focus on lowering total power consumption through numerous innovative technological
advancements.
Kintex® UltraScale FPGAs: High-performance FPGAs with a focus on price/performance, using both monolithic and
next-generation stacked silicon interconnect (SSI) technology. High DSP and blockRAM-to-logic ratios and next-generation
transceivers, combined with low-cost packaging, enable an optimum blend of capability and cost.
Kintex UltraScale+™ FPGAs: Increased performance and on-chip UltraRAM memory to reduce BOM cost. The ideal mix of
high-performance peripherals and cost-effective system implementation. Kintex UltraScale+ FPGAs have numerous power
options that deliver the optimal balance between the required system performance and the smallest power envelope.
Virtex® UltraScale FPGAs: High-capacity, high-performance FPGAs enabled using both monolithic and next-generation SSI
technology. Virtex UltraScale devices achieve the highest system capacity, bandwidth, and performance to address key market and
application requirements through integration of various system-level functions.
Virtex UltraScale+ FPGAs: The highest transceiver bandwidth, highest DSP count, and highest on-chip and in-package memory
available in the UltraScale architecture. Virtex UltraScale+ FPGAs also provide numerous power options that deliver the optimal
balance between the required system performance and the smallest power envelope.
Zynq® UltraScale+ MPSoCs: Combine the Arm® v8-based Cortex®-A53 high-performance energy-efficient 64-bit application
processor with the Arm Cortex-R5F real-time processor and the UltraScale architecture to create the industry's first
programmable MPSoCs. Provide unprecedented power savings, heterogeneous processing, and programmable acceleration.
Zynq® UltraScale+ RFSoCs: Combine RF data converter subsystem and forward error correction with industry-leading
programmable logic and heterogeneous processing capability. Integrated RF-ADCs, RF-DACs, and soft-decision FECs (SD-FEC)
provide the key subsystems for multiband, multi-mode cellular radios and cable infrastructure.
Family Comparisons
Table 1:Device Resources
Kintex
UltraScale
FPGA
MPSoC Processing System
RF-ADC/DAC
SD-FEC
System Logic Cells (K)
Block Memory (Mb)
UltraRAM (Mb)
HBM DRAM (GB)
DSP (Slices)
DSP Performance (GMAC/s)
Transceivers
Max. Transceiver Speed (Gb/s)
Max. Serial Bandwidth (full duplex) (Gb/s)
Memory Interface Performance (Mb/s)
I/O Pins
768–5,520
8,180
12–64
16.3
2,086
2,400
312–832
1,368–3,528
6,287
16–76
32.75
3,268
2,666
280–668
600–2,880
4,268
36–120
30.5
5,616
2,400
338–1,456
318–1,451
12.7–75.9
356–1,843
12.7–60.8
0–81
783–5,541
44.3–132.9
862–8,938
23.6–94.5
90–360
0–16
1,320–12,288
21,897
32–128
58.0
8,384
2,666
208–2,072
240–3,528
6,287
0–72
32.75
3,268
2,666
82–668
3,145–4,272
7,613
8–16
32.75
1,048
2,666
280–408
103–1,143
4.5–34.6
0–36
Kintex
UltraScale+
FPGA
Virtex
UltraScale
FPGA
Virtex
UltraScale+
FPGA
Zynq
UltraScale+
MPSoC
✓
Zynq
UltraScale+
RFSoC
✓
✓
✓
678–930
27.8–38.0
13.5–22.5
DS890 (v3.13) July 21, 2020
Product Specification
UltraScale Architecture and Product Data Sheet: Overview
VirtexUltraScale Device-Package Combinations and Maximum I/Os
Table 8:VirtexUltraScale Device-Package Combinations and Maximum I/Os
Package
(1)(2)(3)
Package
Dimensions
(mm)
40x40
40x40
40x40
42.5x42.5
42.5x42.5
47.5x47.5
47.5x47.5
47.5x47.5
47.5x47.5
47.5x47.5
47.5x47.5
47.5x47.5
47.5x47.5
50x50
52.5x52.5
55x55
0, 448
60, 60
52, 1404
48, 0
52, 364
32, 32
52, 364
40,40
52, 364
52,52
52, 364
52, 52
52, 1248
36, 0
52, 650
32,32
52, 650
32,32
52, 650
40,36
52, 650
40,36
52, 650
40, 36
52, 780
28, 24
52, 780
28,24
52, 780
28,24
52, 650
32,16
52, 650
32,16
52, 650
36,16
VU065
HR, HP
GTH, GTY
52, 468
20,20
VU080
HR, HP
GTH, GTY
52, 468
20,20
52, 286
32,32
VU095
HR, HP
GTH, GTY
52, 468
20,20
52, 286
32,32
52, 286
40, 32
VU125
HR, HP
GTH, GTY
VU160
HR, HP
GTH, GTY
VU190
HR, HP
GTH, GTY
VU440
HR, HP
GTH, GTY
FFVC1517
FFVD1517
FLVD1517
FFVB1760
FLVB1760
FFVA2104
FLVA2104
FFVB2104
FLVB2104
FLGB2104
FFVC2104
FLVC2104
FLGC2104
FLGB2377
FLGA2577
FLGA2892
Notes:
1.
2.
3.
Go to Ordering Information for package designation details.
All packages have 1.0mm ball pitch.
Packages with the same last letter and number sequence, e.g., A2104, are footprint compatible with all other UltraScale
architecture-based devices with the same sequence. The footprint compatible devices within this family are
outlined. See the
UltraScale Architecture Product Selection Guide
for details on inter-family migration.
DS890 (v3.13) July 21, 2020
Product Specification