2024年4月14日发(作者：漫浩邈)
Memory Module Specifications
KVR1333D3D8R9S/4GHB
4GB 512M x 72-Bit PC3-10600
CL9 Registered w/Parity 240-Pin DIMM
DESCRIPTION
This document describes ValueRAM’s 512M x 72-bit (4GB)
DDR3-1333MHz CL9 SDRAM (Synchronous DRAM) regis-
tered w/parity, dual-rank memory module, based on eighteen
256M x 8-bit DDR3-1333MHz FBGA components. The SPD is
programmed to JEDEC standard latency 1333MHz timing of
9-9-9 at 1.5V. This 240-pin DIMM uses gold contact fingers and
requires +1.5V. The electrical and mechanical specifications
are as follows:
DRAM Supported: Hynix B-Die
SPECIFICATIONS
CL(IDD)
Row Cycle Time (tRCmin)
Refresh to Active/Refresh
Command Time (tRFCmin)
Row Active Time (tRASmin)
Power
UL Rating
Operating Temperature
Storage Temperature
9 cycles
49.5ns (min.)
160ns (min.)
36ns (min.)
2.812 W (operating)
94 V - 0
0° C to 85° C
-55° C to +100° C
FEATURES
• JEDEC standard 1.5V ± 0.075V Power Supply
• VDDQ = 1.5V ± 0.075V
• 667MHz fCK for 1333Mb/sec/pin
• 8 independent internal bank
• Programmable CAS Latency: 6,7,8,9,10
• Programmable Additive Latency: 0, CL - 2, or CL - 1 clock
• Programmable CAS Write Latency(CWL) = 7 (DDR3-1333)
• 8-bit pre-fetch
• Burst Length: 8 (Interleave without any limit, sequential with
starting address “000” only), 4 with tCCD = 4 which does
not allow seamless read or write [either on the fly using A12
or MRS]
• Bi-directional Differential Data Strobe
• Internal (self) calibration : Internal self calibration through ZQ
pin (RZQ : 240 ohm ± 1%)
• On Die Termination using ODT pin
• On-DIMM thermal sensor (Grade B)
• Average Refresh Period 7.8us at lower than TCASE 85°C,
3.9us at 85°C < TCASE ≤ 95°C
• Asynchronous Reset
• PCB : Height 1.180” (30.00mm), double sided component
Continued >>
Document No. VALUERAM0948-001.A00 12/06/10 Page 1
continuedValueRAM
MODULE DIMENSIONS:
(units = millimeters)
Document No. VALUERAM0948-001.A00 12/06/10 Page 2
2024年4月14日发(作者：漫浩邈)
Memory Module Specifications
KVR1333D3D8R9S/4GHB
4GB 512M x 72-Bit PC3-10600
CL9 Registered w/Parity 240-Pin DIMM
DESCRIPTION
This document describes ValueRAM’s 512M x 72-bit (4GB)
DDR3-1333MHz CL9 SDRAM (Synchronous DRAM) regis-
tered w/parity, dual-rank memory module, based on eighteen
256M x 8-bit DDR3-1333MHz FBGA components. The SPD is
programmed to JEDEC standard latency 1333MHz timing of
9-9-9 at 1.5V. This 240-pin DIMM uses gold contact fingers and
requires +1.5V. The electrical and mechanical specifications
are as follows:
DRAM Supported: Hynix B-Die
SPECIFICATIONS
CL(IDD)
Row Cycle Time (tRCmin)
Refresh to Active/Refresh
Command Time (tRFCmin)
Row Active Time (tRASmin)
Power
UL Rating
Operating Temperature
Storage Temperature
9 cycles
49.5ns (min.)
160ns (min.)
36ns (min.)
2.812 W (operating)
94 V - 0
0° C to 85° C
-55° C to +100° C
FEATURES
• JEDEC standard 1.5V ± 0.075V Power Supply
• VDDQ = 1.5V ± 0.075V
• 667MHz fCK for 1333Mb/sec/pin
• 8 independent internal bank
• Programmable CAS Latency: 6,7,8,9,10
• Programmable Additive Latency: 0, CL - 2, or CL - 1 clock
• Programmable CAS Write Latency(CWL) = 7 (DDR3-1333)
• 8-bit pre-fetch
• Burst Length: 8 (Interleave without any limit, sequential with
starting address “000” only), 4 with tCCD = 4 which does
not allow seamless read or write [either on the fly using A12
or MRS]
• Bi-directional Differential Data Strobe
• Internal (self) calibration : Internal self calibration through ZQ
pin (RZQ : 240 ohm ± 1%)
• On Die Termination using ODT pin
• On-DIMM thermal sensor (Grade B)
• Average Refresh Period 7.8us at lower than TCASE 85°C,
3.9us at 85°C < TCASE ≤ 95°C
• Asynchronous Reset
• PCB : Height 1.180” (30.00mm), double sided component
Continued >>
Document No. VALUERAM0948-001.A00 12/06/10 Page 1
continuedValueRAM
MODULE DIMENSIONS:
(units = millimeters)
Document No. VALUERAM0948-001.A00 12/06/10 Page 2