2024年4月23日发(作者：风欣悦)
UltraScale Architecture and
Product Data Sheet: Overview
DS890 (v3.13) July 21, 2020Product Specification
General Description
Xilinx® UltraScale™ architecture comprises high-performance FPGA, MPSoC, and RFSoC families that address a vast spectrum of
system requirements with a focus on lowering total power consumption through numerous innovative technological
advancements.
Kintex® UltraScale FPGAs: High-performance FPGAs with a focus on price/performance, using both monolithic and
next-generation stacked silicon interconnect (SSI) technology. High DSP and blockRAM-to-logic ratios and next-generation
transceivers, combined with low-cost packaging, enable an optimum blend of capability and cost.
Kintex UltraScale+™ FPGAs: Increased performance and on-chip UltraRAM memory to reduce BOM cost. The ideal mix of
high-performance peripherals and cost-effective system implementation. Kintex UltraScale+ FPGAs have numerous power
options that deliver the optimal balance between the required system performance and the smallest power envelope.
Virtex® UltraScale FPGAs: High-capacity, high-performance FPGAs enabled using both monolithic and next-generation SSI
technology. Virtex UltraScale devices achieve the highest system capacity, bandwidth, and performance to address key market and
application requirements through integration of various system-level functions.
Virtex UltraScale+ FPGAs: The highest transceiver bandwidth, highest DSP count, and highest on-chip and in-package memory
available in the UltraScale architecture. Virtex UltraScale+ FPGAs also provide numerous power options that deliver the optimal
balance between the required system performance and the smallest power envelope.
Zynq® UltraScale+ MPSoCs: Combine the Arm® v8-based Cortex®-A53 high-performance energy-efficient 64-bit application
processor with the Arm Cortex-R5F real-time processor and the UltraScale architecture to create the industry's first
programmable MPSoCs. Provide unprecedented power savings, heterogeneous processing, and programmable acceleration.
Zynq® UltraScale+ RFSoCs: Combine RF data converter subsystem and forward error correction with industry-leading
programmable logic and heterogeneous processing capability. Integrated RF-ADCs, RF-DACs, and soft-decision FECs (SD-FEC)
provide the key subsystems for multiband, multi-mode cellular radios and cable infrastructure.
Family Comparisons
Table 1:Device Resources
Kintex
UltraScale
FPGA
MPSoC Processing System
RF-ADC/DAC
SD-FEC
System Logic Cells (K)
Block Memory (Mb)
UltraRAM (Mb)
HBM DRAM (GB)
DSP (Slices)
DSP Performance (GMAC/s)
Transceivers
Max. Transceiver Speed (Gb/s)
Max. Serial Bandwidth (full duplex) (Gb/s)
Memory Interface Performance (Mb/s)
I/O Pins
768–5,520
8,180
12–64
16.3
2,086
2,400
312–832
1,368–3,528
6,287
16–76
32.75
3,268
2,666
280–668
600–2,880
4,268
36–120
30.5
5,616
2,400
338–1,456
318–1,451
12.7–75.9
356–1,843
12.7–60.8
0–81
783–5,541
44.3–132.9
862–8,938
23.6–94.5
90–360
0–16
1,320–12,288
21,897
32–128
58.0
8,384
2,666
208–2,072
240–3,528
6,287
0–72
32.75
3,268
2,666
82–668
3,145–4,272
7,613
8–16
32.75
1,048
2,666
280–408
103–1,143
4.5–34.6
0–36
Kintex
UltraScale+
FPGA
Virtex
UltraScale
FPGA
Virtex
UltraScale+
FPGA
Zynq
UltraScale+
MPSoC
✓
Zynq
UltraScale+
RFSoC
✓
✓
✓
678–930
27.8–38.0
13.5–22.5
DS890 (v3.13) July 21, 2020
Product Specification
UltraScale Architecture and Product Data Sheet: Overview
MPSoC
CG DevicesEG Devices
Quad-core Arm Cortex-A53
Dual-core Arm Cortex-R5F
Mali-400MP2
–
EV Devices
Quad-core Arm Cortex-A53
Dual-core Arm Cortex-R5F
Mali-400MP2
H.264/H.265
RFSoC
DR Devices
Quad-core Arm Cortex-A53
Dual-core Arm Cortex-R5F
–
–
APU
RPU
GPU
VCU
Dual-core Arm Cortex-A53
Dual-core Arm Cortex-R5F
–
–
DS890 (v3.13) July 21, 2020
Product Specification
UltraScale Architecture and Product Data Sheet: Overview
DS890 (v3.13) July 21, 2020
Product Specification
UltraScale Architecture and Product Data Sheet: Overview
ZynqUltraScale+ MPSoC: EV Device Feature Summary
Table 17:ZynqUltraScale+ MPSoC: EV Device Feature Summary
ZU4EV
Application Processing Unit
Real-Time Processing Unit
Embedded and External
Memory
General Connectivity
High-Speed Connectivity
Graphic Processing Unit
Video Codec
System Logic Cells
CLB Flip-Flops
CLB LUTs
Distributed RAM (Mb)
Block RAM Blocks
Block RAM (Mb)
UltraRAM Blocks
UltraRAM (Mb)
DSP Slices
CMTs
Max. HP I/O
(1)
Max. HD I/O
(2)
System Monitor
GTH Transceiver 16.3Gb/s
(3)
GTY Transceivers 32.75Gb/s
Transceiver Fractional PLLs
PCIE4 (PCIe Gen3 x16)
150G Interlaken
100G Ethernet w/ RS-FEC
1
192,150
175,680
87,840
2.6
128
4.5
48
13.5
728
4
156
96
2
16
0
8
2
0
0
ZU5EVZU7EV
Quad-core Arm Cortex-A53 MPCore with CoreSight; NEON & Single/Double Precision Floating Point;
32KB/32KB L1 Cache, 1MB L2 Cache
Dual-core Arm Cortex-R5F with CoreSight; Single/Double Precision Floating Point;
32KB/32KB L1 Cache, and TCM
256KB On-Chip Memory w/ECC; External DDR4; DDR3; DDR3L; LPDDR4; LPDDR3;
External Quad-SPI; NAND; eMMC
214 PS I/O; UART; CAN; USB 2.0; I2C; SPI; 32b GPIO; Real Time Clock; WatchDog Timers; Triple
Timer Counters
4 PS-GTR; PCIe Gen1/2; Serial ATA 3.1; DisplayPort 1.2a; USB3.0; SGMII
Arm Mali-400 MP2; 64KB L2 Cache
1
256,200
234,240
117,120
3.5
144
5.1
64
18.0
1,248
4
156
96
2
16
0
8
2
0
0
1
504,000
460,800
230,400
6.2
312
11.0
96
27.0
1,728
8
416
48
2
24
0
12
2
0
0
Notes:
= High-performance I/O with support for I/O voltage from 1.0V to 1.8V.
= High-density I/O with support for I/O voltage from 1.2V to 3.3V.
transceivers in the SFVC784 package support data rates up to 12.5Gb/s. See Table18.
DS890 (v3.13) July 21, 2020
Product Specification
UltraScale Architecture and Product Data Sheet: Overview
ZynqUltraScale+: EV Device-Package Combinations and Maximum I/Os
Table 18:ZynqUltraScale+ MPSoC: EV Device-Package Combinations and Maximum I/Os
(1)(2)(3)(4)
Package
Package
Dimensions
(mm)
23x23
31x31
35x35
40x40
ZU4EV
HD, HP
GTH, GTY
96, 156
4, 0
48, 156
16, 0
ZU5EV
HD, HP
GTH, GTY
96, 156
4, 0
48, 156
16, 0
ZU7EV
HD, HP
GTH, GTY
SFVC784
(5)
FBVB900
FFVC1156
FFVF1517
48, 156
16, 0
48, 312
20, 0
48, 416
24, 0
DS890 (v3.13) July 21, 2020
Product Specification
2024年4月23日发(作者：风欣悦)
UltraScale Architecture and
Product Data Sheet: Overview
DS890 (v3.13) July 21, 2020Product Specification
General Description
Xilinx® UltraScale™ architecture comprises high-performance FPGA, MPSoC, and RFSoC families that address a vast spectrum of
system requirements with a focus on lowering total power consumption through numerous innovative technological
advancements.
Kintex® UltraScale FPGAs: High-performance FPGAs with a focus on price/performance, using both monolithic and
next-generation stacked silicon interconnect (SSI) technology. High DSP and blockRAM-to-logic ratios and next-generation
transceivers, combined with low-cost packaging, enable an optimum blend of capability and cost.
Kintex UltraScale+™ FPGAs: Increased performance and on-chip UltraRAM memory to reduce BOM cost. The ideal mix of
high-performance peripherals and cost-effective system implementation. Kintex UltraScale+ FPGAs have numerous power
options that deliver the optimal balance between the required system performance and the smallest power envelope.
Virtex® UltraScale FPGAs: High-capacity, high-performance FPGAs enabled using both monolithic and next-generation SSI
technology. Virtex UltraScale devices achieve the highest system capacity, bandwidth, and performance to address key market and
application requirements through integration of various system-level functions.
Virtex UltraScale+ FPGAs: The highest transceiver bandwidth, highest DSP count, and highest on-chip and in-package memory
available in the UltraScale architecture. Virtex UltraScale+ FPGAs also provide numerous power options that deliver the optimal
balance between the required system performance and the smallest power envelope.
Zynq® UltraScale+ MPSoCs: Combine the Arm® v8-based Cortex®-A53 high-performance energy-efficient 64-bit application
processor with the Arm Cortex-R5F real-time processor and the UltraScale architecture to create the industry's first
programmable MPSoCs. Provide unprecedented power savings, heterogeneous processing, and programmable acceleration.
Zynq® UltraScale+ RFSoCs: Combine RF data converter subsystem and forward error correction with industry-leading
programmable logic and heterogeneous processing capability. Integrated RF-ADCs, RF-DACs, and soft-decision FECs (SD-FEC)
provide the key subsystems for multiband, multi-mode cellular radios and cable infrastructure.
Family Comparisons
Table 1:Device Resources
Kintex
UltraScale
FPGA
MPSoC Processing System
RF-ADC/DAC
SD-FEC
System Logic Cells (K)
Block Memory (Mb)
UltraRAM (Mb)
HBM DRAM (GB)
DSP (Slices)
DSP Performance (GMAC/s)
Transceivers
Max. Transceiver Speed (Gb/s)
Max. Serial Bandwidth (full duplex) (Gb/s)
Memory Interface Performance (Mb/s)
I/O Pins
768–5,520
8,180
12–64
16.3
2,086
2,400
312–832
1,368–3,528
6,287
16–76
32.75
3,268
2,666
280–668
600–2,880
4,268
36–120
30.5
5,616
2,400
338–1,456
318–1,451
12.7–75.9
356–1,843
12.7–60.8
0–81
783–5,541
44.3–132.9
862–8,938
23.6–94.5
90–360
0–16
1,320–12,288
21,897
32–128
58.0
8,384
2,666
208–2,072
240–3,528
6,287
0–72
32.75
3,268
2,666
82–668
3,145–4,272
7,613
8–16
32.75
1,048
2,666
280–408
103–1,143
4.5–34.6
0–36
Kintex
UltraScale+
FPGA
Virtex
UltraScale
FPGA
Virtex
UltraScale+
FPGA
Zynq
UltraScale+
MPSoC
✓
Zynq
UltraScale+
RFSoC
✓
✓
✓
678–930
27.8–38.0
13.5–22.5
DS890 (v3.13) July 21, 2020
Product Specification
UltraScale Architecture and Product Data Sheet: Overview
MPSoC
CG DevicesEG Devices
Quad-core Arm Cortex-A53
Dual-core Arm Cortex-R5F
Mali-400MP2
–
EV Devices
Quad-core Arm Cortex-A53
Dual-core Arm Cortex-R5F
Mali-400MP2
H.264/H.265
RFSoC
DR Devices
Quad-core Arm Cortex-A53
Dual-core Arm Cortex-R5F
–
–
APU
RPU
GPU
VCU
Dual-core Arm Cortex-A53
Dual-core Arm Cortex-R5F
–
–
DS890 (v3.13) July 21, 2020
Product Specification
UltraScale Architecture and Product Data Sheet: Overview
DS890 (v3.13) July 21, 2020
Product Specification
UltraScale Architecture and Product Data Sheet: Overview
ZynqUltraScale+ MPSoC: EV Device Feature Summary
Table 17:ZynqUltraScale+ MPSoC: EV Device Feature Summary
ZU4EV
Application Processing Unit
Real-Time Processing Unit
Embedded and External
Memory
General Connectivity
High-Speed Connectivity
Graphic Processing Unit
Video Codec
System Logic Cells
CLB Flip-Flops
CLB LUTs
Distributed RAM (Mb)
Block RAM Blocks
Block RAM (Mb)
UltraRAM Blocks
UltraRAM (Mb)
DSP Slices
CMTs
Max. HP I/O
(1)
Max. HD I/O
(2)
System Monitor
GTH Transceiver 16.3Gb/s
(3)
GTY Transceivers 32.75Gb/s
Transceiver Fractional PLLs
PCIE4 (PCIe Gen3 x16)
150G Interlaken
100G Ethernet w/ RS-FEC
1
192,150
175,680
87,840
2.6
128
4.5
48
13.5
728
4
156
96
2
16
0
8
2
0
0
ZU5EVZU7EV
Quad-core Arm Cortex-A53 MPCore with CoreSight; NEON & Single/Double Precision Floating Point;
32KB/32KB L1 Cache, 1MB L2 Cache
Dual-core Arm Cortex-R5F with CoreSight; Single/Double Precision Floating Point;
32KB/32KB L1 Cache, and TCM
256KB On-Chip Memory w/ECC; External DDR4; DDR3; DDR3L; LPDDR4; LPDDR3;
External Quad-SPI; NAND; eMMC
214 PS I/O; UART; CAN; USB 2.0; I2C; SPI; 32b GPIO; Real Time Clock; WatchDog Timers; Triple
Timer Counters
4 PS-GTR; PCIe Gen1/2; Serial ATA 3.1; DisplayPort 1.2a; USB3.0; SGMII
Arm Mali-400 MP2; 64KB L2 Cache
1
256,200
234,240
117,120
3.5
144
5.1
64
18.0
1,248
4
156
96
2
16
0
8
2
0
0
1
504,000
460,800
230,400
6.2
312
11.0
96
27.0
1,728
8
416
48
2
24
0
12
2
0
0
Notes:
= High-performance I/O with support for I/O voltage from 1.0V to 1.8V.
= High-density I/O with support for I/O voltage from 1.2V to 3.3V.
transceivers in the SFVC784 package support data rates up to 12.5Gb/s. See Table18.
DS890 (v3.13) July 21, 2020
Product Specification
UltraScale Architecture and Product Data Sheet: Overview
ZynqUltraScale+: EV Device-Package Combinations and Maximum I/Os
Table 18:ZynqUltraScale+ MPSoC: EV Device-Package Combinations and Maximum I/Os
(1)(2)(3)(4)
Package
Package
Dimensions
(mm)
23x23
31x31
35x35
40x40
ZU4EV
HD, HP
GTH, GTY
96, 156
4, 0
48, 156
16, 0
ZU5EV
HD, HP
GTH, GTY
96, 156
4, 0
48, 156
16, 0
ZU7EV
HD, HP
GTH, GTY
SFVC784
(5)
FBVB900
FFVC1156
FFVF1517
48, 156
16, 0
48, 312
20, 0
48, 416
24, 0
DS890 (v3.13) July 21, 2020
Product Specification