2024年4月26日发(作者：满山槐)
元器件交易网
FEATURES
Model 635
LVPECL or LVDS CLOCK OSCILLATOR
• Standard 7.5x5.0mm Surface Mount Footprint
• Differential LVPECL or LVDS Output
• Fundamental or Overtone Crystal
• Low Phase Jitter
• Frequency Range 19.44 – 250 MHz
• Frequency Stability, ±50 ppm Standard
(±20 ppm, ±25 ppm and ±100 ppm available)
• +2.5Vdc or +3.3Vdc Operation
• Operating Temperature to –40°C to +85°C
• Output Enable Standard
• Tape & Reel Packaging
• RoHS/Green Compliant (6/6)
DESCRIPTION
The Model 635 is a ceramic packaged Clock
oscillator offering reduced size and enhanced
stability. The small size means it is perfect for
any application. The enhanced stability means it
is the perfect choice for today’s communications
applications that require tight frequency control.
ORDERING INFORMATION
635M
OUTPUT TYPE FREQUENCY IN MHz
P = PECL,
Pin 1 Enable Pin 2 N.C.
(standard)
M - indicates MHz and decimal point.
L = LVDS,
Pin 1 Enable Pin 2 N.C.
(standard)
Frequency is recorded with minimum 4
E = PECL,
Pin 2 Enable Pin 1 N.C.
significant digits to the right of the "M".
V = LVDS,
Pin 2 Enable Pin 1 N.C.
FREQUENCY STABILITYSUPPLY VOLTAGE
6 = ± 20 ppm * 2 = 2.5 Vdc
5 = ± 25 ppm 3 = 3.3 Vdc
3 = ± 50 ppm (standard)
2 = ± 100 ppm
(over -40°C to 85°C only)
OPERATING TEMPERATURE RANGE
C = -20°C to +70°C (standard)
I = -40°C to +85°C
* - Not available with 'I' temperature range. Consult factory for availability before ordering.
Example Part Number: 635P3C3155M5200
Document No. 008-0284-0 Page 1 - 4 Rev. D
٠ ٠ ٠ CTS Electronic Components, Inc. ٠ 171 Covington Drive ٠ Bloomingdale, IL 60108 ٠ ٠ ٠
٠ ٠ ٠
٠ ٠ ٠
元器件交易网
Model 635
7.5x5.0mm Low Cost
LVPECL or LVDS Clock Oscillator
ELECTRICAL CHARACTERISTICS
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNIT
V
Maximum Supply Voltage--0.5-5.0V
T
Storage Temperature--55-125°C
Frequency Range
(See Note 1)
f
-MHz
LVPECL and LVDS19.44-250
20, 25, 50
Frequency Stability
∆f/f
---± ppm
(See Note 2 and Ordering Information)
or 100
Operating Temperature
T
-°C
Commercial-2070
25
Industrial-4085
2.382.52.63
Supply Voltage
V
± 5 %V
3.143.33.47
Supply Current
I
Maximum Load-mA
LVPECL50100
-
LVDS2560
T
Application of V
-35ms
Start Up Time
Bandwidth 12 kHz - 20 MHz--1ps RMS Phase Jittertjrms
pjrms---5ps RMS Period Jitter
Enable FunctionStandby
0.7*VV
Pin 1 or Pin 2 Logic '1', Output Enabled--V
Enable Input Voltage
0.3*VV
Pin 1 or Pin 2 Logic '0', Output Disabled--
Disable Input Voltage
I
Disable CurrentPin 1 or Pin 2 Logic '1' , Output Disabled--20uA
T
--5ns Enable Time
Pin 1 or Pin 2 Logic '1'
LVPECL WAVEFORM
R
--50-Ohms
Output Load
@ V- 1.3V
SYM Output Duty Cycle
45-55%
Output Voltage Levels
V
VV- 1.025V
--PECL Load
Logic '1' Level
VV - 1.62V
Logic '0' LevelPECL Load--
Rise and Fall Time
T, T
@ 20% - 80% Levelsns
-0.81.0
f
< 100 MHz
-0.50.6
f
> 100 MHz
LVDS WAVEFORM
R
Between Outputs-100-Ohms
Output Load
SYM@ 1.25V45-55% Output Duty Cycle
V
RL = 100 Ohms247350454mV Differential Output Voltage
----50mV Differential Output Error
V
LVDS Load1.1251.251.375V Offset Voltage
Offset Error----50mV
Output Voltage Levels
V
V
LVDS Load-1.431.6
Logic '1' Level
V
LVDS Load0.91.1- Logic '0' Level
Rise and Fall Time
T, T
ns@ 20% - 80% Levels
-0.81.0
f < 100 MHz
f
> 100 MHz-0.50.6
Notes:
1.
For frequencies above 160 MHz consult factory for availability.
ive of initial tolerance at time of shipment, changes in supply voltage, load, temperature and 10 year aging.
PECL/LVDS OUTPUT WAVEFORM
V
OUT
80%
V
50%
ENABLE TRUTH TABLE
PIN 1 or PIN 2 PIN 4 / PIN 5
20%
OUT
Logic ‘1’ Output
V
Open Output
Logic ‘0’ High Imp.
DUTY CYCLE = t/T x 100 (%)
A
b
s
o
l
u
t
e
M
a
x
i
m
u
m
s
CC
STG
O
O
A
CC
CC
SCC
IH
IL
CC
E
l
e
c
t
r
i
c
a
l
a
n
d
W
a
v
e
f
o
r
m
P
a
r
a
m
e
t
e
r
s
CC
IL
PLZ
L
CC
OH
OL
CC
CC
O
O
RF
L
OD
OS
OH
OL
O
O
RF
TrTf
OH
OS
UPTIME (t)
OL
PERIOD (T)
Document No. 008-0284-0 Page 2 - 4 Rev. D
٠ ٠ ٠
CTS Electronic Components, Inc.
٠
171 Covington Drive
٠
Bloomingdale, IL 60108
٠ ٠ ٠
2024年4月26日发(作者：满山槐)
元器件交易网
FEATURES
Model 635
LVPECL or LVDS CLOCK OSCILLATOR
• Standard 7.5x5.0mm Surface Mount Footprint
• Differential LVPECL or LVDS Output
• Fundamental or Overtone Crystal
• Low Phase Jitter
• Frequency Range 19.44 – 250 MHz
• Frequency Stability, ±50 ppm Standard
(±20 ppm, ±25 ppm and ±100 ppm available)
• +2.5Vdc or +3.3Vdc Operation
• Operating Temperature to –40°C to +85°C
• Output Enable Standard
• Tape & Reel Packaging
• RoHS/Green Compliant (6/6)
DESCRIPTION
The Model 635 is a ceramic packaged Clock
oscillator offering reduced size and enhanced
stability. The small size means it is perfect for
any application. The enhanced stability means it
is the perfect choice for today’s communications
applications that require tight frequency control.
ORDERING INFORMATION
635M
OUTPUT TYPE FREQUENCY IN MHz
P = PECL,
Pin 1 Enable Pin 2 N.C.
(standard)
M - indicates MHz and decimal point.
L = LVDS,
Pin 1 Enable Pin 2 N.C.
(standard)
Frequency is recorded with minimum 4
E = PECL,
Pin 2 Enable Pin 1 N.C.
significant digits to the right of the "M".
V = LVDS,
Pin 2 Enable Pin 1 N.C.
FREQUENCY STABILITYSUPPLY VOLTAGE
6 = ± 20 ppm * 2 = 2.5 Vdc
5 = ± 25 ppm 3 = 3.3 Vdc
3 = ± 50 ppm (standard)
2 = ± 100 ppm
(over -40°C to 85°C only)
OPERATING TEMPERATURE RANGE
C = -20°C to +70°C (standard)
I = -40°C to +85°C
* - Not available with 'I' temperature range. Consult factory for availability before ordering.
Example Part Number: 635P3C3155M5200
Document No. 008-0284-0 Page 1 - 4 Rev. D
٠ ٠ ٠ CTS Electronic Components, Inc. ٠ 171 Covington Drive ٠ Bloomingdale, IL 60108 ٠ ٠ ٠
٠ ٠ ٠
٠ ٠ ٠
元器件交易网
Model 635
7.5x5.0mm Low Cost
LVPECL or LVDS Clock Oscillator
ELECTRICAL CHARACTERISTICS
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNIT
V
Maximum Supply Voltage--0.5-5.0V
T
Storage Temperature--55-125°C
Frequency Range
(See Note 1)
f
-MHz
LVPECL and LVDS19.44-250
20, 25, 50
Frequency Stability
∆f/f
---± ppm
(See Note 2 and Ordering Information)
or 100
Operating Temperature
T
-°C
Commercial-2070
25
Industrial-4085
2.382.52.63
Supply Voltage
V
± 5 %V
3.143.33.47
Supply Current
I
Maximum Load-mA
LVPECL50100
-
LVDS2560
T
Application of V
-35ms
Start Up Time
Bandwidth 12 kHz - 20 MHz--1ps RMS Phase Jittertjrms
pjrms---5ps RMS Period Jitter
Enable FunctionStandby
0.7*VV
Pin 1 or Pin 2 Logic '1', Output Enabled--V
Enable Input Voltage
0.3*VV
Pin 1 or Pin 2 Logic '0', Output Disabled--
Disable Input Voltage
I
Disable CurrentPin 1 or Pin 2 Logic '1' , Output Disabled--20uA
T
--5ns Enable Time
Pin 1 or Pin 2 Logic '1'
LVPECL WAVEFORM
R
--50-Ohms
Output Load
@ V- 1.3V
SYM Output Duty Cycle
45-55%
Output Voltage Levels
V
VV- 1.025V
--PECL Load
Logic '1' Level
VV - 1.62V
Logic '0' LevelPECL Load--
Rise and Fall Time
T, T
@ 20% - 80% Levelsns
-0.81.0
f
< 100 MHz
-0.50.6
f
> 100 MHz
LVDS WAVEFORM
R
Between Outputs-100-Ohms
Output Load
SYM@ 1.25V45-55% Output Duty Cycle
V
RL = 100 Ohms247350454mV Differential Output Voltage
----50mV Differential Output Error
V
LVDS Load1.1251.251.375V Offset Voltage
Offset Error----50mV
Output Voltage Levels
V
V
LVDS Load-1.431.6
Logic '1' Level
V
LVDS Load0.91.1- Logic '0' Level
Rise and Fall Time
T, T
ns@ 20% - 80% Levels
-0.81.0
f < 100 MHz
f
> 100 MHz-0.50.6
Notes:
1.
For frequencies above 160 MHz consult factory for availability.
ive of initial tolerance at time of shipment, changes in supply voltage, load, temperature and 10 year aging.
PECL/LVDS OUTPUT WAVEFORM
V
OUT
80%
V
50%
ENABLE TRUTH TABLE
PIN 1 or PIN 2 PIN 4 / PIN 5
20%
OUT
Logic ‘1’ Output
V
Open Output
Logic ‘0’ High Imp.
DUTY CYCLE = t/T x 100 (%)
A
b
s
o
l
u
t
e
M
a
x
i
m
u
m
s
CC
STG
O
O
A
CC
CC
SCC
IH
IL
CC
E
l
e
c
t
r
i
c
a
l
a
n
d
W
a
v
e
f
o
r
m
P
a
r
a
m
e
t
e
r
s
CC
IL
PLZ
L
CC
OH
OL
CC
CC
O
O
RF
L
OD
OS
OH
OL
O
O
RF
TrTf
OH
OS
UPTIME (t)
OL
PERIOD (T)
Document No. 008-0284-0 Page 2 - 4 Rev. D
٠ ٠ ٠
CTS Electronic Components, Inc.
٠
171 Covington Drive
٠
Bloomingdale, IL 60108
٠ ٠ ٠