2024年5月18日发(作者：广盼盼)
UltraScale Architecture and Product Data Sheet: Overview
In FPGAs and the PL of the MPSoCs and RFSoCs, sensor outputs and up to 17 user-allocated external
analog inputs are digitized using a 10-bit 200 kilo-sample-per-second (kSPS) ADC, and the measurements
are stored in registers that can be accessed via internal FPGA (DRP), JTAG, PMBus, or I2C interfaces. The
I2C interface and PMBus allow the on-chip monitoring to be easily accessed by the System Manager/Host
before and after device configuration.
The System Monitor in the PS MPSoC and RFSoC uses a 10-bit, 1 mega-sample-per-second (MSPS) ADC to
digitize the sensor outputs. The measurements are stored in registers and are accessed via the Advanced
Peripheral Bus (APB) interface by the processors and the platform management unit (PMU) in the PS.
Configuration
The UltraScale architecture-based devices store their customized configuration in SRAM-type internal
latches. The configuration storage is volatile and must be reloaded whenever the device is powered up.
This storage can also be reloaded at any time. Several methods and data formats for loading configuration
are available, determined by the mode pins, with more dedicated configuration datapath pins to simplify
the configuration process.
UltraScale architecture-based devices support secure and non-secure boot with optional Advanced
Encryption Standard - Galois/Counter Mode (AES-GCM) decryption and authentication logic. If only
authentication is required, the UltraScale architecture provides an alternative form of authentication in the
form of RSA algorithms. For RSA authentication support in the Kintex UltraScale and Virtex UltraScale
families, go to UG570
, UltraScale Architecture Configuration User Guide.
UltraScale architecture-based devices also have the ability to select between multiple configurations, and
support robust field-update methodologies. This is especially useful for updates to a design after the end
product has been shipped. Designers can release their product with an early version of the design, thus
getting their product to market faster. This feature allows designers to keep their customers current with
the most up-to-date design while the product is already deployed in the field.
Booting MPSoCs and RFSoCs
ZynqUltraScale+MPSoCs and RFSoCs use a multi-stage boot process that supports both a non-secure
and a secure boot. The PS is the master of the boot and configuration process. For a secure boot, the
AES-GCM, SHA-3/384 decryption/authentication, and 4096-bit RSA blocks decrypt and authenticate the
image.
Upon reset, the device mode pins are read to determine the primary boot device to be used: NAND,
Quad-SPI, SD, eMMC, or JTAG. JTAG can only be used as a non-secure boot source and is intended for
debugging purposes. One of the CPUs, Cortex-A53 or Cortex-R5F, executes code out of on-chip ROM and
copies the first stage boot loader (FSBL) from the boot device to the on-chip memory (OCM).
After copying the FSBL to OCM, the processor executes the FSBL. Xilinx supplies example FSBLs or users
can create their own. The FSBL initiates the boot of the PS and can load and configure the PL, or
configuration of the PL can be deferred to a later stage. The FSBL typically loads either a user application
or an optional second stage boot loader (SSBL) such as U-Boot. Users obtain example SSBL from Xilinx or
a third party, or they can create their own SSBL. The SSBL continues the boot process by loading code from
any of the primary boot devices or from other sources such as USB, Ethernet, etc. If the FSBL did not
configure the PL, the SSBL can do so, or again, the configuration can be deferred to a later stage.
DS890 (v4.0) March 16, 2021
Product Specification
UltraScale Architecture and Product Data Sheet: Overview
The static memory interface controller (NAND, eMMC, or Quad-SPI) is configured using default settings.
To improve device configuration speed, these settings can be modified by information provided in the
boot image header. The ROM boot image is not user readable or executable after boot.
Configuring FPGAs
The SPI (serial NOR) interface (x1, x2, x4, and dual x4 modes) and the BPI (parallel NOR) interface (x8 and
x16 modes) are two common methods used for configuring the FPGA. Users can directly connect an SPI or
BPI flash to the FPGA, and the FPGA's internal configuration logic reads the bitstream out of the flash and
configures itself, eliminating the need for an external controller. The FPGA automatically detects the bus
width on the fly, eliminating the need for any external controls or switches. Bus widths supported are x1,
x2, x4, and dual x4 for SPI, and x8 and x16 for BPI. The larger bus widths increase configuration speed and
reduce the amount of time it takes for the FPGA to start up after power-on.
In master mode, the FPGA can drive the configuration clock from an internally generated clock, or for
higher speed configuration, the FPGA can use an external configuration clock source. This allows
high-speed configuration with the ease of use characteristic of master mode. Slave modes up to 32bits
wide that are especially useful for processor-driven configuration are also supported by the FPGA. In
addition, the new media configuration access port (MCAP) provides a direct connection between the
integrated block for PCIe and the configuration logic to simplify configuration over PCIe.
SEU detection and mitigation (SEM) IP, RSA authentication, post-configuration CRC, and Security Monitor
(SecMon) IP are not supported in the KU025 FPGA.
Packaging
The UltraScale devices are available in a variety of organic flip-chip, lidless flip-chip, and integrated
fan-out (InFO) packages supporting different quantities of I/Os and transceivers. Maximum supported
performance can depend on the style of package and its material. Always refer to the specific device data
sheet for performance specifications by package type.
In flip-chip packages, the silicon device is attached to the package substrate using a high-performance
flip-chip process. Decoupling capacitors are mounted on the package substrate to optimize signal
integrity under simultaneous switching of outputs (SSO) conditions.
InFO packages are small form factor packages that require much less PCB area and are much thinner than
other packaging types. These packages enable the use of high compute density devices in small
applications. The elimination of the package substrate provides excellent thermal and power distribution
and shorter flight times with improved signal integrity.
DS890 (v4.0) March 16, 2021
Product Specification
2024年5月18日发(作者：广盼盼)
UltraScale Architecture and Product Data Sheet: Overview
In FPGAs and the PL of the MPSoCs and RFSoCs, sensor outputs and up to 17 user-allocated external
analog inputs are digitized using a 10-bit 200 kilo-sample-per-second (kSPS) ADC, and the measurements
are stored in registers that can be accessed via internal FPGA (DRP), JTAG, PMBus, or I2C interfaces. The
I2C interface and PMBus allow the on-chip monitoring to be easily accessed by the System Manager/Host
before and after device configuration.
The System Monitor in the PS MPSoC and RFSoC uses a 10-bit, 1 mega-sample-per-second (MSPS) ADC to
digitize the sensor outputs. The measurements are stored in registers and are accessed via the Advanced
Peripheral Bus (APB) interface by the processors and the platform management unit (PMU) in the PS.
Configuration
The UltraScale architecture-based devices store their customized configuration in SRAM-type internal
latches. The configuration storage is volatile and must be reloaded whenever the device is powered up.
This storage can also be reloaded at any time. Several methods and data formats for loading configuration
are available, determined by the mode pins, with more dedicated configuration datapath pins to simplify
the configuration process.
UltraScale architecture-based devices support secure and non-secure boot with optional Advanced
Encryption Standard - Galois/Counter Mode (AES-GCM) decryption and authentication logic. If only
authentication is required, the UltraScale architecture provides an alternative form of authentication in the
form of RSA algorithms. For RSA authentication support in the Kintex UltraScale and Virtex UltraScale
families, go to UG570
, UltraScale Architecture Configuration User Guide.
UltraScale architecture-based devices also have the ability to select between multiple configurations, and
support robust field-update methodologies. This is especially useful for updates to a design after the end
product has been shipped. Designers can release their product with an early version of the design, thus
getting their product to market faster. This feature allows designers to keep their customers current with
the most up-to-date design while the product is already deployed in the field.
Booting MPSoCs and RFSoCs
ZynqUltraScale+MPSoCs and RFSoCs use a multi-stage boot process that supports both a non-secure
and a secure boot. The PS is the master of the boot and configuration process. For a secure boot, the
AES-GCM, SHA-3/384 decryption/authentication, and 4096-bit RSA blocks decrypt and authenticate the
image.
Upon reset, the device mode pins are read to determine the primary boot device to be used: NAND,
Quad-SPI, SD, eMMC, or JTAG. JTAG can only be used as a non-secure boot source and is intended for
debugging purposes. One of the CPUs, Cortex-A53 or Cortex-R5F, executes code out of on-chip ROM and
copies the first stage boot loader (FSBL) from the boot device to the on-chip memory (OCM).
After copying the FSBL to OCM, the processor executes the FSBL. Xilinx supplies example FSBLs or users
can create their own. The FSBL initiates the boot of the PS and can load and configure the PL, or
configuration of the PL can be deferred to a later stage. The FSBL typically loads either a user application
or an optional second stage boot loader (SSBL) such as U-Boot. Users obtain example SSBL from Xilinx or
a third party, or they can create their own SSBL. The SSBL continues the boot process by loading code from
any of the primary boot devices or from other sources such as USB, Ethernet, etc. If the FSBL did not
configure the PL, the SSBL can do so, or again, the configuration can be deferred to a later stage.
DS890 (v4.0) March 16, 2021
Product Specification
UltraScale Architecture and Product Data Sheet: Overview
The static memory interface controller (NAND, eMMC, or Quad-SPI) is configured using default settings.
To improve device configuration speed, these settings can be modified by information provided in the
boot image header. The ROM boot image is not user readable or executable after boot.
Configuring FPGAs
The SPI (serial NOR) interface (x1, x2, x4, and dual x4 modes) and the BPI (parallel NOR) interface (x8 and
x16 modes) are two common methods used for configuring the FPGA. Users can directly connect an SPI or
BPI flash to the FPGA, and the FPGA's internal configuration logic reads the bitstream out of the flash and
configures itself, eliminating the need for an external controller. The FPGA automatically detects the bus
width on the fly, eliminating the need for any external controls or switches. Bus widths supported are x1,
x2, x4, and dual x4 for SPI, and x8 and x16 for BPI. The larger bus widths increase configuration speed and
reduce the amount of time it takes for the FPGA to start up after power-on.
In master mode, the FPGA can drive the configuration clock from an internally generated clock, or for
higher speed configuration, the FPGA can use an external configuration clock source. This allows
high-speed configuration with the ease of use characteristic of master mode. Slave modes up to 32bits
wide that are especially useful for processor-driven configuration are also supported by the FPGA. In
addition, the new media configuration access port (MCAP) provides a direct connection between the
integrated block for PCIe and the configuration logic to simplify configuration over PCIe.
SEU detection and mitigation (SEM) IP, RSA authentication, post-configuration CRC, and Security Monitor
(SecMon) IP are not supported in the KU025 FPGA.
Packaging
The UltraScale devices are available in a variety of organic flip-chip, lidless flip-chip, and integrated
fan-out (InFO) packages supporting different quantities of I/Os and transceivers. Maximum supported
performance can depend on the style of package and its material. Always refer to the specific device data
sheet for performance specifications by package type.
In flip-chip packages, the silicon device is attached to the package substrate using a high-performance
flip-chip process. Decoupling capacitors are mounted on the package substrate to optimize signal
integrity under simultaneous switching of outputs (SSO) conditions.
InFO packages are small form factor packages that require much less PCB area and are much thinner than
other packaging types. These packages enable the use of high compute density devices in small
applications. The elimination of the package substrate provides excellent thermal and power distribution
and shorter flight times with improved signal integrity.
DS890 (v4.0) March 16, 2021
Product Specification