2024年5月19日发(作者：位信鸥)
16-Bit, 20/40/65/80 MSPS,
1.8 V Dual Analog-to-Digital Converter
FEATURES
1.8 V analog supply operation
1.8 V to 3.3 V output supply
Integrated quadrature error correction (QEC)
SNR
77.6 dBFS at 9.7 MHz input
71 dBFS at 200 MHz input
SFDR
93 dBc at 9.7 MHz input
80 dBc at 200 MHz input
Low power
44 mW per channel at 20 MSPS
100 mW per channel at 80 MSPS
Differential input with 700 MHz bandwidth
On-chip voltage reference and sample-and-hold circuit
2 V p-p differential analog input
DNL = −0.5/+1.1 LSB
Serial port control options
Offset binary, gray code, or twos complement data format
Optional clock duty cycle stabilizer (DCS)
Integer 1-to-6 input clock divider
Data output multiplex option
Built-in selectable digital test pattern generation
Energy-saving power-down modes
Data clock output (DCO) with programmable clock and
data alignment
APPLICATIONS
Communications
Diversity radio systems
Multimode digital receivers
GSM, EDGE, W-CDMA, LTE, CDMA2000, WiMAX, TD-SCDMA
I/Q demodulation systems
Smart antenna systems
Battery-powered instruments
Handheld scope meters
Portable medical imaging
Ultrasound
Radar/LIDAR
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
AD9269
FUNCTIONAL BLOCK DIAGRAM
AVDDGNDSDIOSCLK
CSB
AD9269
SPI
R
ORA
E
F
VIN+A
PROGRAMMING DATA
F
S
U
D15A
ADC
O
B
VIN–A
M
T
C
U
P
D0A
T
U
O
VREF
N
DCOA
O
SENSE
QUADRATURE
I
T
ERROR
P
O
DRVDD
VCM
REF
CORRECTION
X
U
SELECT
M
RBIAS
R
ORB
E
F
VIN–B
F
S
U
D15B
ADC
O
B
VIN+B
M
T
C
U
P
D0B
T
U
O
DCOB
DIVIDE
1TO6
DUTY CYCLE
STABILIZERCONTROLS
MODE
1
0
0
-
8
3
CLK+CLK–SYNCDCSPDWNDFSOEB
5
8
0
Figure 1.
PRODUCT HIGHLIGHTS
1. The AD9269 operates from a single 1.8 V analog power
supply and features a separate digital output driver supply
to accommodate 1.8 V to 3.3 V logic families.
2. The patented sample-and-hold circuit maintains excellent
performance for input frequencies up to 200 MHz and is
designed for low cost, low power, and ease of use.
3. An optional SPI selectable dc correction and quadrature
error correction (QEC) feature corrects for dc offset, gain,
and phase mismatches between the two channels.
4. A standard serial port interface (SPI) supports various
product features and functions, such as data output format-
ting, internal clock divider, power-down, DCO/data timing
and offset adjustments, and voltage reference modes.
5. The AD9269 is packaged in a 64-lead RoHS-compliant
LFCSP that is pin compatible with the AD9268 16-bit
ADC, the AD9258 14-bit ADC, the AD9251 14-bit ADC
the AD9231 12-bit ADC, the AD6659 12-bit baseband
diversity receiver, and the AD9204 10-bit ADC, enabling a
simple migration path between 10-bit and 16-bit converters
sampling from 20 MSPS to 125 MSPS.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113 ©2010 Analog Devices, Inc. All rights reserved.
AD9269
Clock Input Considerations ...................................................... 22
Power Dissipation and Standby Mode .................................... 24
Digital Outputs ........................................................................... 25
Timing ......................................................................................... 25
Built-In Self-Test (BIST) and Output Test .................................. 26
Built-In Self-Test (BIST) ............................................................ 26
Output Test Modes ..................................................................... 26
Channel/Chip Synchronization .................................................... 27
DC and Quadrature Error Correction (QEC) ............................ 28
Serial Port Interface (SPI) .............................................................. 29
Configuration Using the SPI ..................................................... 29
Hardware Interface ..................................................................... 29
Configuration Without the SPI ................................................ 30
SPI Accessible Features .............................................................. 30
Memory Map .................................................................................. 31
Reading the Memory Map Register Table ............................... 31
Open Locations .......................................................................... 31
Default Values ............................................................................. 31
Memory Map Register Table ..................................................... 32
Memory Map Register Descriptions ........................................ 34
Applications Information .............................................................. 36
Design Guidelines ...................................................................... 36
Outline Dimensions ....................................................................... 37
Ordering Guide .......................................................................... 37
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Functional Block Diagram .............................................................. 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
General Description ......................................................................... 3
Specifications ..................................................................................... 4
DC Specifications ......................................................................... 4
AC Specifications .......................................................................... 6
Digital Specifications ................................................................... 7
Switching Specifications .............................................................. 8
Timing Specifications .................................................................. 9
Absolute Maximum Ratings .......................................................... 10
Thermal Characteristics ............................................................ 10
ESD Caution ................................................................................ 10
Pin Configuration and Function Descriptions ........................... 11
Typical Performance Characteristics ........................................... 13
AD9269-80 .................................................................................. 13
AD9269-65 .................................................................................. 15
AD9269-40 .................................................................................. 16
AD9269-20 .................................................................................. 17
Equivalent Circuits ......................................................................... 18
Theory of Operation ...................................................................... 19
ADC Architecture ...................................................................... 19
Analog Input Considerations .................................................... 19
Voltage Reference ....................................................................... 21
REVISION HISTORY
1/10—Revision 0: Initial Version
Rev. 0 | Page 2 of 40
2024年5月19日发(作者：位信鸥)
16-Bit, 20/40/65/80 MSPS,
1.8 V Dual Analog-to-Digital Converter
FEATURES
1.8 V analog supply operation
1.8 V to 3.3 V output supply
Integrated quadrature error correction (QEC)
SNR
77.6 dBFS at 9.7 MHz input
71 dBFS at 200 MHz input
SFDR
93 dBc at 9.7 MHz input
80 dBc at 200 MHz input
Low power
44 mW per channel at 20 MSPS
100 mW per channel at 80 MSPS
Differential input with 700 MHz bandwidth
On-chip voltage reference and sample-and-hold circuit
2 V p-p differential analog input
DNL = −0.5/+1.1 LSB
Serial port control options
Offset binary, gray code, or twos complement data format
Optional clock duty cycle stabilizer (DCS)
Integer 1-to-6 input clock divider
Data output multiplex option
Built-in selectable digital test pattern generation
Energy-saving power-down modes
Data clock output (DCO) with programmable clock and
data alignment
APPLICATIONS
Communications
Diversity radio systems
Multimode digital receivers
GSM, EDGE, W-CDMA, LTE, CDMA2000, WiMAX, TD-SCDMA
I/Q demodulation systems
Smart antenna systems
Battery-powered instruments
Handheld scope meters
Portable medical imaging
Ultrasound
Radar/LIDAR
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
AD9269
FUNCTIONAL BLOCK DIAGRAM
AVDDGNDSDIOSCLK
CSB
AD9269
SPI
R
ORA
E
F
VIN+A
PROGRAMMING DATA
F
S
U
D15A
ADC
O
B
VIN–A
M
T
C
U
P
D0A
T
U
O
VREF
N
DCOA
O
SENSE
QUADRATURE
I
T
ERROR
P
O
DRVDD
VCM
REF
CORRECTION
X
U
SELECT
M
RBIAS
R
ORB
E
F
VIN–B
F
S
U
D15B
ADC
O
B
VIN+B
M
T
C
U
P
D0B
T
U
O
DCOB
DIVIDE
1TO6
DUTY CYCLE
STABILIZERCONTROLS
MODE
1
0
0
-
8
3
CLK+CLK–SYNCDCSPDWNDFSOEB
5
8
0
Figure 1.
PRODUCT HIGHLIGHTS
1. The AD9269 operates from a single 1.8 V analog power
supply and features a separate digital output driver supply
to accommodate 1.8 V to 3.3 V logic families.
2. The patented sample-and-hold circuit maintains excellent
performance for input frequencies up to 200 MHz and is
designed for low cost, low power, and ease of use.
3. An optional SPI selectable dc correction and quadrature
error correction (QEC) feature corrects for dc offset, gain,
and phase mismatches between the two channels.
4. A standard serial port interface (SPI) supports various
product features and functions, such as data output format-
ting, internal clock divider, power-down, DCO/data timing
and offset adjustments, and voltage reference modes.
5. The AD9269 is packaged in a 64-lead RoHS-compliant
LFCSP that is pin compatible with the AD9268 16-bit
ADC, the AD9258 14-bit ADC, the AD9251 14-bit ADC
the AD9231 12-bit ADC, the AD6659 12-bit baseband
diversity receiver, and the AD9204 10-bit ADC, enabling a
simple migration path between 10-bit and 16-bit converters
sampling from 20 MSPS to 125 MSPS.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113 ©2010 Analog Devices, Inc. All rights reserved.
AD9269
Clock Input Considerations ...................................................... 22
Power Dissipation and Standby Mode .................................... 24
Digital Outputs ........................................................................... 25
Timing ......................................................................................... 25
Built-In Self-Test (BIST) and Output Test .................................. 26
Built-In Self-Test (BIST) ............................................................ 26
Output Test Modes ..................................................................... 26
Channel/Chip Synchronization .................................................... 27
DC and Quadrature Error Correction (QEC) ............................ 28
Serial Port Interface (SPI) .............................................................. 29
Configuration Using the SPI ..................................................... 29
Hardware Interface ..................................................................... 29
Configuration Without the SPI ................................................ 30
SPI Accessible Features .............................................................. 30
Memory Map .................................................................................. 31
Reading the Memory Map Register Table ............................... 31
Open Locations .......................................................................... 31
Default Values ............................................................................. 31
Memory Map Register Table ..................................................... 32
Memory Map Register Descriptions ........................................ 34
Applications Information .............................................................. 36
Design Guidelines ...................................................................... 36
Outline Dimensions ....................................................................... 37
Ordering Guide .......................................................................... 37
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Functional Block Diagram .............................................................. 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
General Description ......................................................................... 3
Specifications ..................................................................................... 4
DC Specifications ......................................................................... 4
AC Specifications .......................................................................... 6
Digital Specifications ................................................................... 7
Switching Specifications .............................................................. 8
Timing Specifications .................................................................. 9
Absolute Maximum Ratings .......................................................... 10
Thermal Characteristics ............................................................ 10
ESD Caution ................................................................................ 10
Pin Configuration and Function Descriptions ........................... 11
Typical Performance Characteristics ........................................... 13
AD9269-80 .................................................................................. 13
AD9269-65 .................................................................................. 15
AD9269-40 .................................................................................. 16
AD9269-20 .................................................................................. 17
Equivalent Circuits ......................................................................... 18
Theory of Operation ...................................................................... 19
ADC Architecture ...................................................................... 19
Analog Input Considerations .................................................... 19
Voltage Reference ....................................................................... 21
REVISION HISTORY
1/10—Revision 0: Initial Version
Rev. 0 | Page 2 of 40