2024年5月22日发(作者：丙山柳)

Kintex-7 FPGA

XC7K480T CES9937 Errata

EN179 (v1.3) February 28, 2012Errata Notification

Introduction

Thank you for participating in the Kintex™-7 FPGAs Engineering Sample Program. As part of this program, we are pleased

to provide to you engineering samples of the devices listed in Table1. Although Xilinx has made every effort to ensure the

highest possible quality, these devices are subject to the limitations described in the following errata.

Devices

These errata apply to the devices shown in Table1.

Table 1:Devices Affected by These Errata

Product Family

Kintex-7

Device

XC7K480T CES9937

JTAG ID

(Revision Code)

0

Packages

All

Speed Grades

-1, -2

Temperature

0 to 85°C

Hardware Errata Details

This section provides a detailed description of each hardware issue known at the release time of this document.

External Memory Interfaces

Phaser Block Divide by Two Mode for DDR3 and DDR2

The Phaser block "divide by two" mode used to implement DDR3 and DDR2 external memory interfaces at frequencies from

303–399MHz is not operational. The Phaser block must be used in 1:1 mode, which restricts the minimum supported DDR3

and DDR2 memory clock frequency to 400MHz (800Mb/s DDR).

Work-around

Select a Memory Clock frequency of 400MHz (DDR3 or DDR2) or higher (DDR3 only) in the Memory Interface

Generator (MIG) tool to ensure that the Phaser block is set to 1:1 mode.

XADC

Integral Nonlinearity

The XADC has a four LSB (~1 mV) integral nonlinearity (INL) error versus the data sheet specifications (DS182,

Kintex-7FPGAs Data Sheet: DC and Switching Characteristics, v1.3) of two LSBs.

XADC On-chip Reference Variation

The XADC on-chip reference source can exceed the DS182, Kintex-7FPGAs Data Sheet: DC and Switching Characteristics

data sheet specific ia ti on of 1.25V ±1% by an additional 0.5%. See Answer Record 44971

for more information on the

impact to XADC measurements when the on-chip reference source is used.

EN179 (v1.3) February 28, 2012

Errata Notification

Kintex-7 FPGA XC7K480T CES9937 Errata

GTX Transceivers

Out-of-Band Signaling

The GTX transceiver circuitry for out-of-band (OOB) signaling is always enabled.

GTX Line Rate

The GTX transceiver operation is limited to a maximum of 6.6 Gb/s.

QPLL Frequency Range

The supported QPLL frequency range is 5.93–6.6 GHz.

TXOUTCLK and RXOUTCLK Ports

The GTX transceiver TXOUTCLK and RXOUTCLK ports can exhibit loss of edges or excessive jitter when used

simultaneously within a GTX channel and with other channels in a transceiver Quad.

The following rules must be followed for proper operation of TXOUTCLK and RXOUTCLK:

•

•

•

Use either TXOUTCLK or RXOUTCLK within any GTX channel, not both.

Use either TXOUTCLK of GTX0 or RXOUTCLK of GTX1, not both.

Use the reference clock directly from IBUFDS_GTXE2 to drive the fabric logic and GTX user clocks when necessary

([TX/RX]USRCLK, [TX/RX]USRCLK2).

Set RXOUTCLKSEL = 3'b000 when RXOUTCLK is not used. Set TXOUTCLKSEL = 3'b000 when TXOUTCLK is not

used.

See Answer Record 43244

for more information.

QPLL Use Mode

The QPLL can lose lock if reset at one temperature extreme and operated at the other.

Work-around

See Answer Record 43244 for the user design work-around.

Receiver Link Margin

The receiver can have a reduction in jitter tolerance when used in full-rate mode (RXOUT_DIV == 1).

Work-around

See Answer Record 43244 for attribute updates and equalization selection.

CPLL Jitter

The GTX CPLL when operated at 3.1 GHz, or above, can exhibit higher jitter when MGTAVTT is higher than nominal.

Transmit Electrical Idle

The transmitter common mode voltage is higher than expected when TX electrical idle is enabled. The electrical idle

detection in the receiver is not impacted when links are AC coupled.

EN179 (v1.3) February 28, 2012

Errata Notification

Kintex-7 FPGA XC7K480T CES9937 Errata

Receiver Detection for PCIe

The Receiver Detection feature used for PCIe® applications is not supported.

Work-around

Set the following attributes to force the transmitter to always detect a receiver:

-

-

-

TX_RXDETECT_REF = 3'b000

RX_CM_SEL = 2'b11

(PMA_RSV2[4], RX_CM_TRIM[2:0]) = 4’b1010

PCIe ASPM Support

ASPM L0s is not supported for Gen 2 (5Gb/s) line rate.

Work-around

Set the following attributes on the Integrated Block for PCI Express to disable ASPM L0s:

EN179 (v1.3) February 28, 2012

Errata Notification

Kintex-7 FPGA XC7K480T CES9937 Errata

Device Type

Package

Speed Grade

XC7K480T

TM

FFG901xxxXXXX

DDxxxxxxxA

1C ES9937

Date Code

Lot Code

Engineering Sample

Operating Range

EN171_01_072111

Figure 1:Example Device Top Mark

Date

10/28/11

12/02/11

01/24/12

02/28/12

Version

1.0

1.1

1.2

1.3

Initial Xilinx release.

Description of Revisions

Added XADC On-chip Reference Variation.

Added Dual Rank for DDR3 and DDR2. Updated Phaser Block Divide by Two Mode for DDR3 and

DDR2 and XADC On-chip Reference Variation. Added Out-of-Band Signaling.

Removed Dual Rank for DDR3 and DDR2; silicon support for dual rank reinstated.

EN179 (v1.3) February 28, 2012

Errata Notification

Kintex-7 FPGA XC7K480T CES9937 Errata

EN179 (v1.3) February 28, 2012

Errata Notification

2024年5月22日发(作者：丙山柳)

Kintex-7 FPGA

XC7K480T CES9937 Errata

EN179 (v1.3) February 28, 2012Errata Notification

Introduction

Thank you for participating in the Kintex™-7 FPGAs Engineering Sample Program. As part of this program, we are pleased

to provide to you engineering samples of the devices listed in Table1. Although Xilinx has made every effort to ensure the

highest possible quality, these devices are subject to the limitations described in the following errata.

Devices

These errata apply to the devices shown in Table1.

Table 1:Devices Affected by These Errata

Product Family

Kintex-7

Device

XC7K480T CES9937

JTAG ID

(Revision Code)

0

Packages

All

Speed Grades

-1, -2

Temperature

0 to 85°C

Hardware Errata Details

This section provides a detailed description of each hardware issue known at the release time of this document.

External Memory Interfaces

Phaser Block Divide by Two Mode for DDR3 and DDR2

The Phaser block "divide by two" mode used to implement DDR3 and DDR2 external memory interfaces at frequencies from

303–399MHz is not operational. The Phaser block must be used in 1:1 mode, which restricts the minimum supported DDR3

and DDR2 memory clock frequency to 400MHz (800Mb/s DDR).

Work-around

Select a Memory Clock frequency of 400MHz (DDR3 or DDR2) or higher (DDR3 only) in the Memory Interface

Generator (MIG) tool to ensure that the Phaser block is set to 1:1 mode.

XADC

Integral Nonlinearity

The XADC has a four LSB (~1 mV) integral nonlinearity (INL) error versus the data sheet specifications (DS182,

Kintex-7FPGAs Data Sheet: DC and Switching Characteristics, v1.3) of two LSBs.

XADC On-chip Reference Variation

The XADC on-chip reference source can exceed the DS182, Kintex-7FPGAs Data Sheet: DC and Switching Characteristics

data sheet specific ia ti on of 1.25V ±1% by an additional 0.5%. See Answer Record 44971

for more information on the

impact to XADC measurements when the on-chip reference source is used.

EN179 (v1.3) February 28, 2012

Errata Notification

Kintex-7 FPGA XC7K480T CES9937 Errata

GTX Transceivers

Out-of-Band Signaling

The GTX transceiver circuitry for out-of-band (OOB) signaling is always enabled.

GTX Line Rate

The GTX transceiver operation is limited to a maximum of 6.6 Gb/s.

QPLL Frequency Range

The supported QPLL frequency range is 5.93–6.6 GHz.

TXOUTCLK and RXOUTCLK Ports

The GTX transceiver TXOUTCLK and RXOUTCLK ports can exhibit loss of edges or excessive jitter when used

simultaneously within a GTX channel and with other channels in a transceiver Quad.

The following rules must be followed for proper operation of TXOUTCLK and RXOUTCLK:

•

•

•

Use either TXOUTCLK or RXOUTCLK within any GTX channel, not both.

Use either TXOUTCLK of GTX0 or RXOUTCLK of GTX1, not both.

Use the reference clock directly from IBUFDS_GTXE2 to drive the fabric logic and GTX user clocks when necessary

([TX/RX]USRCLK, [TX/RX]USRCLK2).

Set RXOUTCLKSEL = 3'b000 when RXOUTCLK is not used. Set TXOUTCLKSEL = 3'b000 when TXOUTCLK is not

used.

See Answer Record 43244

for more information.

QPLL Use Mode

The QPLL can lose lock if reset at one temperature extreme and operated at the other.

Work-around

See Answer Record 43244 for the user design work-around.

Receiver Link Margin

The receiver can have a reduction in jitter tolerance when used in full-rate mode (RXOUT_DIV == 1).

Work-around

See Answer Record 43244 for attribute updates and equalization selection.

CPLL Jitter

The GTX CPLL when operated at 3.1 GHz, or above, can exhibit higher jitter when MGTAVTT is higher than nominal.

Transmit Electrical Idle

The transmitter common mode voltage is higher than expected when TX electrical idle is enabled. The electrical idle

detection in the receiver is not impacted when links are AC coupled.

EN179 (v1.3) February 28, 2012

Errata Notification

Kintex-7 FPGA XC7K480T CES9937 Errata

Receiver Detection for PCIe

The Receiver Detection feature used for PCIe® applications is not supported.

Work-around

Set the following attributes to force the transmitter to always detect a receiver:

-

-

-

TX_RXDETECT_REF = 3'b000

RX_CM_SEL = 2'b11

(PMA_RSV2[4], RX_CM_TRIM[2:0]) = 4’b1010

PCIe ASPM Support

ASPM L0s is not supported for Gen 2 (5Gb/s) line rate.

Work-around

Set the following attributes on the Integrated Block for PCI Express to disable ASPM L0s:

EN179 (v1.3) February 28, 2012

Errata Notification

Kintex-7 FPGA XC7K480T CES9937 Errata

Device Type

Package

Speed Grade

XC7K480T

TM

FFG901xxxXXXX

DDxxxxxxxA

1C ES9937

Date Code

Lot Code

Engineering Sample

Operating Range

EN171_01_072111

Figure 1:Example Device Top Mark

Date

10/28/11

12/02/11

01/24/12

02/28/12

Version

1.0

1.1

1.2

1.3

Initial Xilinx release.

Description of Revisions

Added XADC On-chip Reference Variation.

Added Dual Rank for DDR3 and DDR2. Updated Phaser Block Divide by Two Mode for DDR3 and

DDR2 and XADC On-chip Reference Variation. Added Out-of-Band Signaling.

Removed Dual Rank for DDR3 and DDR2; silicon support for dual rank reinstated.

EN179 (v1.3) February 28, 2012

Errata Notification

Kintex-7 FPGA XC7K480T CES9937 Errata

EN179 (v1.3) February 28, 2012

Errata Notification