2024年5月22日发(作者：剑若)

Device/Package Combinations and Maximum I/Os

I/O Channels By Device

(1)

PackageHX250T

GTX

FF1154/FFG1154

FF1155/FFG1155

FF1923/FFG1923

FF1924/FFG1924

Notes:

all devices, a serial transceiver channel is one set of MGTRXP, MGTRXN, MGTTXP, and MGTTXN pins.

HX255T

GTXGTH

HX380T

GTX

48

GTH

0

12

24

24

40

48

HX565T

GTXGTHGTH

048

24

24

12

24

24

40

48

24

24

Virtex-6 FPGA Packaging

UG365 (v2.6) October 3, 2018

Chapter 1:Packaging Overview

Table1-5 shows the number of available I/Os and the number of differential I/O pairs for

each Virtex-6 device/package combination. The RF packages are only used for the

Virtex-6Q devices (XQ) at the end of the table.

Table 1-5:

Virtex-6

Device

Available I/O Pin/Device/Package Combinations

Virtex-6FPGAPackage

User I/O Pins

Available User I/Os

Differential I/O Pairs

Available User I/Os

Differential I/O Pairs

Available User I/Os

Differential I/O Pairs

Available User I/Os

Differential I/O Pairs

Available User I/Os

Differential I/O Pairs

Available User I/Os

Differential I/O Pairs

Available User I/Os

Differential I/O Pairs

Available User I/Os

Differential I/O Pairs

Available User I/Os

Differential I/O Pairs

Available User I/Os

Differential I/O Pairs

Available User I/Os

Differential I/O Pairs

Available User I/Os

Differential I/O Pairs

Available User I/Os

Differential I/O Pairs

FF484

FF784FF1156FF1759

FF1154FF1155FF1760

FF1923FF1924

RF784RF1156RF1759

XC6VLX75T

240

120

240

120

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

360

180

400

200

400

200

400

200

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

XC6VLX130T

600

300

600

300

600

300

600

300

–

–

–

–

XC6VLX195T

XC6VLX240T

720

360

720

360

840

420

–

–

XC6VLX365T

XC6VLX550T

1200

600

1200

600

–

–

–

–

–

–

–

–

–

–

–

–

XC6VLX760

XC6VSX315T

600

300

600

300

–

–

–

–

–

–

–

–

720

360

840

420

–

–

–

–

–

–

–

–

XC6VSX475T

XC6VHX250T

320

160

–

–

XC6VHX255T

440

220

440

220

–

–

480

240

720

360

720

360

XC6VHX380T

320

160

–

–

640

320

640

320

XC6VHX565T

Virtex-6 FPGA Packaging

UG365 (v2.6) October 3, 2018

Chapter 1:Packaging Overview

Virtex-6 FPGA Packaging

UG365 (v2.6) October 3, 2018

Pin Definitions

Table 1-6:Virtex-6 FPGA Pin Definitions (Cont’d)

Direction

Input

Input

Input

Input

Description

Analog supply for the receiver and transmitter internal circuits. In Virtex-6 HXT

devices containing GTH transceivers.

Analog supply for the PLL and the receiver equalizers. In Virtex-6 HXT devices

containing GTH transceivers.

Analog supply for the transmit driver. In Virtex-6 HXT devices containing GTH

transceivers.

Analog supply for the reference clock buffer and the PLL. In Virtex-6 HXT

devices containing GTH transceivers.

GND reference for the GTH transceiver internal circuitry. These pins should be

connected to the PCB power supply GND reference plane. In Virtex-6 HXT

devices containing GTH transceivers.

GTH Quad positive differential reference clock. In Virtex-6 HXT devices

containing GTH transceivers.

GTH Quad negative differential reference clock. In Virtex-6 HXT devices

containing GTH transceivers.

GTXE1 positive differential reference clock.

GTXE1 negative differential reference clock.

Precision reference resistor pin for internal calibration termination. Always

located in Bank 115.

(4)

Precision reference resistor pin for internal calibration termination. Always

located in Bank 115.

(4)

Internal precision current, voltage, and resistor references for the GTH Quad.

Connect this pin to a 1KΩ resistor with the other terminal of the resistor

connected to GND. In Virtex-6 HXT devices containing GTH transceivers.

Reserved. No Connection; leave floating. In Virtex-6 HXT devices containing

GTH transceivers.

Pin Name

MGTHAVCC

MGTHAVCCRX

MGTHAVTT

MGTHAVCCPLL

MGTHAGNDInput

MGTREFCLKP

MGTREFCLKN

MGTREFCLK0/1P

MGTREFCLK0/1N

MGTAVTTRCAL

MGTRREF

Input

Input

Input

Input

N/A

Input

MGTRBIASInput

RSVD

Notes:

N/A

dedicated pins (JTAG and configuration) are powered by V

CC_CONFIG

(V

CC_0

).

2.V

CCO

pins in unbonded banks must be connected to the V

CCO

for that bank for package migration. Do NOT connect unbonded

V

CCO

pins to different supplies. Without a package migration requirement, V

CCO

pins in unbonded banks can be left unconnected

or tied to a common supply (V

CCO

or ground).

more information on connecting the System Monitor pins, see Virtex-6 FPGA System Monitor User Guide.

FF484 and FF784 contain MGTAVCC and MGTAVTT pins. All other packages contain MGTAVCC_N/_S pins. All the respective

MGTAV* supply pins are connected via planes in the package to the GTXs. The MGTAVCC and MGTAVTT supply all GTXs in a

device. The MGTAVCC_N and MGTAVTT_N supply all GTXs in the upper half (North) and MGTAVCC_S and MGTAVTT_S supply

all GTXs in the lower half (South). If no GTXs are used in the lower half, then the *_S supply pins can be connected to GND. All *_N

pins must always be connected to a supply because the calibration resistor resides in the upper half of the part (bank_115). For more

information consult the Virtex-6 FPGA RocketIO GTX Transceiver User Guide.

Virtex-6 FPGA Packaging

UG365 (v2.6) October 3, 2018

Chapter 1:Packaging Overview

Die Level Bank Numbering and Clock Pins Overview

Figure1-1 through Figure1-11 visually describe a die view of the FPGA bank numbering.

Table1-7 shows the I/O bank names and locations. Not all banks are bonded out in every

part/package combination.

Table 1-7:

Virtex-6 FPGA Bank Numbering

Location

I/O center, left bank column

I/O center, right bank column

I/O outer, left bank column

I/O outer, right bank column

Description

Available in every device.

Available in every device.

Only available in all LX, LXT, and SXT

devices.

Device dependent, for LX, LXT, and SXT

devices only.

Bank Name

IOCL

IOCR

IOOL

IOOR

Virtex-6 FPGA Packaging

UG365 (v2.6) October 3, 2018

2024年5月22日发(作者：剑若)

Device/Package Combinations and Maximum I/Os

I/O Channels By Device

(1)

PackageHX250T

GTX

FF1154/FFG1154

FF1155/FFG1155

FF1923/FFG1923

FF1924/FFG1924

Notes:

all devices, a serial transceiver channel is one set of MGTRXP, MGTRXN, MGTTXP, and MGTTXN pins.

HX255T

GTXGTH

HX380T

GTX

48

GTH

0

12

24

24

40

48

HX565T

GTXGTHGTH

048

24

24

12

24

24

40

48

24

24

Virtex-6 FPGA Packaging

UG365 (v2.6) October 3, 2018

Chapter 1:Packaging Overview

Table1-5 shows the number of available I/Os and the number of differential I/O pairs for

each Virtex-6 device/package combination. The RF packages are only used for the

Virtex-6Q devices (XQ) at the end of the table.

Table 1-5:

Virtex-6

Device

Available I/O Pin/Device/Package Combinations

Virtex-6FPGAPackage

User I/O Pins

Available User I/Os

Differential I/O Pairs

Available User I/Os

Differential I/O Pairs

Available User I/Os

Differential I/O Pairs

Available User I/Os

Differential I/O Pairs

Available User I/Os

Differential I/O Pairs

Available User I/Os

Differential I/O Pairs

Available User I/Os

Differential I/O Pairs

Available User I/Os

Differential I/O Pairs

Available User I/Os

Differential I/O Pairs

Available User I/Os

Differential I/O Pairs

Available User I/Os

Differential I/O Pairs

Available User I/Os

Differential I/O Pairs

Available User I/Os

Differential I/O Pairs

FF484

FF784FF1156FF1759

FF1154FF1155FF1760

FF1923FF1924

RF784RF1156RF1759

XC6VLX75T

240

120

240

120

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

360

180

400

200

400

200

400

200

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

XC6VLX130T

600

300

600

300

600

300

600

300

–

–

–

–

XC6VLX195T

XC6VLX240T

720

360

720

360

840

420

–

–

XC6VLX365T

XC6VLX550T

1200

600

1200

600

–

–

–

–

–

–

–

–

–

–

–

–

XC6VLX760

XC6VSX315T

600

300

600

300

–

–

–

–

–

–

–

–

720

360

840

420

–

–

–

–

–

–

–

–

XC6VSX475T

XC6VHX250T

320

160

–

–

XC6VHX255T

440

220

440

220

–

–

480

240

720

360

720

360

XC6VHX380T

320

160

–

–

640

320

640

320

XC6VHX565T

Virtex-6 FPGA Packaging

UG365 (v2.6) October 3, 2018

Chapter 1:Packaging Overview

Virtex-6 FPGA Packaging

UG365 (v2.6) October 3, 2018

Pin Definitions

Table 1-6:Virtex-6 FPGA Pin Definitions (Cont’d)

Direction

Input

Input

Input

Input

Description

Analog supply for the receiver and transmitter internal circuits. In Virtex-6 HXT

devices containing GTH transceivers.

Analog supply for the PLL and the receiver equalizers. In Virtex-6 HXT devices

containing GTH transceivers.

Analog supply for the transmit driver. In Virtex-6 HXT devices containing GTH

transceivers.

Analog supply for the reference clock buffer and the PLL. In Virtex-6 HXT

devices containing GTH transceivers.

GND reference for the GTH transceiver internal circuitry. These pins should be

connected to the PCB power supply GND reference plane. In Virtex-6 HXT

devices containing GTH transceivers.

GTH Quad positive differential reference clock. In Virtex-6 HXT devices

containing GTH transceivers.

GTH Quad negative differential reference clock. In Virtex-6 HXT devices

containing GTH transceivers.

GTXE1 positive differential reference clock.

GTXE1 negative differential reference clock.

Precision reference resistor pin for internal calibration termination. Always

located in Bank 115.

(4)

Precision reference resistor pin for internal calibration termination. Always

located in Bank 115.

(4)

Internal precision current, voltage, and resistor references for the GTH Quad.

Connect this pin to a 1KΩ resistor with the other terminal of the resistor

connected to GND. In Virtex-6 HXT devices containing GTH transceivers.

Reserved. No Connection; leave floating. In Virtex-6 HXT devices containing

GTH transceivers.

Pin Name

MGTHAVCC

MGTHAVCCRX

MGTHAVTT

MGTHAVCCPLL

MGTHAGNDInput

MGTREFCLKP

MGTREFCLKN

MGTREFCLK0/1P

MGTREFCLK0/1N

MGTAVTTRCAL

MGTRREF

Input

Input

Input

Input

N/A

Input

MGTRBIASInput

RSVD

Notes:

N/A

dedicated pins (JTAG and configuration) are powered by V

CC_CONFIG

(V

CC_0

).

2.V

CCO

pins in unbonded banks must be connected to the V

CCO

for that bank for package migration. Do NOT connect unbonded

V

CCO

pins to different supplies. Without a package migration requirement, V

CCO

pins in unbonded banks can be left unconnected

or tied to a common supply (V

CCO

or ground).

more information on connecting the System Monitor pins, see Virtex-6 FPGA System Monitor User Guide.

FF484 and FF784 contain MGTAVCC and MGTAVTT pins. All other packages contain MGTAVCC_N/_S pins. All the respective

MGTAV* supply pins are connected via planes in the package to the GTXs. The MGTAVCC and MGTAVTT supply all GTXs in a

device. The MGTAVCC_N and MGTAVTT_N supply all GTXs in the upper half (North) and MGTAVCC_S and MGTAVTT_S supply

all GTXs in the lower half (South). If no GTXs are used in the lower half, then the *_S supply pins can be connected to GND. All *_N

pins must always be connected to a supply because the calibration resistor resides in the upper half of the part (bank_115). For more

information consult the Virtex-6 FPGA RocketIO GTX Transceiver User Guide.

Virtex-6 FPGA Packaging

UG365 (v2.6) October 3, 2018

Chapter 1:Packaging Overview

Die Level Bank Numbering and Clock Pins Overview

Figure1-1 through Figure1-11 visually describe a die view of the FPGA bank numbering.

Table1-7 shows the I/O bank names and locations. Not all banks are bonded out in every

part/package combination.

Table 1-7:

Virtex-6 FPGA Bank Numbering

Location

I/O center, left bank column

I/O center, right bank column

I/O outer, left bank column

I/O outer, right bank column

Description

Available in every device.

Available in every device.

Only available in all LX, LXT, and SXT

devices.

Device dependent, for LX, LXT, and SXT

devices only.

Bank Name

IOCL

IOCR

IOOL

IOOR

Virtex-6 FPGA Packaging

UG365 (v2.6) October 3, 2018