2024年5月26日发(作者：莫新之)
M74HCT573
OCTAL D-TYPE LATCH
WITH 3 STATE OUTPUT NON INVERTING
s
s
s
s
s
s
HIGH SPEED:
t
PD
= 21ns (TYP.) at V
CC
= 4.5V
LOW POWER DISSIPATION:
I
CC
= 4µA(MAX.) at T
A
=25°C
COMPATIBLE WITH TTL OUTPUTS :
V
IH
= 2V (MIN.) V
IL
= 0.8V (MAX)
BALANCED PROPAGATION DELAYS:
t
PLH
≅
t
PHL
SYMMETRICAL OUTPUT IMPEDANCE:
|I
OH
| = I
OL
= 6mA (MIN)
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 573
DIPSOPTSSOP
ORDER CODES
PACKAGE
DIP
SOP
TSSOP
TUBE
M74HCT573B1R
M74HCT573M1R
T & R
M74HCT573RM13TR
M74HCT573TTR
DESCRIPTION
The M74HCT573 is an high speed CMOS OCTAL
LATCH WITH 3-STATE OUTPUTS fabricated
with silicon gate C
2
MOS technology.
This 8-BIT D-Type latches is controlled by a latch
enable input (LE) and output enable input (OE).
While the LE input is held at a high level, the Q
outputs will follow the data input precisely. When
the LE is taken low, the Q outputs will be latched
precisely at the logic level of D input data.
While the OE input is at low level, the eight outputs
will be in a normal logic state (high or low logic
level) and while OE is at high level the outputs will
be in a high impedance state.
The 3-State output configuration and the wide
choice of outline make bus organized system
simple.
The M74HCT573 is designed to directly interface
HSC
2
MOS systems with TTL and NMOS
components.
All inputs are equipped with protection circuits
against static discharge and transient excess
voltage.
PIN CONNECTION AND IEC LOGIC SYMBOLS
July 20011/11
芯天下--/
M74HCT573
INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION
PIN No
1
2, 3, 4, 5, 6,
7, 8, 9
12, 13, 14,
15, 16, 17,
18, 19
11
10
20
SYMBOL
OE
D0 to D7
Q0 to Q7
NAME AND FUNCTION
3 State Output Enable
Input (Active LOW)
Data Inputs
3 State Latch Outputs
LE
GND
V
CC
Latch Enable Input
Ground (0V)
Positive Supply Voltage
TRUTH TABLE
INPUTS
OE
H
L
L
L
LE
X
L
H
H
D
X
X
L
H
OUTPUTS
Q
Z
NO CHANGE (*)
L
H
X: Don’t Care
Z: High Impedance
(*): Q Outputs are latched at the time when the LE input is taken low logic level.
LOGIC DIAGRAM
2/11
芯天下--/
2024年5月26日发(作者：莫新之)
M74HCT573
OCTAL D-TYPE LATCH
WITH 3 STATE OUTPUT NON INVERTING
s
s
s
s
s
s
HIGH SPEED:
t
PD
= 21ns (TYP.) at V
CC
= 4.5V
LOW POWER DISSIPATION:
I
CC
= 4µA(MAX.) at T
A
=25°C
COMPATIBLE WITH TTL OUTPUTS :
V
IH
= 2V (MIN.) V
IL
= 0.8V (MAX)
BALANCED PROPAGATION DELAYS:
t
PLH
≅
t
PHL
SYMMETRICAL OUTPUT IMPEDANCE:
|I
OH
| = I
OL
= 6mA (MIN)
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 573
DIPSOPTSSOP
ORDER CODES
PACKAGE
DIP
SOP
TSSOP
TUBE
M74HCT573B1R
M74HCT573M1R
T & R
M74HCT573RM13TR
M74HCT573TTR
DESCRIPTION
The M74HCT573 is an high speed CMOS OCTAL
LATCH WITH 3-STATE OUTPUTS fabricated
with silicon gate C
2
MOS technology.
This 8-BIT D-Type latches is controlled by a latch
enable input (LE) and output enable input (OE).
While the LE input is held at a high level, the Q
outputs will follow the data input precisely. When
the LE is taken low, the Q outputs will be latched
precisely at the logic level of D input data.
While the OE input is at low level, the eight outputs
will be in a normal logic state (high or low logic
level) and while OE is at high level the outputs will
be in a high impedance state.
The 3-State output configuration and the wide
choice of outline make bus organized system
simple.
The M74HCT573 is designed to directly interface
HSC
2
MOS systems with TTL and NMOS
components.
All inputs are equipped with protection circuits
against static discharge and transient excess
voltage.
PIN CONNECTION AND IEC LOGIC SYMBOLS
July 20011/11
芯天下--/
M74HCT573
INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION
PIN No
1
2, 3, 4, 5, 6,
7, 8, 9
12, 13, 14,
15, 16, 17,
18, 19
11
10
20
SYMBOL
OE
D0 to D7
Q0 to Q7
NAME AND FUNCTION
3 State Output Enable
Input (Active LOW)
Data Inputs
3 State Latch Outputs
LE
GND
V
CC
Latch Enable Input
Ground (0V)
Positive Supply Voltage
TRUTH TABLE
INPUTS
OE
H
L
L
L
LE
X
L
H
H
D
X
X
L
H
OUTPUTS
Q
Z
NO CHANGE (*)
L
H
X: Don’t Care
Z: High Impedance
(*): Q Outputs are latched at the time when the LE input is taken low logic level.
LOGIC DIAGRAM
2/11
芯天下--/