MEMORY存储芯片MTFC8GAKAJCN-4M IT中文规格书-USB迷|专注于互联网分享

2024年6月2日发(作者：史飞雪)

Block Lock Feature

The block lock feature protects either the entire device or ranges of blocks from being

programmed and erased. Using the block lock feature is preferable to using WP# to pre-

vent PROGRAM and ERASE operations.

Block lock is enabled and disabled at power-on through the LOCK pin. At power-on, if

LOCK is LOW, all BLOCK LOCK commands are disabled. However if LOCK is HIGH at

power-on, the BLOCK LOCK commands are enabled and, by default, all the blocks on

the device are protected, or locked, from PROGRAM and ERASE operations, even if WP#

is HIGH.

Before the contents of the device can be modified, the device must first be unlocked.

Either a range of blocks or the entire device may be unlocked. PROGRAM and ERASE

operations complete successfully only in the block ranges that have been unlocked.

Blocks, once unlocked, can be locked again to protect them from further PROGRAM

and ERASE operations.

Blocks that are locked can be protected further, or locked tight. When locked tight, the

device’s blocks can no longer be locked or unlocked until the device is power cycled.

WP# and Block Lock

The following is true when the block lock feature is enabled:

•Holding WP# LOW locks all blocks, provided the blocks are not locked tight.

•If WP# is held LOW to lock blocks, then returned to HIGH, a new UNLOCK command

must be issued to unlock blocks.

UNLOCK (23h-24h)

By default at power-on, if LOCK is HIGH, all the blocks are locked and protected from

PROGRAM and ERASE operations. The UNLOCK (23h) command is used to unlock a

range of blocks. Unlocked blocks have no protection and can be programmed or erased.

The UNLOCK command uses two registers, a lower boundary block address register and

an upper boundary block address register, and the invert area bit to determine what

range of blocks are unlocked. When the invert area bit = 0, the range of blocks within

the lower and upper boundary address registers are unlocked. When the invert area bit

= 1, the range of blocks outside the boundaries of the lower and upper boundary ad-

dress registers are unlocked. The lower boundary block address must be less than the

upper boundary block address. The figures below show examples of how the lower and

upper boundary address registers work with the invert area bit.

To unlock a range of blocks, issue the UNLOCK (23h) command followed by the appro-

priate address cycles that indicate the lower boundary block address. Then issue the

24h command followed by the appropriate address cycles that indicate the upper boun-

dary block address. The least significant page address bit, PA0, should be set to 1 if set-

ting the invert area bit; otherwise, it should be 0. The other page address bits should be

Only one range of blocks can be specified in the lower and upper boundary block ad-

dress registers. If after unlocking a range of blocks the UNLOCK command is again is-

sued, the new block address range determines which blocks are unlocked. The previous

unlocked block address range is not retained.

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m60a_4gb_ecc_ – Rev. M 2/12 EN

4Gb, 8Gb, 16Gb: x8, x16 NAND Flash Memory

Two-Plane Operations

Figure 78: TWO-PLANE BLOCK ERASE

CLE

CE#

WE#

ALE

DBSY

BERS

R/B#

RE#

I/Ox

60h

Address input (3 cycles)

1st plane

D1h

60h

Address input (3 cycles)

2nd plane

D0h

70h

or 78h

Status

Don‘t Care

Optional

Figure 79: TWO-PLANE/MULTIPLE-DIE READ STATUS Cycle

CE#

CLE

WE#

ALE

RE#

WHR

I/Ox

78hAddress (3 cycles)

REA

Status output

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m60a_4gb_ecc_ – Rev. M 2/12 EN

4Gb, 8Gb, 16Gb: x8, x16 NAND Flash Memory

Interleaved Die (Multi-LUN) Operations

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m60a_4gb_ecc_ – Rev. M 2/12 EN

4Gb, 8Gb, 16Gb: x8, x16 NAND Flash Memory

Internal ECC and Spare Area Mapping for ECC

Internal ECC enables 5-bit detection and 4-bit error correction in 512 bytes (x8) or 256

words (x16) of the main area and 4 bytes (x8) or 2 words (x16) of metadata I in the spare

area. The metadata II area, which consists of two bytes (x8) and one word (x16), is not

ECC protected. During the busy time for PROGRAM operations, internal ECC generates

parity bits when error detection is complete.

During READ operations the device executes the internal ECC engine (5-bit detection

and 4-bit error correction). When the READ operaton is complete, read status bit 0 must

be checked to determine whether errors larger than four bits have occurred.

Following the READ STATUS command, the device must be returned to read mode by

issuing the 00h command.

Limitations of internal ECC include the spare area, defined in the figures below, and

ECC parity areas that cannot be written to. Each ECC user area (referred to as main and

spare) must be written within one partial-page program so that the NAND device can

calculate the proper ECC parity. The number of partial-page programs within a page

cannot exceed four.

Figure 80: Spare Area Mapping (x8)

Max ByteMin Byte

AddressAddress

ECC ProtectedAreaDescription

1FFh000hYesMain 0User data

3FFh200hYesMain 1User data

5FFh400hYesMain 2User data

7FFh600hYesMain 3User data

801h800hNoReserved

803h802hNoUser metadata II

807h804hYesSpare 0User metadata I

80Fh808hYesSpare 0ECC for main/spare 0

811h810hNoReserved

813h812hNoUser metadata II

817h814hYesSpare 1User metadata I

81Fh818hYesSpare 1ECC for main/spare 1

821h820hNoReserved

823h822hNoUser metadata II

827h824hYesSpare 2User metadata I

82Fh828hYesSpare 2ECC for main/spare 2

831h830hNoUser data

833h832hNoUser metadata II

837h834hYesSpare 3User metadata I

83Fh838hYesSpare 3ECC for main/spare 3

Bad Block

Information

2 bytes

ECC

Parity

8 bytes

User Data

(Metadata)

6 bytes

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m60a_4gb_ecc_ – Rev. M 2/12 EN

4Gb, 8Gb, 16Gb: x8, x16 NAND Flash Memory

Internal ECC and Spare Area Mapping for ECC

Figure 81: Spare Area Mapping (x16)

Max word Min word

Address Address

ECC ProtectedAreaDescription

0FFh 000h Yes Main 0 User data

1FFh 100h Yes Main 1 User data

2FFh 200h Yes Main 2 User data

3FFh 300h Yes Main 3 User data

400h 400h No Reserved

401h 401h No User metadata II

403h 402h Yes Spare 0 User metadata I

407h 404h Yes Spare 0 ECC for main/spare 0

408h 408h No Reserved

409h 409h No User metadata II

40Bh 40Ah Yes Spare 1 User metadata I

40Fh 40Ch Yes Spare 1 ECC for main/spare 1

410h 410h No Reserved

411h 411h No User metadata II

413h 412h Yes Spare 2 User metadata I

417h 414h Yes Spare 2 ECC for main/spare 2

418h 418h No User data

419h 419h No User metadata II

41Bh 41Ah Yes Spare 3 User metadata I

41Fh 41Ch Yes Spare 3 ECC for main/spare 3

Bad Block

Information

1 word

ECC

Parity

4 words

User Data

(Metadata)

3 words