2024年6月2日发(作者：司徒赐)
元器件交易网
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Low-Voltage CMOS 16-Bit
D-Type Flip-Flop
MC74LCX16374
With 5V-Tolerant Inputs and Outputs
(3-State, Non-Inverting)
The MC74LCX16374 is a high performance, non–inverting 16–bit
D–type flip–flop operating from a 2.7 to 3.6V supply. The device is byte
controlled. Each byte has separate Output Enable and Clock Pulse
inputs. These control pins can be tied together for full 16–bit operation.
High impedance TTL compatible inputs significantly reduce current
loading to input drivers while TTL compatible outputs offer improved
switching noise performance. A V
I
specification of 5.5V allows
MC74LCX16374 inputs to be safely driven from 5V devices.
The MC74LCX16374 consists of 16 edge–triggered flip–flops with
individual D–type inputs and 5V–tolerant 3–state true outputs. The
buffered clocks (CPn) and buffered Output Enables (OEn) are common to
all flip–flops within the respective byte. The flip–flops will store the state of
individual D inputs that meet the setup and hold time requirements on the
LOW–to–HIGH Clock (CP) transition. With the OE LOW, the contents of
the flip–flops are available at the outputs. When the OE is HIGH, the
outputs go to the high impedance state. The OE input level does not affect
the operation of the flip–flops.
LOW–VOLTAGE
CMOS 16–BIT
D–TYPE FLIP–FLOP
•
•
•
•
•
•
•
•
•
Designed for 2.7 to 3.6V V
CC
Operation
6.2ns Maximum t
pd
5V Tolerant — Interface Capability With 5V TTL Logic
Supports Live Insertion and Withdrawal
I
OFF
Specification Guarantees High Impedance When V
CC
= 0V
LVTTL Compatible
LVCMOS Compatible
24mA Balanced Output Sink and Source Capability
DT SUFFIX
PLASTIC TSSOP PACKAGE
CASE 1201–01
PIN NAMES
Pins
OEn
CPn
D0–D15
O0–O15
Function
Output Enable Inputs
Clock Pulse Inputs
Inputs
Outputs
Near Zero Static Supply Current in All Three Logic States (20µA)
Substantially Reduces System Power Requirements
•
Latchup Performance Exceeds 500mA
•
ESD Performance: Human Body Model >2000V; Machine Model >200V
11/96
©
Motorola, Inc. 1996
1
REV 1
元器件交易网
MC74LCX16374
LOGIC DIAGRAM
OE1
1
O0
2
O1
3
GND
4
O2
5
O3
6
V
CC
7
O4
8
O5
9
GND
10
O6
11
O7
12
O8
13
O9
14
GND
15
O10
16
O11
17
V
CC
18
O12
19
O13
20
GND
21
O14
22
O15
23
OE2
24
48
CP1
47
D0
46
D1
45
GND
44
D2
43
D3
42
V
CC
41
D4
40
D5
39
GND
38
D6
37
D7
36
D8
35
D9
34
GND
33
D10
32
D11
31
V
CC
30
D12
29
D13
28
GND
27
D14
26
D15
25
CP2
D7
37
D6
38
D5
40
nCP
D
nCP
D
nCP
D
Q
D4
41
nCP
D
8
Q
O4
D12
9
30
nCP
D
nCP
D
nCP
D
nCP
D
19
Q
O12
D3
43
nCP
D
6
Q
O3
D11
32
nCP
D
17
Q
O11
D2
44
nCP
D
5
Q
O2
D10
33
nCP
D
16
Q
O10
D1
46
nCP
D
3
Q
O1
D9
35
nCP
D
14
Q
O9
D0
47
OE1
CP1
1
48
nCP
D
2
Q
OE2
CP2
O0
D8
24
25
nCP
D
13
Q
36
O8
O5
D13
20
Q
29
O13
11
Q
O6
D14
22
Q
27
O14
12
Q
O7
D15
23
Q
26
O15
Inputs
CP1
↑
↑
L
X
OE1
L
L
L
H
D0:7
H
L
X
X
Outputs
O0:7
H
L
O0
Z
CP2
↑
↑
L
X
Inputs
OE2
L
L
L
H
D8:15
H
L
X
X
Outputs
O8:15
H
L
O0
Z
H = High Voltage Level; L = Low Voltage Level; Z = High Impedance State; ↑= Low–to–High Transition; X = High or Low Voltage Level and
Transitions Are Acceptable, for I
CC
reasons, DO NOT FLOAT Inputs
MOTOROLA2LCX DATA
BR1339 — REV 3
2024年6月2日发(作者：司徒赐)
元器件交易网
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Low-Voltage CMOS 16-Bit
D-Type Flip-Flop
MC74LCX16374
With 5V-Tolerant Inputs and Outputs
(3-State, Non-Inverting)
The MC74LCX16374 is a high performance, non–inverting 16–bit
D–type flip–flop operating from a 2.7 to 3.6V supply. The device is byte
controlled. Each byte has separate Output Enable and Clock Pulse
inputs. These control pins can be tied together for full 16–bit operation.
High impedance TTL compatible inputs significantly reduce current
loading to input drivers while TTL compatible outputs offer improved
switching noise performance. A V
I
specification of 5.5V allows
MC74LCX16374 inputs to be safely driven from 5V devices.
The MC74LCX16374 consists of 16 edge–triggered flip–flops with
individual D–type inputs and 5V–tolerant 3–state true outputs. The
buffered clocks (CPn) and buffered Output Enables (OEn) are common to
all flip–flops within the respective byte. The flip–flops will store the state of
individual D inputs that meet the setup and hold time requirements on the
LOW–to–HIGH Clock (CP) transition. With the OE LOW, the contents of
the flip–flops are available at the outputs. When the OE is HIGH, the
outputs go to the high impedance state. The OE input level does not affect
the operation of the flip–flops.
LOW–VOLTAGE
CMOS 16–BIT
D–TYPE FLIP–FLOP
•
•
•
•
•
•
•
•
•
Designed for 2.7 to 3.6V V
CC
Operation
6.2ns Maximum t
pd
5V Tolerant — Interface Capability With 5V TTL Logic
Supports Live Insertion and Withdrawal
I
OFF
Specification Guarantees High Impedance When V
CC
= 0V
LVTTL Compatible
LVCMOS Compatible
24mA Balanced Output Sink and Source Capability
DT SUFFIX
PLASTIC TSSOP PACKAGE
CASE 1201–01
PIN NAMES
Pins
OEn
CPn
D0–D15
O0–O15
Function
Output Enable Inputs
Clock Pulse Inputs
Inputs
Outputs
Near Zero Static Supply Current in All Three Logic States (20µA)
Substantially Reduces System Power Requirements
•
Latchup Performance Exceeds 500mA
•
ESD Performance: Human Body Model >2000V; Machine Model >200V
11/96
©
Motorola, Inc. 1996
1
REV 1
元器件交易网
MC74LCX16374
LOGIC DIAGRAM
OE1
1
O0
2
O1
3
GND
4
O2
5
O3
6
V
CC
7
O4
8
O5
9
GND
10
O6
11
O7
12
O8
13
O9
14
GND
15
O10
16
O11
17
V
CC
18
O12
19
O13
20
GND
21
O14
22
O15
23
OE2
24
48
CP1
47
D0
46
D1
45
GND
44
D2
43
D3
42
V
CC
41
D4
40
D5
39
GND
38
D6
37
D7
36
D8
35
D9
34
GND
33
D10
32
D11
31
V
CC
30
D12
29
D13
28
GND
27
D14
26
D15
25
CP2
D7
37
D6
38
D5
40
nCP
D
nCP
D
nCP
D
Q
D4
41
nCP
D
8
Q
O4
D12
9
30
nCP
D
nCP
D
nCP
D
nCP
D
19
Q
O12
D3
43
nCP
D
6
Q
O3
D11
32
nCP
D
17
Q
O11
D2
44
nCP
D
5
Q
O2
D10
33
nCP
D
16
Q
O10
D1
46
nCP
D
3
Q
O1
D9
35
nCP
D
14
Q
O9
D0
47
OE1
CP1
1
48
nCP
D
2
Q
OE2
CP2
O0
D8
24
25
nCP
D
13
Q
36
O8
O5
D13
20
Q
29
O13
11
Q
O6
D14
22
Q
27
O14
12
Q
O7
D15
23
Q
26
O15
Inputs
CP1
↑
↑
L
X
OE1
L
L
L
H
D0:7
H
L
X
X
Outputs
O0:7
H
L
O0
Z
CP2
↑
↑
L
X
Inputs
OE2
L
L
L
H
D8:15
H
L
X
X
Outputs
O8:15
H
L
O0
Z
H = High Voltage Level; L = Low Voltage Level; Z = High Impedance State; ↑= Low–to–High Transition; X = High or Low Voltage Level and
Transitions Are Acceptable, for I
CC
reasons, DO NOT FLOAT Inputs
MOTOROLA2LCX DATA
BR1339 — REV 3