2024年10月31日发(作者：强安寒)
元器件交易网
CY62136FV30 MoBL
®
2-Mbit (128K x 16) Static RAM
Features
■
■
Very high speed: 45 ns
Temperature ranges
❐
Industrial: –40°C to +85°C
❐
Automotive: –40°C to +125°C
■
Wide voltage range: 2.20V–3.60V
■
■
automatic power down feature that significantly reduces power
consumption by 90% when addresses are not toggling. Placing
the device into standby mode reduces power consumption by
more than 99% when deselected (CE HIGH). The input and
output pins (IO
0
through IO
15
) are placed in a high impedance
state when:
■
■
■
■
Deselected (CE HIGH)
Outputs are disabled (OE HIGH)
Both Byte High Enable and Byte Low Enable are disabled
(BHE, BLE HIGH)
Write operation is active (CE LOW and WE LOW)
Pin compatible with CY62136V, CY62136CV30/CV33, and
CY62136EV30
Ultra low standby power
❐
Typical standby current: 1µA
❐
Maximum standby current: 5 µA (Industrial)
■
Ultra low active power
❐
Typical active current: 1.6 mA at f = 1 MHz (45 ns speed)
■
Easy memory expansion with CE, and OE features
■
■
■
Automatic power down when deselected
CMOS for optimum speed and power
Available in Pb-free 48-ball VFBGA and 44-pin TSOP II
packages
Write to the device by taking Chip Enable (CE) and Write Enable
(WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data
from IO pins (IO
0
through IO
7
) is written into the location
specified on the address pins (A
0
through A
16
). If Byte High
Enable (BHE) is LOW, then data from IO pins (IO
8
through IO
15
)
is written into the location specified on the address pins (A
0
through A
16
).
Read from the device by taking Chip Enable (CE) and Output
Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If
Byte Low Enable (BLE) is LOW, then data from the memory
location specified by the address pins appears on IO
0
to IO
7
. If
Byte High Enable (BHE) is LOW, then data from memory
appears on IO
8
to IO
15
. See the “Truth Table” on page9 for a
complete description of read and write modes.
For best practice recommendations, refer to the Cypress
application note AN1064, SRAM System Guidelines.
Functional Description
The CY62136FV30 is a high performance CMOS static RAM
organized as 128K words by 16 bits. This device features
advanced circuit design to provide ultra low active current. This
is ideal for providing More Battery Life™ (MoBL
®
) in portable
applications such as cellular telephones. The device also has an
Logic Block Diagram
DATA IN DRIVERS
A
10
A
9
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
R
O
W
D
E
C
O
D
E
R
128K x 16
RAM Array
S
E
N
S
E
A
M
P
S
IO
0
–IO
7
IO
8
–IO
15
COLUMN DECODER
A
1
1
A
1
2
A
1
3
A
1
4
A
1
5
A
1
6
BHE
WE
CE
OE
BLE
CypressSemiconductorCorporation
Document Number: 001-08402 Rev. *D
•198 Champion Court•SanJose
,
CA95134-1709•408-943-2600
Revised August 03, 2007
元器件交易网
CY62136FV30 MoBL
®
Product Portfolio
Power Dissipation
ProductRange
V
CC
Range (V)
Min
CY62136FV30LLIndustrial
Automotive
2.2
2.2
Typ
[1]
3.0
3.0
Max
3.6
3.6
Speed
(ns)
Operating I
CC
(mA)
f = 1MHz
Typ
[1]
45 1.6
55 2
Max
2.5
3
f = f
max
Typ
[1]
13
15
Max
18
25
Standby I
SB2
(mA)
Typ
[1]
1
1
Max
5
20
Pin Configuration
Figure 1. 48-Ball VFBGA Pinout
[2, 3]
1
BLE
IO
8
IO
9
V
SS
V
CC
IO
14
IO
15
NC
2
OE
BHE
IO
10
IO
11
IO
12
IO
13
NC
A
8
3
A
0
A
3
A
5
NC
NC
A
14
A
12
A
9
4
A
1
A
4
A
6
A
7
A
16
A
15
A
13
A
10
5
A
2
CE
IO
1
IO
3
IO
4
IO
5
WE
A
11
6
NC
IO
0
IO
2
V
CC
V
SS
IO
6
IO
7
NC
A
B
C
D
E
F
G
H
Figure 2. 44-Pin TSOP II
[2]
A
4
A
3
A
2
A
1
A
0
CE
IO
0
IO
1
IO
2
IO
3
V
CC
V
SS
IO
4
IO
5
IO
6
IO
7
WE
A
16
A
15
A
14
A
13
A
12
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A
5
A
6
A
7
OE
BHE
BLE
IO
15
IO
14
IO
13
IO
12
V
SS
V
CC
IO
11
IO
10
IO
9
IO
8
NC
A
8
A
9
A
10
A
11
NC
Notes
l values are included for reference only and are not guaranteed or tested. Typical values are measured at V
CC
= V
CC(typ)
, T
A
= 25°C.
pins are not connected on the die.
D3, H1, G2, and H6 in the VFBGA package are address expansion pins for 4 Mb, 8 Mb, 16 Mb, and 32 Mb, respectively.
Document Number: 001-08402 Rev. *D Page 2 of 12
元器件交易网
CY62136FV30 MoBL
®
Maximum Ratings
Exceeding the maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Storage Temperature ................................–65°C to + 150°C
Ambient Temperature with
Power Applied ..........................................–55°C to + 125°C
Supply Voltage to Ground
Potential .............................–0.3V to 3.9V (V
CC(max)
+ 0.3V)
DC Voltage Applied to Outputs
in High Z State
[4, 5]
..............–0.3V to 3.9V (V
CC(max)
+ 0.3V)
DC Input Voltage
[4, 5]
..........–0.3V to 3.9V (V
CC(max)
+ 0.3V)
Output Current into Outputs (LOW) ............................20 mA
Static Discharge Voltage ......................................... > 2001V
(MIL-STD-883, Method 3015)
Latch up Current ....................................................> 200 mA
Operating Range
Device
CY62136FV30LL
Range
Industrial
Ambient
Temperature
V
CC
[6]
–40°C to +85°C 2.2V to 3.6V
Automotive–40°C to +125°C
Electrical Characteristics
Over the Operating Range
45 ns (Industrial)
Parameter
V
OH
V
OL
V
IH
V
IL
I
IX
I
OZ
I
CC
Description
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Test Conditions
2.2 < V
CC
< 2.7
2.7 < V
CC
< 3.6
2.2 < V
CC
< 2.7
2.7 < V
CC
< 3.6
2.2 < V
CC
< 2.7
2.7 < V
CC
< 3.6
2.2 < V
CC
< 2.7
2.7 < V
CC
< 3.6
Input Leakage CurrentGND < V
I
< V
CC
Output Leakage
Current
GND < V
O
< V
CC
, Output Disabled
V
CC
= V
CCmax
I
OUT
= 0 mA
CMOS Levels
I
OH
= –0.1 mA
I
OH
= –1.0 mA
I
OL
= 0.1 mA
I
OL
= 2.1mA
1.8
2.2
–0.3
–0.3
–1
–1
13
1.6
1
MinTyp
[1]
2.0
2.4
0.4
0.4
V
CC
+ 0.31.8
V
CC
+ 0.32.2
0.6
0.8
+1
+1
18
2.5
5
–0.3
–0.3
–4
–4
15
2
1
Max
55 ns (Automotive)
MinTyp
[1]
2.0
2.4
0.4
0.4
V
CC
+ 0.3
V
CC
+ 0.3
0.6
0.8
+4
+4
25
3
20µA
MaxUnit
V
V
V
V
V
V
V
V
µA
µA
mA
V
CC
Operating Supply f = f
max
= 1/t
RC
Current
f = 1 MHz
I
SB1
Automatic CE Power
CE > V
CC
– 0.2V,
Down Current — CMOS V
IN
> V
CC
– 0.2V, V
IN
< 0.2V,
Inputs
f = f
max
(Address and Data Only),
f = 0 (OE, WE, BHE, and BLE), V
CC
= 3.60V
Automatic CE Power
CE > V
CC
– 0.2V,
Down Current — CMOS V
IN
> V
CC
– 0.2V or V
IN
< 0.2V,
Inputsf = 0, V
CC
= 3.60V
I
SB2
[7]
15120µA
Capacitance
Tested initially and after any design or process changes that may affect these parameters.
Parameter
C
IN
C
OUT
Description
Input Capacitance
Output Capacitance
Test Conditions
T
A
= 25°C, f = 1 MHz,
V
CC
= V
CC(typ)
Max
10
10
Unit
pF
pF
Notes
4.V
IL(min)
= –2.0V for pulse durations less than 20 ns.
5.V
IH(max)
=V
CC
+0.75V for pulse durations less than 20 ns.
device AC operation assumes a minimum of 100 µs ramp time from 0 to V
CC
(min) and 200 µs wait time after V
CC
stabilization.
chip enable (CE) and byte enables (BHE and BLE) are tied to CMOS levels to meet the I
SB2
/ I
CCDR
specification. Other inputs can be left floating.
Document Number: 001-08402 Rev. *D Page 3 of 12
元器件交易网
CY62136FV30 MoBL
®
Thermal Resistance
Tested initially and after any design or process changes that may affect these parameters
.
Parameter
Θ
JA
Θ
JC
Description
Thermal Resistance
(Junction to Ambient)
Thermal Resistance
(Junction to Case)
Test Conditions
Still air, soldered on a 3 × 4.5 inch,
two layer printed circuit board
VFBGA
75
10
TSOP II
77
13
Unit
°C/W
°C/W
AC Test Loads and Waveforms
Figure 3. AC Test Loads and Waveforms
V
CC
OUTPUT
R1
V
CC
30 pF
INCLUDING
JIG AND
SCOPE
R2
10%
GND
Rise Time = 1 V/ns
ALL INPUT PULSES
90%
90%
10%
Fall Time = 1 V/ns
Equivalent to: THÉVENIN EQUIVALENT
R
TH
OUTPUTV
2.5V (2.2V to 2.7V)
16667
15385
8000
1.20
3.0V (2.7V to 3.6V)
1103
1554
645
1.75
Unit
Ω
Ω
Ω
V
Parameters
R1
R2
R
TH
V
TH
Data Retention Characteristics
Over the Operating Range
Parameter
V
DR
I
CCDR
[7]
t
CDR
[8]
t
R
[9]
Description
V
CC
for Data Retention
Data Retention Current
Chip Deselect to Data Retention Time
Operation Recovery Time
V
CC
= 1.5V, CE > V
CC
- 0.2V, Industrial
V
IN
> V
CC
- 0.2V or V
IN
< 0.2V
Automotive
0
t
RC
ConditionsMin
1.5
4
12
ns
ns
Typ
[1]
MaxUnit
V
µA
Data Retention Waveform
Figure 4. Data Retention Waveform
[10]
V
CC(min)
t
CDR
DATA RETENTION MODE
V
DR
>1.5V
V
CC
CE or
V
CC(min)
t
R
Notes
initially and after any design or process changes that may affect these parameters.
device operation requires linear V
CC
ramp from V
DR
to V
CC(min)
> 100 µs or stable at V
CC(min)
> 100 µs.
is the AND of both BHE and BLE. Deselect the chip by either disabling chip enable signals or by disabling both BHE and BLE.
Document Number: 001-08402 Rev. *D Page 4 of 12
元器件交易网
CY62136FV30 MoBL
®
Switching Characteristics
Over the Operating Range
[11, 12]
Parameter
Read Cycle
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
t
PU
t
PD
t
DBE
t
LZBE
t
HZBE
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low Z
[13]
OE HIGH to High Z
[13, 14]
CE LOW to Low Z
[13]
CE HIGH to High Z
[13, 14]
CE LOW to Power Up
CE HIGH to Power Down
BLE/BHE LOW to Data Valid
BLE/BHE LOW to Low Z
[13]
BLE/BHE HIGH to High Z
[13, 14]
5
18
0
45
22
10
20
10
18
0
55
25
5
18
10
20
10
45
22
5
20
45
45
10
55
25
55
55
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Description
45 ns (Industrial)
MinMax
55 ns (Automotive)
MinMax
Unit
Write Cycle
[15]
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
BW
t
SD
t
HD
t
HZWE
t
LZWE
Write Cycle Time
CE LOW to Write End
Address Setup to Write End
Address Hold from Write End
Address Setup to Write Start
WE Pulse Width
BLE/BHE LOW to Write End
Data Setup to Write End
Data Hold From Write End
WE LOW to High Z
[13, 14]
WE HIGH to Low Z
[13]
10
45
35
35
0
0
35
35
25
0
18
10
55
40
40
0
0
40
40
25
0
20
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
conditions for all parameters, other than tri-state parameters, assume signal transition time of 3 ns (1V/ns) or less, timing reference levels of V
CC(typ)
/2, input pulse
levels of 0 to V
CC(typ)
, and output loading of the specified I
OL
/I
OH
as shown in the “AC Test Loads and Waveforms” on page4.
timing parameters are subject to byte enable signals (BHE or BLE) not switching when chip is disabled. Please see application note AN13842 for further clarification.
any given temperature and voltage condition, t
HZCE
is less than t
LZCE
, t
HZBE
is less than t
LZBE
, t
HZOE
is less than t
LZOE
, and t
HZWE
is less than t
LZWE
for any given
device.
14.t
HZOE
, t
HZCE
, t
HZBE
, and t
HZWE
transitions are measured when the outputs enter a high impedance state.
internal write time of the memory is defined by the overlap of WE, CE
= V
IL
, BHE and/or BLE = V
IL
. All signals are ACTIVE to initiate a write and any of these
signals can terminate a write by going INACTIVE. The data input setup and hold timing are referenced to the edge of the signal that terminates the write.
Document Number: 001-08402 Rev. *D Page 5 of 12
元器件交易网
CY62136FV30 MoBL
®
Switching Waveforms
Figure 5. Read Cycle No.1: Address Transition Controlled.
[16, 17]
t
RC
ADDRESS
t
OHA
DATA OUT
PREVIOUS DATA VALID
t
AA
DATA VALID
Figure 6. Read Cycle No. 2: OE Controlled
[17, 18]
ADDRESS
t
RC
CE
t
PD
t
ACE
OE
t
DOE
BHE/BLE
t
LZOE
t
HZBE
t
DBE
t
LZBE
DATA OUT
HIGH IMPEDANCE
t
LZCE
t
PU
V
CC
SUPPLY
CURRENT
50%
50%
I
CC
I
SB
DATA VALID
HIGH
IMPEDANCE
t
HZOE
t
HZCE
Notes
device is continuously selected. OE, CE = V
IL
, BHE and/or BLE = V
IL
.
is HIGH for read cycle.
s valid before or similar to CE and BHE, BLE transition LOW.
Document Number: 001-08402 Rev. *D Page 6 of 12
元器件交易网
CY62136FV30 MoBL
®
Switching Waveforms
(continued)
Figure 7. Write Cycle No 1: WE Controlled
[15, 19, 20]
t
WC
ADDRESS
t
SCE
CE
t
AW
t
SA
WE
t
PWE
t
HA
BHE/BLE
t
BW
OE
NOTE 21
t
HZOE
t
SD
DATA
IN
t
HD
DATA IO
Figure 8. Write Cycle 2: CE Controlled
[15, 19, 20]
t
WC
ADDRESS
t
SCE
CE
t
SA
WE
t
AW
t
PWE
t
HA
BHE/BLE
t
BW
OE
t
SD
DATAIONOTE 21
t
HZOE
DATA
IN
t
HD
Notes
IO is high impedance if OE = V
IH
.
CE goes HIGH simultaneously with WE = V
IH
, the output remains in a high impedance state.
this period, the IOs are in output state. Do not apply input signals.
Document Number: 001-08402 Rev. *D Page 7 of 12
元器件交易网
CY62136FV30 MoBL
®
Switching Waveforms
(continued)
Figure 9. Write Cycle 3: WE controlled, OE LOW
[20]
t
WC
ADDRESS
t
SCE
CE
BHE/BLE
t
AW
WE
t
SA
t
BW
t
HA
t
PWE
t
SD
DATA IO
NOTE 21
t
HZWE
DATA
IN
t
HD
t
LZWE
Figure 10. Write Cycle 4: BHE/BLE Controlled, OE LOW
[20]
t
WC
ADDRESS
CE
t
SCE
t
AW
BHE/BLE
t
SA
WE
t
HZWE
t
HA
t
BW
t
PWE
t
SD
DATA
IN
t
LZWE
t
HD
DATA IO
NOTE 21
Document Number: 001-08402 Rev. *D Page 8 of 12
元器件交易网
CY62136FV30 MoBL
®
Truth Table
CE
H
X
L
L
L
L
L
L
L
L
L
WE
X
X
H
H
H
H
H
H
L
L
L
OE
X
X
L
L
L
H
H
H
X
X
X
BHEBLE
X
H
L
H
L
L
H
L
L
H
L
X
H
L
L
H
L
L
H
L
L
H
Inputs or Outputs
HighZ
High Z
Data Out (IO
0
–IO
15
)
DataOut(IO
0
–IO
7
);
IO
8
–IO
15
in High Z
Data Out (IO
8
–IO
15
);
IO
0
–IO
7
in High Z
High Z
High Z
High Z
Data In (IO
0
–IO
15
)
Data In (IO
0
–IO
7
);
IO
8
–IO
15
in High Z
Data In (IO
8
–IO
15
);
IO
0
–IO
7
in High Z
Mode
DeselectorPowerDown
Deselect or Power Down
Read
Read
Read
Output Disabled
Output Disabled
Output Disabled
Write
Write
Write
Power
Standby(I
SB
)
Standby (I
SB
)
Active(I
CC
)
Active (I
CC
)
Active (I
CC
)
Active (I
CC
)
Active (I
CC
)
Active (I
CC
)
Active (I
CC
)
Active (I
CC
)
Active (I
CC
)
Document Number: 001-08402 Rev. *D Page 9 of 12
元器件交易网
CY62136FV30 MoBL
®
Ordering Information
Speed
(ns)
45
55
Ordering Code
CY62136FV30LL-45BVXI
CY62136FV30LL-45ZSXI
CY62136FV30LL-55ZSXE
Package
Diagram
Package Type
Operating
Range
Industrial
Automotive
51-8515048-Ball VFBGA (Pb-Free)
51-8508744-Pin TSOP II (Pb-Free)
51-8508744-Pin TSOP II (Pb-Free)
Contact your local Cypress sales representative for availability of these parts.
Package Diagrams
Figure 11. 48-Ball VFBGA (6 x 8 x 1 mm)
TOPVIEW
BOTTOMVIEW
A1CORNER
Ø0.05MC
A1CORNER
123456
Ø0.25MCAB
Ø0.30±0.05(48X)
654321
A
B
C
8
.
0
0
±
0
.
1
0
0
.
7
5
8
.
0
0
±
0
.
1
0
5
.
2
5
D
E
F
G
H
A
B
C
D
E
2
.
6
2
5
F
G
H
A
B
6.00±0.10
A
1.875
0.75
3.75
B
6.00±0.10
0
.
5
5
M
A
X
.
0
.
2
5
C
0.15(4X)
0
.
2
1
±
0
.
0
5
0
.
1
0
C
1
.
0
0
M
A
X
SEATINGPLANE
0
.
2
6
M
A
X
.
C
51-85150-*D
Document Number: 001-08402 Rev. *D Page 10 of 12
元器件交易网
CY62136FV30 MoBL
®
Package Diagrams
(continued)
Figure 12. 44-Pin TSOP II
Document Number: 001-08402 Rev. *D
51-85087-*A
Page 11 of 12
元器件交易网
CY62136FV30 MoBL
®
Document History Page
Document Title: CY62136FV30 MoBL
®
2-Mbit (128K x 16) Static RAM
Document Number: 001-08402
REV.
**
*A
ECN NO.
467351
797956
Issue
Date
See ECN
See ECN
Orig. of
Change
NXR
VKN
Description of Change
New datasheet
Converted from preliminary to final
Changed I
SB1(typ)
and
I
SB1(max)
specification from 0.5
µA to 1.0 µA and
2.5
µA to 5.0 µA, respectively
Changed I
SB2(typ)
and
I
SB2(max)
specification from 0.5
µA to 1.0 µA and
2.5
µA to 5.0 µA, respectively
Changed I
CCDR(typ)
and
I
CCDR(max)
specification from 0.5
µA to 1.0 µA and
2.5
µA to 4.0 µA, respectively
Changed I
CC(max)
specification from 2.25
µA to 2.5 µA
Added Automotive information
Updated Ordering information table
Added footnote 12 related to t
ACE
Added footnote 9 related to I
SB2
and
I
CCDR
Made footnote 13 applicable to AC parameters from t
ACE
*B869500See ECNVKN
*C
*D
901800
1371124
See ECNVKN
See ECNVKN/AESAConverted Automotive information from preliminary to final
Changed I
IX
min spec from –1 µA to –4 µA and I
IX
max spec from +1 µA to +4 µA
Changed I
OZ
min spec from –1 µA to –4 µA and I
OZ
max spec from +1 µA to +4 µA
Changed t
DBE
spec from 55 ns to 25 ns for automotive part
© Cypress Semiconductor Corporation, 2006-2007. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used
for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use
as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support
systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 001-08402 Rev. *D Page 12 of 12
MoBL is a registered trademark and More Battery Life is a trademark of Cypress Semiconductor. All product and company names mentioned in this document are the trademarks of their respective holders
.
Revised August 03, 2007
2024年10月31日发(作者：强安寒)
元器件交易网
CY62136FV30 MoBL
®
2-Mbit (128K x 16) Static RAM
Features
■
■
Very high speed: 45 ns
Temperature ranges
❐
Industrial: –40°C to +85°C
❐
Automotive: –40°C to +125°C
■
Wide voltage range: 2.20V–3.60V
■
■
automatic power down feature that significantly reduces power
consumption by 90% when addresses are not toggling. Placing
the device into standby mode reduces power consumption by
more than 99% when deselected (CE HIGH). The input and
output pins (IO
0
through IO
15
) are placed in a high impedance
state when:
■
■
■
■
Deselected (CE HIGH)
Outputs are disabled (OE HIGH)
Both Byte High Enable and Byte Low Enable are disabled
(BHE, BLE HIGH)
Write operation is active (CE LOW and WE LOW)
Pin compatible with CY62136V, CY62136CV30/CV33, and
CY62136EV30
Ultra low standby power
❐
Typical standby current: 1µA
❐
Maximum standby current: 5 µA (Industrial)
■
Ultra low active power
❐
Typical active current: 1.6 mA at f = 1 MHz (45 ns speed)
■
Easy memory expansion with CE, and OE features
■
■
■
Automatic power down when deselected
CMOS for optimum speed and power
Available in Pb-free 48-ball VFBGA and 44-pin TSOP II
packages
Write to the device by taking Chip Enable (CE) and Write Enable
(WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data
from IO pins (IO
0
through IO
7
) is written into the location
specified on the address pins (A
0
through A
16
). If Byte High
Enable (BHE) is LOW, then data from IO pins (IO
8
through IO
15
)
is written into the location specified on the address pins (A
0
through A
16
).
Read from the device by taking Chip Enable (CE) and Output
Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If
Byte Low Enable (BLE) is LOW, then data from the memory
location specified by the address pins appears on IO
0
to IO
7
. If
Byte High Enable (BHE) is LOW, then data from memory
appears on IO
8
to IO
15
. See the “Truth Table” on page9 for a
complete description of read and write modes.
For best practice recommendations, refer to the Cypress
application note AN1064, SRAM System Guidelines.
Functional Description
The CY62136FV30 is a high performance CMOS static RAM
organized as 128K words by 16 bits. This device features
advanced circuit design to provide ultra low active current. This
is ideal for providing More Battery Life™ (MoBL
®
) in portable
applications such as cellular telephones. The device also has an
Logic Block Diagram
DATA IN DRIVERS
A
10
A
9
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
R
O
W
D
E
C
O
D
E
R
128K x 16
RAM Array
S
E
N
S
E
A
M
P
S
IO
0
–IO
7
IO
8
–IO
15
COLUMN DECODER
A
1
1
A
1
2
A
1
3
A
1
4
A
1
5
A
1
6
BHE
WE
CE
OE
BLE
CypressSemiconductorCorporation
Document Number: 001-08402 Rev. *D
•198 Champion Court•SanJose
,
CA95134-1709•408-943-2600
Revised August 03, 2007
元器件交易网
CY62136FV30 MoBL
®
Product Portfolio
Power Dissipation
ProductRange
V
CC
Range (V)
Min
CY62136FV30LLIndustrial
Automotive
2.2
2.2
Typ
[1]
3.0
3.0
Max
3.6
3.6
Speed
(ns)
Operating I
CC
(mA)
f = 1MHz
Typ
[1]
45 1.6
55 2
Max
2.5
3
f = f
max
Typ
[1]
13
15
Max
18
25
Standby I
SB2
(mA)
Typ
[1]
1
1
Max
5
20
Pin Configuration
Figure 1. 48-Ball VFBGA Pinout
[2, 3]
1
BLE
IO
8
IO
9
V
SS
V
CC
IO
14
IO
15
NC
2
OE
BHE
IO
10
IO
11
IO
12
IO
13
NC
A
8
3
A
0
A
3
A
5
NC
NC
A
14
A
12
A
9
4
A
1
A
4
A
6
A
7
A
16
A
15
A
13
A
10
5
A
2
CE
IO
1
IO
3
IO
4
IO
5
WE
A
11
6
NC
IO
0
IO
2
V
CC
V
SS
IO
6
IO
7
NC
A
B
C
D
E
F
G
H
Figure 2. 44-Pin TSOP II
[2]
A
4
A
3
A
2
A
1
A
0
CE
IO
0
IO
1
IO
2
IO
3
V
CC
V
SS
IO
4
IO
5
IO
6
IO
7
WE
A
16
A
15
A
14
A
13
A
12
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A
5
A
6
A
7
OE
BHE
BLE
IO
15
IO
14
IO
13
IO
12
V
SS
V
CC
IO
11
IO
10
IO
9
IO
8
NC
A
8
A
9
A
10
A
11
NC
Notes
l values are included for reference only and are not guaranteed or tested. Typical values are measured at V
CC
= V
CC(typ)
, T
A
= 25°C.
pins are not connected on the die.
D3, H1, G2, and H6 in the VFBGA package are address expansion pins for 4 Mb, 8 Mb, 16 Mb, and 32 Mb, respectively.
Document Number: 001-08402 Rev. *D Page 2 of 12
元器件交易网
CY62136FV30 MoBL
®
Maximum Ratings
Exceeding the maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Storage Temperature ................................–65°C to + 150°C
Ambient Temperature with
Power Applied ..........................................–55°C to + 125°C
Supply Voltage to Ground
Potential .............................–0.3V to 3.9V (V
CC(max)
+ 0.3V)
DC Voltage Applied to Outputs
in High Z State
[4, 5]
..............–0.3V to 3.9V (V
CC(max)
+ 0.3V)
DC Input Voltage
[4, 5]
..........–0.3V to 3.9V (V
CC(max)
+ 0.3V)
Output Current into Outputs (LOW) ............................20 mA
Static Discharge Voltage ......................................... > 2001V
(MIL-STD-883, Method 3015)
Latch up Current ....................................................> 200 mA
Operating Range
Device
CY62136FV30LL
Range
Industrial
Ambient
Temperature
V
CC
[6]
–40°C to +85°C 2.2V to 3.6V
Automotive–40°C to +125°C
Electrical Characteristics
Over the Operating Range
45 ns (Industrial)
Parameter
V
OH
V
OL
V
IH
V
IL
I
IX
I
OZ
I
CC
Description
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Test Conditions
2.2 < V
CC
< 2.7
2.7 < V
CC
< 3.6
2.2 < V
CC
< 2.7
2.7 < V
CC
< 3.6
2.2 < V
CC
< 2.7
2.7 < V
CC
< 3.6
2.2 < V
CC
< 2.7
2.7 < V
CC
< 3.6
Input Leakage CurrentGND < V
I
< V
CC
Output Leakage
Current
GND < V
O
< V
CC
, Output Disabled
V
CC
= V
CCmax
I
OUT
= 0 mA
CMOS Levels
I
OH
= –0.1 mA
I
OH
= –1.0 mA
I
OL
= 0.1 mA
I
OL
= 2.1mA
1.8
2.2
–0.3
–0.3
–1
–1
13
1.6
1
MinTyp
[1]
2.0
2.4
0.4
0.4
V
CC
+ 0.31.8
V
CC
+ 0.32.2
0.6
0.8
+1
+1
18
2.5
5
–0.3
–0.3
–4
–4
15
2
1
Max
55 ns (Automotive)
MinTyp
[1]
2.0
2.4
0.4
0.4
V
CC
+ 0.3
V
CC
+ 0.3
0.6
0.8
+4
+4
25
3
20µA
MaxUnit
V
V
V
V
V
V
V
V
µA
µA
mA
V
CC
Operating Supply f = f
max
= 1/t
RC
Current
f = 1 MHz
I
SB1
Automatic CE Power
CE > V
CC
– 0.2V,
Down Current — CMOS V
IN
> V
CC
– 0.2V, V
IN
< 0.2V,
Inputs
f = f
max
(Address and Data Only),
f = 0 (OE, WE, BHE, and BLE), V
CC
= 3.60V
Automatic CE Power
CE > V
CC
– 0.2V,
Down Current — CMOS V
IN
> V
CC
– 0.2V or V
IN
< 0.2V,
Inputsf = 0, V
CC
= 3.60V
I
SB2
[7]
15120µA
Capacitance
Tested initially and after any design or process changes that may affect these parameters.
Parameter
C
IN
C
OUT
Description
Input Capacitance
Output Capacitance
Test Conditions
T
A
= 25°C, f = 1 MHz,
V
CC
= V
CC(typ)
Max
10
10
Unit
pF
pF
Notes
4.V
IL(min)
= –2.0V for pulse durations less than 20 ns.
5.V
IH(max)
=V
CC
+0.75V for pulse durations less than 20 ns.
device AC operation assumes a minimum of 100 µs ramp time from 0 to V
CC
(min) and 200 µs wait time after V
CC
stabilization.
chip enable (CE) and byte enables (BHE and BLE) are tied to CMOS levels to meet the I
SB2
/ I
CCDR
specification. Other inputs can be left floating.
Document Number: 001-08402 Rev. *D Page 3 of 12
元器件交易网
CY62136FV30 MoBL
®
Thermal Resistance
Tested initially and after any design or process changes that may affect these parameters
.
Parameter
Θ
JA
Θ
JC
Description
Thermal Resistance
(Junction to Ambient)
Thermal Resistance
(Junction to Case)
Test Conditions
Still air, soldered on a 3 × 4.5 inch,
two layer printed circuit board
VFBGA
75
10
TSOP II
77
13
Unit
°C/W
°C/W
AC Test Loads and Waveforms
Figure 3. AC Test Loads and Waveforms
V
CC
OUTPUT
R1
V
CC
30 pF
INCLUDING
JIG AND
SCOPE
R2
10%
GND
Rise Time = 1 V/ns
ALL INPUT PULSES
90%
90%
10%
Fall Time = 1 V/ns
Equivalent to: THÉVENIN EQUIVALENT
R
TH
OUTPUTV
2.5V (2.2V to 2.7V)
16667
15385
8000
1.20
3.0V (2.7V to 3.6V)
1103
1554
645
1.75
Unit
Ω
Ω
Ω
V
Parameters
R1
R2
R
TH
V
TH
Data Retention Characteristics
Over the Operating Range
Parameter
V
DR
I
CCDR
[7]
t
CDR
[8]
t
R
[9]
Description
V
CC
for Data Retention
Data Retention Current
Chip Deselect to Data Retention Time
Operation Recovery Time
V
CC
= 1.5V, CE > V
CC
- 0.2V, Industrial
V
IN
> V
CC
- 0.2V or V
IN
< 0.2V
Automotive
0
t
RC
ConditionsMin
1.5
4
12
ns
ns
Typ
[1]
MaxUnit
V
µA
Data Retention Waveform
Figure 4. Data Retention Waveform
[10]
V
CC(min)
t
CDR
DATA RETENTION MODE
V
DR
>1.5V
V
CC
CE or
V
CC(min)
t
R
Notes
initially and after any design or process changes that may affect these parameters.
device operation requires linear V
CC
ramp from V
DR
to V
CC(min)
> 100 µs or stable at V
CC(min)
> 100 µs.
is the AND of both BHE and BLE. Deselect the chip by either disabling chip enable signals or by disabling both BHE and BLE.
Document Number: 001-08402 Rev. *D Page 4 of 12
元器件交易网
CY62136FV30 MoBL
®
Switching Characteristics
Over the Operating Range
[11, 12]
Parameter
Read Cycle
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
t
PU
t
PD
t
DBE
t
LZBE
t
HZBE
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low Z
[13]
OE HIGH to High Z
[13, 14]
CE LOW to Low Z
[13]
CE HIGH to High Z
[13, 14]
CE LOW to Power Up
CE HIGH to Power Down
BLE/BHE LOW to Data Valid
BLE/BHE LOW to Low Z
[13]
BLE/BHE HIGH to High Z
[13, 14]
5
18
0
45
22
10
20
10
18
0
55
25
5
18
10
20
10
45
22
5
20
45
45
10
55
25
55
55
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Description
45 ns (Industrial)
MinMax
55 ns (Automotive)
MinMax
Unit
Write Cycle
[15]
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
BW
t
SD
t
HD
t
HZWE
t
LZWE
Write Cycle Time
CE LOW to Write End
Address Setup to Write End
Address Hold from Write End
Address Setup to Write Start
WE Pulse Width
BLE/BHE LOW to Write End
Data Setup to Write End
Data Hold From Write End
WE LOW to High Z
[13, 14]
WE HIGH to Low Z
[13]
10
45
35
35
0
0
35
35
25
0
18
10
55
40
40
0
0
40
40
25
0
20
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
conditions for all parameters, other than tri-state parameters, assume signal transition time of 3 ns (1V/ns) or less, timing reference levels of V
CC(typ)
/2, input pulse
levels of 0 to V
CC(typ)
, and output loading of the specified I
OL
/I
OH
as shown in the “AC Test Loads and Waveforms” on page4.
timing parameters are subject to byte enable signals (BHE or BLE) not switching when chip is disabled. Please see application note AN13842 for further clarification.
any given temperature and voltage condition, t
HZCE
is less than t
LZCE
, t
HZBE
is less than t
LZBE
, t
HZOE
is less than t
LZOE
, and t
HZWE
is less than t
LZWE
for any given
device.
14.t
HZOE
, t
HZCE
, t
HZBE
, and t
HZWE
transitions are measured when the outputs enter a high impedance state.
internal write time of the memory is defined by the overlap of WE, CE
= V
IL
, BHE and/or BLE = V
IL
. All signals are ACTIVE to initiate a write and any of these
signals can terminate a write by going INACTIVE. The data input setup and hold timing are referenced to the edge of the signal that terminates the write.
Document Number: 001-08402 Rev. *D Page 5 of 12
元器件交易网
CY62136FV30 MoBL
®
Switching Waveforms
Figure 5. Read Cycle No.1: Address Transition Controlled.
[16, 17]
t
RC
ADDRESS
t
OHA
DATA OUT
PREVIOUS DATA VALID
t
AA
DATA VALID
Figure 6. Read Cycle No. 2: OE Controlled
[17, 18]
ADDRESS
t
RC
CE
t
PD
t
ACE
OE
t
DOE
BHE/BLE
t
LZOE
t
HZBE
t
DBE
t
LZBE
DATA OUT
HIGH IMPEDANCE
t
LZCE
t
PU
V
CC
SUPPLY
CURRENT
50%
50%
I
CC
I
SB
DATA VALID
HIGH
IMPEDANCE
t
HZOE
t
HZCE
Notes
device is continuously selected. OE, CE = V
IL
, BHE and/or BLE = V
IL
.
is HIGH for read cycle.
s valid before or similar to CE and BHE, BLE transition LOW.
Document Number: 001-08402 Rev. *D Page 6 of 12
元器件交易网
CY62136FV30 MoBL
®
Switching Waveforms
(continued)
Figure 7. Write Cycle No 1: WE Controlled
[15, 19, 20]
t
WC
ADDRESS
t
SCE
CE
t
AW
t
SA
WE
t
PWE
t
HA
BHE/BLE
t
BW
OE
NOTE 21
t
HZOE
t
SD
DATA
IN
t
HD
DATA IO
Figure 8. Write Cycle 2: CE Controlled
[15, 19, 20]
t
WC
ADDRESS
t
SCE
CE
t
SA
WE
t
AW
t
PWE
t
HA
BHE/BLE
t
BW
OE
t
SD
DATAIONOTE 21
t
HZOE
DATA
IN
t
HD
Notes
IO is high impedance if OE = V
IH
.
CE goes HIGH simultaneously with WE = V
IH
, the output remains in a high impedance state.
this period, the IOs are in output state. Do not apply input signals.
Document Number: 001-08402 Rev. *D Page 7 of 12
元器件交易网
CY62136FV30 MoBL
®
Switching Waveforms
(continued)
Figure 9. Write Cycle 3: WE controlled, OE LOW
[20]
t
WC
ADDRESS
t
SCE
CE
BHE/BLE
t
AW
WE
t
SA
t
BW
t
HA
t
PWE
t
SD
DATA IO
NOTE 21
t
HZWE
DATA
IN
t
HD
t
LZWE
Figure 10. Write Cycle 4: BHE/BLE Controlled, OE LOW
[20]
t
WC
ADDRESS
CE
t
SCE
t
AW
BHE/BLE
t
SA
WE
t
HZWE
t
HA
t
BW
t
PWE
t
SD
DATA
IN
t
LZWE
t
HD
DATA IO
NOTE 21
Document Number: 001-08402 Rev. *D Page 8 of 12
元器件交易网
CY62136FV30 MoBL
®
Truth Table
CE
H
X
L
L
L
L
L
L
L
L
L
WE
X
X
H
H
H
H
H
H
L
L
L
OE
X
X
L
L
L
H
H
H
X
X
X
BHEBLE
X
H
L
H
L
L
H
L
L
H
L
X
H
L
L
H
L
L
H
L
L
H
Inputs or Outputs
HighZ
High Z
Data Out (IO
0
–IO
15
)
DataOut(IO
0
–IO
7
);
IO
8
–IO
15
in High Z
Data Out (IO
8
–IO
15
);
IO
0
–IO
7
in High Z
High Z
High Z
High Z
Data In (IO
0
–IO
15
)
Data In (IO
0
–IO
7
);
IO
8
–IO
15
in High Z
Data In (IO
8
–IO
15
);
IO
0
–IO
7
in High Z
Mode
DeselectorPowerDown
Deselect or Power Down
Read
Read
Read
Output Disabled
Output Disabled
Output Disabled
Write
Write
Write
Power
Standby(I
SB
)
Standby (I
SB
)
Active(I
CC
)
Active (I
CC
)
Active (I
CC
)
Active (I
CC
)
Active (I
CC
)
Active (I
CC
)
Active (I
CC
)
Active (I
CC
)
Active (I
CC
)
Document Number: 001-08402 Rev. *D Page 9 of 12
元器件交易网
CY62136FV30 MoBL
®
Ordering Information
Speed
(ns)
45
55
Ordering Code
CY62136FV30LL-45BVXI
CY62136FV30LL-45ZSXI
CY62136FV30LL-55ZSXE
Package
Diagram
Package Type
Operating
Range
Industrial
Automotive
51-8515048-Ball VFBGA (Pb-Free)
51-8508744-Pin TSOP II (Pb-Free)
51-8508744-Pin TSOP II (Pb-Free)
Contact your local Cypress sales representative for availability of these parts.
Package Diagrams
Figure 11. 48-Ball VFBGA (6 x 8 x 1 mm)
TOPVIEW
BOTTOMVIEW
A1CORNER
Ø0.05MC
A1CORNER
123456
Ø0.25MCAB
Ø0.30±0.05(48X)
654321
A
B
C
8
.
0
0
±
0
.
1
0
0
.
7
5
8
.
0
0
±
0
.
1
0
5
.
2
5
D
E
F
G
H
A
B
C
D
E
2
.
6
2
5
F
G
H
A
B
6.00±0.10
A
1.875
0.75
3.75
B
6.00±0.10
0
.
5
5
M
A
X
.
0
.
2
5
C
0.15(4X)
0
.
2
1
±
0
.
0
5
0
.
1
0
C
1
.
0
0
M
A
X
SEATINGPLANE
0
.
2
6
M
A
X
.
C
51-85150-*D
Document Number: 001-08402 Rev. *D Page 10 of 12
元器件交易网
CY62136FV30 MoBL
®
Package Diagrams
(continued)
Figure 12. 44-Pin TSOP II
Document Number: 001-08402 Rev. *D
51-85087-*A
Page 11 of 12
元器件交易网
CY62136FV30 MoBL
®
Document History Page
Document Title: CY62136FV30 MoBL
®
2-Mbit (128K x 16) Static RAM
Document Number: 001-08402
REV.
**
*A
ECN NO.
467351
797956
Issue
Date
See ECN
See ECN
Orig. of
Change
NXR
VKN
Description of Change
New datasheet
Converted from preliminary to final
Changed I
SB1(typ)
and
I
SB1(max)
specification from 0.5
µA to 1.0 µA and
2.5
µA to 5.0 µA, respectively
Changed I
SB2(typ)
and
I
SB2(max)
specification from 0.5
µA to 1.0 µA and
2.5
µA to 5.0 µA, respectively
Changed I
CCDR(typ)
and
I
CCDR(max)
specification from 0.5
µA to 1.0 µA and
2.5
µA to 4.0 µA, respectively
Changed I
CC(max)
specification from 2.25
µA to 2.5 µA
Added Automotive information
Updated Ordering information table
Added footnote 12 related to t
ACE
Added footnote 9 related to I
SB2
and
I
CCDR
Made footnote 13 applicable to AC parameters from t
ACE
*B869500See ECNVKN
*C
*D
901800
1371124
See ECNVKN
See ECNVKN/AESAConverted Automotive information from preliminary to final
Changed I
IX
min spec from –1 µA to –4 µA and I
IX
max spec from +1 µA to +4 µA
Changed I
OZ
min spec from –1 µA to –4 µA and I
OZ
max spec from +1 µA to +4 µA
Changed t
DBE
spec from 55 ns to 25 ns for automotive part
© Cypress Semiconductor Corporation, 2006-2007. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used
for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use
as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support
systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 001-08402 Rev. *D Page 12 of 12
MoBL is a registered trademark and More Battery Life is a trademark of Cypress Semiconductor. All product and company names mentioned in this document are the trademarks of their respective holders
.
Revised August 03, 2007