2024年10月29日发(作者：臧靖荷)
元器件交易网
IF Modulator/Demodulator IC
Technical Data
Features
•Use with HPMX-5001
Up/Down Converter Chip
for DECT Telephone
Applications
•2.7–5.5 V Single Supply
Voltage
•>75 dB RSSI Range
•Internal Data Slicer
•On-chip LO Generation,
Including VCO, Prescalers
and Phase/Frequency
Detector
•Flexible Chip Biasing,
Including Standby Mode
•Supports Reference Crystal
Frequencies of 9, 12, and 16
Times the DECT Bit Rate
(1.152 MHz)
•IF Input Frequency Range
up to 250 MHz
•TQFP-48 Surface Mount
Package
Applications
•DECT, Unlicensed PCS and
ISM Band Handsets,
Basestations and Wireless
LANs
Plastic TQFP-48 Package
–
5
0
0
2
H
9
P
M
X
4
3
3
0
1
9
6
4
3
5
Pin Configuration
4837
136
HPMX–5002
9433
12
6435019
1324
25
7-105
HPMX-5002
Description
The Hewlett-Packard HPMX-5002
IF Modulator/Demodulator
provides all of the active compo-
nents necessary for the demodula-
tion of a downconverted DECT
signal. Designed specifically for
DECT, the HPMX-5002 contains a
down-conversion mixer (to a 2nd
IF), limiting amplifier chain,
discriminator/data slicer, lock
detector, and RSSI circuits. The
LO2 generation is also included
on-chip, via a VCO, dividers, and
phase/frequency detector. The
divide ratios are programmable to
support reference frequencies of
either 9, 12, or 16 times the DECT
bit rate of 1.152␣MHz allowing the
use of common, low cost crystals.
The LO2 VCO can also be utilized in
transmit mode by directly modulat-
ing the external VCO tank. An AGC
loop in the buffered VCO output
suppresses harmonics and reduces
signal level variability.
The HPMX-5002 is designed to meet
the size and power demands of
portable applications. Battery cell
count and cost are reduced due to
the 2.7 V minimum supply voltage.
The TQFP-48 package, combined
with the high level of integration,
means smaller footprints and fewer
components. Flexible chip biasing
takes full advantage of the power
savings inherent in time-duplexed
systems such as DECT.
元器件交易网
1
0
0
k
Ω
4
100 kΩ
5
0.1 µ
3
6
2
7
1
8
100 kΩ
= connector
= terminal
DC post
0.01 µ
0.01 µ
0.01 µ
6 kΩ
1000 p
10 Ω
0.01 µ0.01 µ
100 p
0.01 µ
10 p
2.7 µH
100 p
0.01 µ
0 Ω
3.9 µH
3.9 p
22 p
3 to 10 p
0.01 µ
49.9 Ω
0.01 µ
0.01 µ
0 Ω
48
1
IFOP1
DMOD
1
F
1
P
1
V
S
U
B
D
C
1
B
D
C
1
A
V
C
C
2
V
E
E
2
B
G
R
X
L
O
P
L
L
N
C
N
C
R
X
15 µH
37
36
NC
IF1
VEE1
VCC1
0 Ω
0.01 µ
10 p
10 Ω
0.01 µ
270 nH
0.01 µ
0.01 µ
270 nH
1 p
1.2 k Ω
3.9 µH
68 p
4.7 kΩ
2
2
p
DMODOP
BUF1
BUF2
TCNT
DATA
SLICER
R
S
S
I
0.01 µ
1 p
100 nH
22 p
68 p
4.7 kΩ
IP1
IPDC
VEE5
VCC5
0
.
0
1
µ
1
k
Ω
0.01 µ
0 Ω
1
0
0
0
p
TCSET
DATOP
10 p
20 kΩ
1000 p
RSS1
LKFIL
LKDET
REF
4
9
.
9
Ω
8.2 p
0 Ω
0 Ω
8.2 p
220 nH
8.2 p
1000 p
20 kΩ
20 kΩ
LOCK
DET
1
k
Ω
φ
Freq.
Det.
9/12/16
90/216
OSCOPB
OSCOP
CHARGE
PUMP
VCOADJ
VCOB
12
V
C
O
A
V
C
C
3
V
C
C
4
V
E
E
3
V
E
E
4
D
1
V
1
D
1
V
2
D
1
V
3
A
G
C
P
F
D
25
1324
1 kΩ
1
0
0
0
p
1
0
0
0
p
N
C
N
C
51.1 Ω
0.01 µ
0 Ω
0.01 µ
0 Ω
3.9 p
120 n
10 kΩ
22 p
0.01 µ
10 Ω
654
0.01 µ
0.01 µ
0
Ω
0
.
0
1
µ
10 Ω
0
.
0
1
µ
1
k
Ω
4
4
0
0
p
330 p
0
.
0
1
µ
0
.
0
1
µ
4.7 kΩ
3.3 kΩ
1000 p
12
3
1 kΩ
0 Ω
0.01 µ
10 kΩ
Figure 1. HPMX-5002 Test Board Schematic Diagram.
7-106
元器件交易网
HPMX-5002 Functional Block Diagram
IFIP1
IF1
IFOP1
DMOD
DMODOP
BUF1
BUF2TCSET
IP1
DATA
SLICER
RSSI
DATAOP
RSSI
DIV2
DIV1
OSCOP
OSCOPB
90/216
φ
FREQ.
DET.
BIAS
CONTROL
9/12/16
CHARGE
PUMP
LOCK
DET.
REF
BGR
VCOADJVCOB
VCOADIV3
PFDLKDETPLL
RX
XLO
HPMX-5002 Absolute Maximum Ratings
[1]
SymbolParameter
V
CC
Supply Voltage
Voltage at any Pin
[4]
Power Dissipation
[2,3]
Junction Temperature
Storage Temperature
Units
V
V
mW
°C
°C
Min.
-0.2
-0.2
Max.
7.5
V
CC
+ 0.2
200
+110
+125
Thermal Resistance
[2]
:
θ
jc
= 80°C/W
Notes:
ion of this device in excess
of any of these parameters may
cause permanent damage.
2.T
case
= 25°C
at 10 mW/°C for T
case
> 90°C
CMOS logic inputs, see
Summary Characterization
Information Table.
P
diss
T
STG
-55
HPMX-5002 Guaranteed Electrical Specifications
Unless otherwise noted, all parameters are guaranteed under the following conditions: 2.7 V < V
CC
< 5.5 V.
Test results are based upon use of networks shown in test diagram (see Figure 1). f
in
= 110.592 MHz.
Typical values are for V
CCX
= 3.0 V, T
A
= 25°C.
SymbolParameters and Test .
I
ccx
Total V
ccx
supply current
(PLL locked)
(PLL locked)
RX mode
PLL mode
TX “flywheel” mode
Standby mode
high current mode
low current mode
input matched to 50 Ω
mA
mA
mA
µA
µA
µA
dB
21
16
9
400
30
5
550
50
8
27
20
11.5
100
1000
100
GIF1
VDATOP
VDATOP
Charge pump current
Charge pump current
Mixer power gain from
IP1 to IF1, external load
impedance of 600 Ω
Data slicer output level
Data slicer output level
Logic ‘0’
Logic ‘1’
V
V
0.3
V
ccx
-0.3
7-107
元器件交易网
HPMX-5002 Summary Characterization Information
Typical values measured on test board shown in Figure 1 at V
ccx
= 3.0 V, T
A
= 25°C,
f
in
= 110.592 MHz, f
LO2
= 103.68 MHz, unless otherwise noted.
Symbol
V
IH
V
IL
I
IH
I
IL
P
1 dB
I
IP3
NF
IF1
Z
inIP1
Parameters and Test Conditions
CMOS input high voltage (can be pulled up as high as V
cc
+7V)
CMOS input low voltage
CMOS input high current
CMOS input low current
Mode switching time
Mixer input 1 dB compression point
Mixer input IP3
Mixer SSB noise figure
(see test diagram Fig. 1)
Mixer input impedance
matched to 50 Ω source
matched to 50 Ω source
input matched to 50 Ω
source, 600 Ω load at output
50 MHz < f
in
< 250 MHz
Units
V
V
µA
µA
µS
dBm
dBm
dB
Ω
dB
mV/dB
V
Typ.
≥ V
cc
-0.8
≤ 1.0
<50
> - 50
<1
-23
-17
12
100
75
17
RSSI dynamic rangeNote 1
(for signal input at IFIP1; RSSI output measured with 6 bit ADC)
RSSI voltage change
RSSI output voltage. V
ccx
= 3 V,
V
RSSI
is monotonic
Note 1
2 IF limiter input level:
- 90 dBm
-50 dBm
-20 dBm
Z
outRSSI
IF2f
3 dB
A
VIF2
Z
inIFIP1
V
outLO2
RSSI output impedance
IF2 limiter bandwidth
IF2 limiter voltage gain
IF2 limiter input impedance at pin IFIP1
Prior to limiting, Note 2
Note 2
0.88
1.48
2.04
kΩ
30
MHz
dB
Ω
mVp-p
45
57
600
335
80:1
-142
<100
1.1
LO2 output buffer differential amplitude>1.5 kΩ differential load,
(between OSCOP and OSCOPB)f
vco
=103.68 MHz, V
CC
=3 V
Bit slicer time constant ratio
LO2 VCO output buffer noise floor
(@ 4 MHz offset)
PLL charge pump leakage current
TCSET=0 vs. TCSET=1
tank circuit Q=35dBc/Hz
pA
Logic ‘0’ (unlocked)mA ILKDETLock detector current sink
Notes:
1:RSSI signal is monotonic over stated dynamic range, but not necessarily linear. Voltage change is
defined in the linear region of the transfer curve.
2:IF2 frequency in the range 1 MHz < f < 45 MHz, with 10 nF capacitors from DC1A and DC1B to
ground.
7-108
元器件交易网
HPMX-5002 Pin Description
No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
37
38
39
40
Mnemonic
IFOP1
DMOD
DMODOP
BUF1
BUF2
TCNT
TCSET
DATOP
RSSI
LKFIL
LKDET
REF
VCC3
VEE3
DIV1
DIV2
DIV3
PFD
VEE4
VCC4
AGC
VCOA
VCOB
VCOADJ
OSCOP
OSCOPB
VCC5
VEE5
IPDC
IP1
VCC1
VEE1
IF1
IFIP1
DC1A
VCC2
VEE2
I/O Type
Analog O/P
Analog I/P
Analog O/P
Analog I/P
Analog O/P
Analog DC
CMOS I/P
CMOS O/P
Analog O/P
Analog DC
CMOS O/P
Analog I/P
DC Supply
Ground
CMOS I/P
CMOS I/P
CMOS I/P
Analog O/P
Ground
DC Supply
Analog DC
Analog I/P
Analog O/P
Analog I/P
Analog O/P
Analog O/P
DC Supply
Ground
Analog DC
Analog I/P
DC Supply
Ground
Analog O/P
Analog I/P
Analog DC
DC Supply
Ground
Description
Output of IF amplifier, feeds quadrature network for discriminator
Input to discriminator mixer, driven by output of quadrature network
Output of discriminator mixer, drives external low-pass data filter
Noninverting input of buffer amplifier that drives the data slicer
Output of buffer amplifer that drives the data slicer
External capacitor connection which sets time constant for data slicer
Data slicer time constant select
Output bit stream from data slicer
Receive Signal Strength Indicator output
External capacitor connection which sets time constant for lock detector
Indicates that LO2 PLL is in lock status
Reference signal for LO2 PLL
PLL supply voltage
PLL ground
Controls divide ratio for reference frequency input to the LO2 PLL
Controls divide ratio for reference frequency input to the LO2 PLL
Controls divide ratio for VCO frequency input to the LO2 PLL
LO2 PLL phase/frequency detector charge pump output
LO2 VCO ground
LO2 VCO supply voltage
External capacitor connection to compensate LO2 VCO AGC loop
VCO tank force line
VCO tank sense line
Controls amplitude of buffered LO2 VCO output
Buffered LO2 output (+)
Buffered LO2 output (-)
1st IF supply voltage
1st IF ground
External capacitor connection for decoupling 1st IF bias point
1st IF input signal
IF limiting amplifier supply voltage
IF limiting amplifier ground
Downconverted signal from front-end mixer, drives external filter
(hi-Z output, open collector)
Input to IF limiting amplifier, driven by external filter
(600 Ω impedance, internally set)
External capacitor connection for decoupling IF limiting amplifier
IF limiting amplifier supply voltage
IF limiting amplifier ground
7-109
元器件交易网
HPMX-5002 Pin Description,
continued
No.
41
42
43
44
45
47
18,19,
36,46,
48
Mnemonic
DC1B
VSUB
XLO
PLL
RX
BGR
N/C
I/O Type
Analog DC
Ground
CMOS I/P
CMOS I/P
CMOS I/P
Analog DC
Not
connected
Description
External capacitor connection for decoupling IF limiting amplifier
Substrate connection
Controls bias to VCO and PLL components in conjunction with PLL pin
Controls bias to VCO and PLL components in conjunction with XLO pin
Controls bias to receive signal path, RSSI, data slicer
External capacitor connection for decoupling bandgap reference voltage
All unconnected pins should be connected to a low-noise ground
Table 1: HPMX-5002 Mode Control
Table 2: HPMX-5002 PLL Divider Programming
(CMOS Logic Levels)
Mode
PLL
TX
RX
STBY
“flywheel”
PLL
1
0
1
1
XLO
0
0
0
1
see text
RX
1
1
0
1
(CMOS Logic Levels)
REF divide by:
9
12
16
Not defined
LO2 divide by:
90
216
DIV1
1
0
0
1
X
X
DIV2
0
0
1
1
X
X
DIV3
X
X
X
X
0
1
7-110
元器件交易网
IFIP1
IF1
IFOP1
DMOD
DMODOP
BUF1
BUF2TCSET
IP1
DATA
SLICER
RSSI
DATAOP
RSSI
DIV2
DIV1
OSCOP
OSCOPB
90/216
φ
FREQ.
DET.
BIAS
CONTROL
9/12/16
CHARGE
PUMP
LOCK
DET.
REF
BGR
VCOADJVCOB
VCOADIV3
PFDLKDETPLL
RX
XLO
Figure 2. HPMX-5002 Detailed Block Diagram.
Functional Description
Please refer to Figure 2, Detailed
Block Diagram, above. Figure 2
contains a graphical representa-
tion of all 32 active signal pins of
the HPMX-5002. For clarity, the
supply, ground, and substrate pins
are deleted.
Modes of Operation
The HPMX-5002 supports four
basic modes of operation. The logic
states necessary to program each
mode are listed in Table 1, Mode
Programming. The modes are:
Receive mode (RX),
which is used during the receive
time slot in DECT systems. All
blocks are powered on in this
mode.
LO2 synthesis mode (PLL),
which enables the IC to achieve
phase lock without biasing the
receive signal path, thus saving
power. This is very useful for
DECT blind-slot applications.
Transmit mode (TX),
designed for use when the LO2
VCO is directly modulated by the
DECT data stream for subsequent
up-conversion to the channel
frequency (with the HPMX-5001
DECT Upconverter/Down-
converter). In this mode, only the
VCO and LO2 output buffer are
biased and operational. In order
to use the LO2 VCO as a modula-
tion source, it is necessary to first
program the HPMX-5002 in PLL
mode. Once the loop has achieved
lock, the PLL is then disabled by
setting the PLL pin to a logic 0.
This puts the VCO into “flywheel”
operation, preventing the PLL
from interfering with the modula-
tion of the VCO. Leakage in the
tank circuit shown in Figure 3
allows the VCO to drift at a rate of
2.5 kHz per mS, well within the
DECT specs of 13 kHz per mS.
Standby mode,
where all blocks are powered
down. This mode allows the
system designer to effectively turn
the IC off without having to use
battery control, and also allows
the IC to change quickly to an
active mode.
Detailed Circuit
Description
PLL Section
The PLL section of the
HPMX-5002 contains three major
sections: a set of reference and
LO2 dividers, a phase/frequency
detector with charge pump, and a
lock detector.
The dividers for both the refer-
ence and LO2 signals in the PLL
section are programmable to
accomodate the most popular
DECT reference frequencies and
also to enable the use of higher
1st IF frequencies if desired.
7-111
元器件交易网
Figure␣3 illustrates the logic states
necessary to program both the
reference and LO2 dividers.
The reference divider ratios were
selected to conform to the three
most popular DECT reference
frequencies of 10.368 MHz,
13.824␣MHz, and 18.432 MHz. The
LO2 divider values allow the use
of either a 110.592 MHz or
112.32␣MHz 1st IF with a divide
value of 90 (which yields a LO2 of
103.68 MHz). In addition, the
divide by 216 value permits the
use of a much higher 1st IF
(222.91␣MHz, with a correspond-
ing LO2 of 248.832 MHz), which
enables the use of much smaller
SAW filters and relaxes the image
filtering requirements.
The phase/frequency detector also
incorporates a lock detection
feature. The user must supply a
decoupling capacitor (recom-
mended value of 1 nF) from the
LKFIL pin to ground. If the loop is
not in phase lock, the LKDET pin
will sink up to 1 mA. This open
collector output is utilized so that
this signal can be wire-ORed with
other lock detection circuits, such
as from the 1LO portion of the
system. The pullup resistor can
also be tied to the CMOS positive
supply, thus eliminating potential
problems with CMOS logic high
voltages when different positive
supplies are used between the
radio and the baseband processor.
When the PLL loop phase error is
less than approximately 0.3␣radi-
ans, the LKDET current sink goes
to zero.
VCO Section
The VCO section has two major
components, a sustaining ampli-
fier and a buffered external
output. The sustaining amplifer is
designed to be used with an
external tank circuit, and incorpo-
rates a force (VCOA) and sense
(VCOB) architecture to reduce the
effects of package parasitics. As
described earlier, the VCOB pin
may be overdriven by an external
LO, in which case the on-chip
sustaining amplifier acts as a
buffer stage before the
downconverting mixer.
The buffered external output is a
differential signal (OSCOP,
OSCOPB). The buffer also
incorporates an AGC loop in order
to provide a sinusoidal output
signal with constant amplitude
which is insensitive to variations
in tank Q and loading. This helps
to suppress harmonics and
eliminates therefore the need for
an upconversion filter if the
HPMX-5002 is used in a system
together with the 2.5 GHz
upconverter/downconverter
HPMX-5001. The AGC requires an
external compensation capacitor
(recommended value 1 nF) from
the AGC pin to ground.
Signal Path
The input to the HPMX-5002 is an
AC-coupled IF signal (IP1). The
input buffer before the
downconverting mixer requires a
decoupling capacitor from the
IPDC pin to ground (recom-
mended value 10 pF).
The buffered input is then mixed
with the LO2, and the output of
the mixer (IF1) drives an off-chip
bandpass filter centered at the IF2
frequency (6.9 MHz for a 110.592
MHz 1IF). The filtered signal is
then fed to the IFIP1 pin, which is
the input to the limiting amplifier
chain. The limiting amplifier
requires two external decoupling
capacitors from pins DC1A and
DC1B to ground (recommended
value 10 nF).
7-112
The limiting amplifier chain also
feeds the Received Signal Strength
Indicator (RSSI) block. The RSSI
signal is monotonic over a 75 dB
dynamic range, and in its linear
range varies at 17 mV/dB. The
RSSI signal is designed to be
digitized by the CMOS burst mode
controller.
The output of the limiting ampli-
fier (IFOP1) drives the discrimina-
tor circuit. This signal is fed
directly to one of the input ports
of a Gilbert cell mixer, and it also
drives an external quadrature
network (with a recommended Q
of 8 for optimum performance).
The output of the external quadra-
ture network is then fed into the
other input port of the Gilbert cell
(via the DMOD pin). The output
of the Gilbert cell is taken at the
DMODOP pin, which drives an
external lowpass filter. To aid in
the construction of the filter, a
buffer stage is included on-chip.
The BUF1 pin is the noninverting
input of the buffer, and BUF2 is
the output, which is also con-
nected to the input of the data
slicer.
The data slicer operates on a dual
time constant architecture,
controlled via the TCSET pin.
During the preamble portion of a
DECT timeslot (with TCSET set to
1), the data slicer quickly acquires
the midpoint voltage of the
incoming data stream, correcting
any DC offsets that may have
occurred due to frequency devia-
tions within the DECT specifica-
tion. The value of this initial time
constant is determined by an
external capacitor connected
between TCNT and ground. A
10␣nF capacitor allows the accu-
rate acquisition of the midpoint
voltage within half of the 16-bit
DECT preamble.
元器件交易网
Once the midpoint voltage has
been acquired, TCSET is then
forced to a 0, and the time con-
stant of the midpoint voltage
tracking circuit is increased by a
factor of 80. This effectively
freezes the midpoint voltage from
any variations due to normal data
transitions, but still allows for
some correction of frequency
drifts during the data burst.
The output of the data slicer
(DATOP) is a CMOS-compatible
bitstream. However, it is recom-
mended that an external NPN
amplifier stage be used to drive
the CMOS baseband processor, in
order to minimize the amount of
ground and supply currents in the
HPMX-5002 which might desensi-
tize the chip.
D: 1897.344 MHz
B: 1881.792 MHz
CERAMIC
TX PA
TX FILTER
0: 893.376 MHz Rx
896.832 MHz Tx
9: 885.600 MHz Rx
889.056 MHz Tx
10.368 MHz
X2
Tank
φ
÷N
Freq.
÷12
Det.
T/R
FRONT-END
RF FILTER
RX LNA
CERAMIC
IMAGE
FILTER
HPMX-5001
REFERENCE
OSCILLATOR
32/33
IF2 = 6.912 MHz
IF1 = 110.592 MHz
LC Filter
SAW Channel Filter
LC filter
NetworkFilter
SYNTHESIZER
N=1034-1025 INCL. /32,33 Rx
N=1038-1029 INCL. /32,33 Tx
PFD FREQ. = 864 kHz
Data
Slicer
φ
Freq.
Det.
RSSI
÷9
Lock
Det.
HPMX-5002
RX DATA
÷9
Charge
Pump
PFD FREQ. = 1.152 MHz
Tank
LO2 = 103.68 MHz
RC filter
TX Data
Gaussian LPF
All other connections go to Burst Mode Controller, power source, or ground.
Figure 3. Typical HPMX-5002 Application with HPMX-5001 T/R Chip.
7-113
元器件交易网
Circuit in the IC
Vcc
IFOP1
Pin 1
DMOD
Pin 2
Vcc
DMODOP
Pin 3
Vcc
BUF1
Pin 4
Vcc
BUF2
Pin 5
Figure 4. HPMX-5002 Internal and Equivalent Circuits, Pins 1-5.
7-114
Small Signal Equivalent Circuit
(typical values)
330 Ω
IFOP1
V
9 kΩ
DMOD
330 Ω
DMODOP
V
>50 kΩ
BUF1
650 Ω
BUF2
V
元器件交易网
Circuit in the IC
Vcc
Small Signal Equivalent Circuit
(typical values)
DATAOP
Pin 8
Vcc
Vcc
RSSI
Pin 9
30 kΩ
RSSI
Vcc
RSSI
Pin 11
Vcc
VCOA
VCOB
V
Pins 24, 25
Vcc
65 Ω
OSCOP
OSCOPB
OSCOP
OSCOPS
Pins 27, 28
V
Figure 5. HPMX-5002 Internal and Equivalent Circuits, Pins 8, 9, 11, 24, 25, 27, and 28.
7-115
元器件交易网
Circuit in the ICSmall Signal Equivalent Circuit
Vcc
Pin 32
IP1
Vcc
IF1
Pin 35
Vcc
V
Pin 37
IFIP1
Figure 6. HPMX-5002 Internal and Equivalent Circuits, Pins 32, 35, and 37.
7-116
(typical values)
IP1
100 Ω
IFIP1
600 Ω
元器件交易网
Package Dimensions 48 Pin Thin Quad Flat Package
All dimensions shown in mm.
9.0±0.25
7.0±0.1
9.0±0.25
7.0±0.1
0.22 typ.0.5
1.4±0.05
0.05 min., 0.1 max.
0.6+0.15, -0.10
Part Number Ordering Information
Part Number
HPMX-5002-STR
HPMX-5002-TR1
HPMX-5002-TY1
No. of Devices
10
1000
250
Container
Strip
Tape and Reel
Tray
7-117
元器件交易网
Tape Dimensions and Product Orientation for Outline TQFP-48
REEL
CARRIER
TAPE
USER
FEED
DIRECTION
COVER TAPE
2.0 (See Note 7)
0.30 ± 0.05
4.0 (See Note 2)
1.5+0.1/-0.0 DIA
1.75
R 0.5 (2)
1.6 (2)
5.0
B
O
7.5 (See Note 7)
16.0 ± 0.3
HPMX–50029433
6435
019
K
1
K
O
1.5 Min.
6.4 (2)
A
O
12.0
Cover tape width = 13.3 ± 0.1 mm
Cover tape thickness = 0.051 mm (0.002 inch)
NOTES:
1. Dimensions are in millimeters
2. 10 sprocket hole pitch cumulative tolerance ±0.2
3. Chamber not to exceed 1 mm in 100 mm
4. Material: black conductive Advantek™ polystyrene
5. A
O
and B
O
measured on a plane 0.3 mm above the bottom of the pocket.
6. K
O
measured from a plane on the inside bottom of the pocket to the top surface of the carrier.
7. Pocket position relative to sprocket hole measured as true position of pocket, not pocket hole.
A
O
= 9.3 mm
B
O
= 9.3 mm
K
O
= 2.2 mm
K
1
= 1.6 mm
7-118
2024年10月29日发(作者：臧靖荷)
元器件交易网
IF Modulator/Demodulator IC
Technical Data
Features
•Use with HPMX-5001
Up/Down Converter Chip
for DECT Telephone
Applications
•2.7–5.5 V Single Supply
Voltage
•>75 dB RSSI Range
•Internal Data Slicer
•On-chip LO Generation,
Including VCO, Prescalers
and Phase/Frequency
Detector
•Flexible Chip Biasing,
Including Standby Mode
•Supports Reference Crystal
Frequencies of 9, 12, and 16
Times the DECT Bit Rate
(1.152 MHz)
•IF Input Frequency Range
up to 250 MHz
•TQFP-48 Surface Mount
Package
Applications
•DECT, Unlicensed PCS and
ISM Band Handsets,
Basestations and Wireless
LANs
Plastic TQFP-48 Package
–
5
0
0
2
H
9
P
M
X
4
3
3
0
1
9
6
4
3
5
Pin Configuration
4837
136
HPMX–5002
9433
12
6435019
1324
25
7-105
HPMX-5002
Description
The Hewlett-Packard HPMX-5002
IF Modulator/Demodulator
provides all of the active compo-
nents necessary for the demodula-
tion of a downconverted DECT
signal. Designed specifically for
DECT, the HPMX-5002 contains a
down-conversion mixer (to a 2nd
IF), limiting amplifier chain,
discriminator/data slicer, lock
detector, and RSSI circuits. The
LO2 generation is also included
on-chip, via a VCO, dividers, and
phase/frequency detector. The
divide ratios are programmable to
support reference frequencies of
either 9, 12, or 16 times the DECT
bit rate of 1.152␣MHz allowing the
use of common, low cost crystals.
The LO2 VCO can also be utilized in
transmit mode by directly modulat-
ing the external VCO tank. An AGC
loop in the buffered VCO output
suppresses harmonics and reduces
signal level variability.
The HPMX-5002 is designed to meet
the size and power demands of
portable applications. Battery cell
count and cost are reduced due to
the 2.7 V minimum supply voltage.
The TQFP-48 package, combined
with the high level of integration,
means smaller footprints and fewer
components. Flexible chip biasing
takes full advantage of the power
savings inherent in time-duplexed
systems such as DECT.
元器件交易网
1
0
0
k
Ω
4
100 kΩ
5
0.1 µ
3
6
2
7
1
8
100 kΩ
= connector
= terminal
DC post
0.01 µ
0.01 µ
0.01 µ
6 kΩ
1000 p
10 Ω
0.01 µ0.01 µ
100 p
0.01 µ
10 p
2.7 µH
100 p
0.01 µ
0 Ω
3.9 µH
3.9 p
22 p
3 to 10 p
0.01 µ
49.9 Ω
0.01 µ
0.01 µ
0 Ω
48
1
IFOP1
DMOD
1
F
1
P
1
V
S
U
B
D
C
1
B
D
C
1
A
V
C
C
2
V
E
E
2
B
G
R
X
L
O
P
L
L
N
C
N
C
R
X
15 µH
37
36
NC
IF1
VEE1
VCC1
0 Ω
0.01 µ
10 p
10 Ω
0.01 µ
270 nH
0.01 µ
0.01 µ
270 nH
1 p
1.2 k Ω
3.9 µH
68 p
4.7 kΩ
2
2
p
DMODOP
BUF1
BUF2
TCNT
DATA
SLICER
R
S
S
I
0.01 µ
1 p
100 nH
22 p
68 p
4.7 kΩ
IP1
IPDC
VEE5
VCC5
0
.
0
1
µ
1
k
Ω
0.01 µ
0 Ω
1
0
0
0
p
TCSET
DATOP
10 p
20 kΩ
1000 p
RSS1
LKFIL
LKDET
REF
4
9
.
9
Ω
8.2 p
0 Ω
0 Ω
8.2 p
220 nH
8.2 p
1000 p
20 kΩ
20 kΩ
LOCK
DET
1
k
Ω
φ
Freq.
Det.
9/12/16
90/216
OSCOPB
OSCOP
CHARGE
PUMP
VCOADJ
VCOB
12
V
C
O
A
V
C
C
3
V
C
C
4
V
E
E
3
V
E
E
4
D
1
V
1
D
1
V
2
D
1
V
3
A
G
C
P
F
D
25
1324
1 kΩ
1
0
0
0
p
1
0
0
0
p
N
C
N
C
51.1 Ω
0.01 µ
0 Ω
0.01 µ
0 Ω
3.9 p
120 n
10 kΩ
22 p
0.01 µ
10 Ω
654
0.01 µ
0.01 µ
0
Ω
0
.
0
1
µ
10 Ω
0
.
0
1
µ
1
k
Ω
4
4
0
0
p
330 p
0
.
0
1
µ
0
.
0
1
µ
4.7 kΩ
3.3 kΩ
1000 p
12
3
1 kΩ
0 Ω
0.01 µ
10 kΩ
Figure 1. HPMX-5002 Test Board Schematic Diagram.
7-106
元器件交易网
HPMX-5002 Functional Block Diagram
IFIP1
IF1
IFOP1
DMOD
DMODOP
BUF1
BUF2TCSET
IP1
DATA
SLICER
RSSI
DATAOP
RSSI
DIV2
DIV1
OSCOP
OSCOPB
90/216
φ
FREQ.
DET.
BIAS
CONTROL
9/12/16
CHARGE
PUMP
LOCK
DET.
REF
BGR
VCOADJVCOB
VCOADIV3
PFDLKDETPLL
RX
XLO
HPMX-5002 Absolute Maximum Ratings
[1]
SymbolParameter
V
CC
Supply Voltage
Voltage at any Pin
[4]
Power Dissipation
[2,3]
Junction Temperature
Storage Temperature
Units
V
V
mW
°C
°C
Min.
-0.2
-0.2
Max.
7.5
V
CC
+ 0.2
200
+110
+125
Thermal Resistance
[2]
:
θ
jc
= 80°C/W
Notes:
ion of this device in excess
of any of these parameters may
cause permanent damage.
2.T
case
= 25°C
at 10 mW/°C for T
case
> 90°C
CMOS logic inputs, see
Summary Characterization
Information Table.
P
diss
T
STG
-55
HPMX-5002 Guaranteed Electrical Specifications
Unless otherwise noted, all parameters are guaranteed under the following conditions: 2.7 V < V
CC
< 5.5 V.
Test results are based upon use of networks shown in test diagram (see Figure 1). f
in
= 110.592 MHz.
Typical values are for V
CCX
= 3.0 V, T
A
= 25°C.
SymbolParameters and Test .
I
ccx
Total V
ccx
supply current
(PLL locked)
(PLL locked)
RX mode
PLL mode
TX “flywheel” mode
Standby mode
high current mode
low current mode
input matched to 50 Ω
mA
mA
mA
µA
µA
µA
dB
21
16
9
400
30
5
550
50
8
27
20
11.5
100
1000
100
GIF1
VDATOP
VDATOP
Charge pump current
Charge pump current
Mixer power gain from
IP1 to IF1, external load
impedance of 600 Ω
Data slicer output level
Data slicer output level
Logic ‘0’
Logic ‘1’
V
V
0.3
V
ccx
-0.3
7-107
元器件交易网
HPMX-5002 Summary Characterization Information
Typical values measured on test board shown in Figure 1 at V
ccx
= 3.0 V, T
A
= 25°C,
f
in
= 110.592 MHz, f
LO2
= 103.68 MHz, unless otherwise noted.
Symbol
V
IH
V
IL
I
IH
I
IL
P
1 dB
I
IP3
NF
IF1
Z
inIP1
Parameters and Test Conditions
CMOS input high voltage (can be pulled up as high as V
cc
+7V)
CMOS input low voltage
CMOS input high current
CMOS input low current
Mode switching time
Mixer input 1 dB compression point
Mixer input IP3
Mixer SSB noise figure
(see test diagram Fig. 1)
Mixer input impedance
matched to 50 Ω source
matched to 50 Ω source
input matched to 50 Ω
source, 600 Ω load at output
50 MHz < f
in
< 250 MHz
Units
V
V
µA
µA
µS
dBm
dBm
dB
Ω
dB
mV/dB
V
Typ.
≥ V
cc
-0.8
≤ 1.0
<50
> - 50
<1
-23
-17
12
100
75
17
RSSI dynamic rangeNote 1
(for signal input at IFIP1; RSSI output measured with 6 bit ADC)
RSSI voltage change
RSSI output voltage. V
ccx
= 3 V,
V
RSSI
is monotonic
Note 1
2 IF limiter input level:
- 90 dBm
-50 dBm
-20 dBm
Z
outRSSI
IF2f
3 dB
A
VIF2
Z
inIFIP1
V
outLO2
RSSI output impedance
IF2 limiter bandwidth
IF2 limiter voltage gain
IF2 limiter input impedance at pin IFIP1
Prior to limiting, Note 2
Note 2
0.88
1.48
2.04
kΩ
30
MHz
dB
Ω
mVp-p
45
57
600
335
80:1
-142
<100
1.1
LO2 output buffer differential amplitude>1.5 kΩ differential load,
(between OSCOP and OSCOPB)f
vco
=103.68 MHz, V
CC
=3 V
Bit slicer time constant ratio
LO2 VCO output buffer noise floor
(@ 4 MHz offset)
PLL charge pump leakage current
TCSET=0 vs. TCSET=1
tank circuit Q=35dBc/Hz
pA
Logic ‘0’ (unlocked)mA ILKDETLock detector current sink
Notes:
1:RSSI signal is monotonic over stated dynamic range, but not necessarily linear. Voltage change is
defined in the linear region of the transfer curve.
2:IF2 frequency in the range 1 MHz < f < 45 MHz, with 10 nF capacitors from DC1A and DC1B to
ground.
7-108
元器件交易网
HPMX-5002 Pin Description
No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
37
38
39
40
Mnemonic
IFOP1
DMOD
DMODOP
BUF1
BUF2
TCNT
TCSET
DATOP
RSSI
LKFIL
LKDET
REF
VCC3
VEE3
DIV1
DIV2
DIV3
PFD
VEE4
VCC4
AGC
VCOA
VCOB
VCOADJ
OSCOP
OSCOPB
VCC5
VEE5
IPDC
IP1
VCC1
VEE1
IF1
IFIP1
DC1A
VCC2
VEE2
I/O Type
Analog O/P
Analog I/P
Analog O/P
Analog I/P
Analog O/P
Analog DC
CMOS I/P
CMOS O/P
Analog O/P
Analog DC
CMOS O/P
Analog I/P
DC Supply
Ground
CMOS I/P
CMOS I/P
CMOS I/P
Analog O/P
Ground
DC Supply
Analog DC
Analog I/P
Analog O/P
Analog I/P
Analog O/P
Analog O/P
DC Supply
Ground
Analog DC
Analog I/P
DC Supply
Ground
Analog O/P
Analog I/P
Analog DC
DC Supply
Ground
Description
Output of IF amplifier, feeds quadrature network for discriminator
Input to discriminator mixer, driven by output of quadrature network
Output of discriminator mixer, drives external low-pass data filter
Noninverting input of buffer amplifier that drives the data slicer
Output of buffer amplifer that drives the data slicer
External capacitor connection which sets time constant for data slicer
Data slicer time constant select
Output bit stream from data slicer
Receive Signal Strength Indicator output
External capacitor connection which sets time constant for lock detector
Indicates that LO2 PLL is in lock status
Reference signal for LO2 PLL
PLL supply voltage
PLL ground
Controls divide ratio for reference frequency input to the LO2 PLL
Controls divide ratio for reference frequency input to the LO2 PLL
Controls divide ratio for VCO frequency input to the LO2 PLL
LO2 PLL phase/frequency detector charge pump output
LO2 VCO ground
LO2 VCO supply voltage
External capacitor connection to compensate LO2 VCO AGC loop
VCO tank force line
VCO tank sense line
Controls amplitude of buffered LO2 VCO output
Buffered LO2 output (+)
Buffered LO2 output (-)
1st IF supply voltage
1st IF ground
External capacitor connection for decoupling 1st IF bias point
1st IF input signal
IF limiting amplifier supply voltage
IF limiting amplifier ground
Downconverted signal from front-end mixer, drives external filter
(hi-Z output, open collector)
Input to IF limiting amplifier, driven by external filter
(600 Ω impedance, internally set)
External capacitor connection for decoupling IF limiting amplifier
IF limiting amplifier supply voltage
IF limiting amplifier ground
7-109
元器件交易网
HPMX-5002 Pin Description,
continued
No.
41
42
43
44
45
47
18,19,
36,46,
48
Mnemonic
DC1B
VSUB
XLO
PLL
RX
BGR
N/C
I/O Type
Analog DC
Ground
CMOS I/P
CMOS I/P
CMOS I/P
Analog DC
Not
connected
Description
External capacitor connection for decoupling IF limiting amplifier
Substrate connection
Controls bias to VCO and PLL components in conjunction with PLL pin
Controls bias to VCO and PLL components in conjunction with XLO pin
Controls bias to receive signal path, RSSI, data slicer
External capacitor connection for decoupling bandgap reference voltage
All unconnected pins should be connected to a low-noise ground
Table 1: HPMX-5002 Mode Control
Table 2: HPMX-5002 PLL Divider Programming
(CMOS Logic Levels)
Mode
PLL
TX
RX
STBY
“flywheel”
PLL
1
0
1
1
XLO
0
0
0
1
see text
RX
1
1
0
1
(CMOS Logic Levels)
REF divide by:
9
12
16
Not defined
LO2 divide by:
90
216
DIV1
1
0
0
1
X
X
DIV2
0
0
1
1
X
X
DIV3
X
X
X
X
0
1
7-110
元器件交易网
IFIP1
IF1
IFOP1
DMOD
DMODOP
BUF1
BUF2TCSET
IP1
DATA
SLICER
RSSI
DATAOP
RSSI
DIV2
DIV1
OSCOP
OSCOPB
90/216
φ
FREQ.
DET.
BIAS
CONTROL
9/12/16
CHARGE
PUMP
LOCK
DET.
REF
BGR
VCOADJVCOB
VCOADIV3
PFDLKDETPLL
RX
XLO
Figure 2. HPMX-5002 Detailed Block Diagram.
Functional Description
Please refer to Figure 2, Detailed
Block Diagram, above. Figure 2
contains a graphical representa-
tion of all 32 active signal pins of
the HPMX-5002. For clarity, the
supply, ground, and substrate pins
are deleted.
Modes of Operation
The HPMX-5002 supports four
basic modes of operation. The logic
states necessary to program each
mode are listed in Table 1, Mode
Programming. The modes are:
Receive mode (RX),
which is used during the receive
time slot in DECT systems. All
blocks are powered on in this
mode.
LO2 synthesis mode (PLL),
which enables the IC to achieve
phase lock without biasing the
receive signal path, thus saving
power. This is very useful for
DECT blind-slot applications.
Transmit mode (TX),
designed for use when the LO2
VCO is directly modulated by the
DECT data stream for subsequent
up-conversion to the channel
frequency (with the HPMX-5001
DECT Upconverter/Down-
converter). In this mode, only the
VCO and LO2 output buffer are
biased and operational. In order
to use the LO2 VCO as a modula-
tion source, it is necessary to first
program the HPMX-5002 in PLL
mode. Once the loop has achieved
lock, the PLL is then disabled by
setting the PLL pin to a logic 0.
This puts the VCO into “flywheel”
operation, preventing the PLL
from interfering with the modula-
tion of the VCO. Leakage in the
tank circuit shown in Figure 3
allows the VCO to drift at a rate of
2.5 kHz per mS, well within the
DECT specs of 13 kHz per mS.
Standby mode,
where all blocks are powered
down. This mode allows the
system designer to effectively turn
the IC off without having to use
battery control, and also allows
the IC to change quickly to an
active mode.
Detailed Circuit
Description
PLL Section
The PLL section of the
HPMX-5002 contains three major
sections: a set of reference and
LO2 dividers, a phase/frequency
detector with charge pump, and a
lock detector.
The dividers for both the refer-
ence and LO2 signals in the PLL
section are programmable to
accomodate the most popular
DECT reference frequencies and
also to enable the use of higher
1st IF frequencies if desired.
7-111
元器件交易网
Figure␣3 illustrates the logic states
necessary to program both the
reference and LO2 dividers.
The reference divider ratios were
selected to conform to the three
most popular DECT reference
frequencies of 10.368 MHz,
13.824␣MHz, and 18.432 MHz. The
LO2 divider values allow the use
of either a 110.592 MHz or
112.32␣MHz 1st IF with a divide
value of 90 (which yields a LO2 of
103.68 MHz). In addition, the
divide by 216 value permits the
use of a much higher 1st IF
(222.91␣MHz, with a correspond-
ing LO2 of 248.832 MHz), which
enables the use of much smaller
SAW filters and relaxes the image
filtering requirements.
The phase/frequency detector also
incorporates a lock detection
feature. The user must supply a
decoupling capacitor (recom-
mended value of 1 nF) from the
LKFIL pin to ground. If the loop is
not in phase lock, the LKDET pin
will sink up to 1 mA. This open
collector output is utilized so that
this signal can be wire-ORed with
other lock detection circuits, such
as from the 1LO portion of the
system. The pullup resistor can
also be tied to the CMOS positive
supply, thus eliminating potential
problems with CMOS logic high
voltages when different positive
supplies are used between the
radio and the baseband processor.
When the PLL loop phase error is
less than approximately 0.3␣radi-
ans, the LKDET current sink goes
to zero.
VCO Section
The VCO section has two major
components, a sustaining ampli-
fier and a buffered external
output. The sustaining amplifer is
designed to be used with an
external tank circuit, and incorpo-
rates a force (VCOA) and sense
(VCOB) architecture to reduce the
effects of package parasitics. As
described earlier, the VCOB pin
may be overdriven by an external
LO, in which case the on-chip
sustaining amplifier acts as a
buffer stage before the
downconverting mixer.
The buffered external output is a
differential signal (OSCOP,
OSCOPB). The buffer also
incorporates an AGC loop in order
to provide a sinusoidal output
signal with constant amplitude
which is insensitive to variations
in tank Q and loading. This helps
to suppress harmonics and
eliminates therefore the need for
an upconversion filter if the
HPMX-5002 is used in a system
together with the 2.5 GHz
upconverter/downconverter
HPMX-5001. The AGC requires an
external compensation capacitor
(recommended value 1 nF) from
the AGC pin to ground.
Signal Path
The input to the HPMX-5002 is an
AC-coupled IF signal (IP1). The
input buffer before the
downconverting mixer requires a
decoupling capacitor from the
IPDC pin to ground (recom-
mended value 10 pF).
The buffered input is then mixed
with the LO2, and the output of
the mixer (IF1) drives an off-chip
bandpass filter centered at the IF2
frequency (6.9 MHz for a 110.592
MHz 1IF). The filtered signal is
then fed to the IFIP1 pin, which is
the input to the limiting amplifier
chain. The limiting amplifier
requires two external decoupling
capacitors from pins DC1A and
DC1B to ground (recommended
value 10 nF).
7-112
The limiting amplifier chain also
feeds the Received Signal Strength
Indicator (RSSI) block. The RSSI
signal is monotonic over a 75 dB
dynamic range, and in its linear
range varies at 17 mV/dB. The
RSSI signal is designed to be
digitized by the CMOS burst mode
controller.
The output of the limiting ampli-
fier (IFOP1) drives the discrimina-
tor circuit. This signal is fed
directly to one of the input ports
of a Gilbert cell mixer, and it also
drives an external quadrature
network (with a recommended Q
of 8 for optimum performance).
The output of the external quadra-
ture network is then fed into the
other input port of the Gilbert cell
(via the DMOD pin). The output
of the Gilbert cell is taken at the
DMODOP pin, which drives an
external lowpass filter. To aid in
the construction of the filter, a
buffer stage is included on-chip.
The BUF1 pin is the noninverting
input of the buffer, and BUF2 is
the output, which is also con-
nected to the input of the data
slicer.
The data slicer operates on a dual
time constant architecture,
controlled via the TCSET pin.
During the preamble portion of a
DECT timeslot (with TCSET set to
1), the data slicer quickly acquires
the midpoint voltage of the
incoming data stream, correcting
any DC offsets that may have
occurred due to frequency devia-
tions within the DECT specifica-
tion. The value of this initial time
constant is determined by an
external capacitor connected
between TCNT and ground. A
10␣nF capacitor allows the accu-
rate acquisition of the midpoint
voltage within half of the 16-bit
DECT preamble.
元器件交易网
Once the midpoint voltage has
been acquired, TCSET is then
forced to a 0, and the time con-
stant of the midpoint voltage
tracking circuit is increased by a
factor of 80. This effectively
freezes the midpoint voltage from
any variations due to normal data
transitions, but still allows for
some correction of frequency
drifts during the data burst.
The output of the data slicer
(DATOP) is a CMOS-compatible
bitstream. However, it is recom-
mended that an external NPN
amplifier stage be used to drive
the CMOS baseband processor, in
order to minimize the amount of
ground and supply currents in the
HPMX-5002 which might desensi-
tize the chip.
D: 1897.344 MHz
B: 1881.792 MHz
CERAMIC
TX PA
TX FILTER
0: 893.376 MHz Rx
896.832 MHz Tx
9: 885.600 MHz Rx
889.056 MHz Tx
10.368 MHz
X2
Tank
φ
÷N
Freq.
÷12
Det.
T/R
FRONT-END
RF FILTER
RX LNA
CERAMIC
IMAGE
FILTER
HPMX-5001
REFERENCE
OSCILLATOR
32/33
IF2 = 6.912 MHz
IF1 = 110.592 MHz
LC Filter
SAW Channel Filter
LC filter
NetworkFilter
SYNTHESIZER
N=1034-1025 INCL. /32,33 Rx
N=1038-1029 INCL. /32,33 Tx
PFD FREQ. = 864 kHz
Data
Slicer
φ
Freq.
Det.
RSSI
÷9
Lock
Det.
HPMX-5002
RX DATA
÷9
Charge
Pump
PFD FREQ. = 1.152 MHz
Tank
LO2 = 103.68 MHz
RC filter
TX Data
Gaussian LPF
All other connections go to Burst Mode Controller, power source, or ground.
Figure 3. Typical HPMX-5002 Application with HPMX-5001 T/R Chip.
7-113
元器件交易网
Circuit in the IC
Vcc
IFOP1
Pin 1
DMOD
Pin 2
Vcc
DMODOP
Pin 3
Vcc
BUF1
Pin 4
Vcc
BUF2
Pin 5
Figure 4. HPMX-5002 Internal and Equivalent Circuits, Pins 1-5.
7-114
Small Signal Equivalent Circuit
(typical values)
330 Ω
IFOP1
V
9 kΩ
DMOD
330 Ω
DMODOP
V
>50 kΩ
BUF1
650 Ω
BUF2
V
元器件交易网
Circuit in the IC
Vcc
Small Signal Equivalent Circuit
(typical values)
DATAOP
Pin 8
Vcc
Vcc
RSSI
Pin 9
30 kΩ
RSSI
Vcc
RSSI
Pin 11
Vcc
VCOA
VCOB
V
Pins 24, 25
Vcc
65 Ω
OSCOP
OSCOPB
OSCOP
OSCOPS
Pins 27, 28
V
Figure 5. HPMX-5002 Internal and Equivalent Circuits, Pins 8, 9, 11, 24, 25, 27, and 28.
7-115
元器件交易网
Circuit in the ICSmall Signal Equivalent Circuit
Vcc
Pin 32
IP1
Vcc
IF1
Pin 35
Vcc
V
Pin 37
IFIP1
Figure 6. HPMX-5002 Internal and Equivalent Circuits, Pins 32, 35, and 37.
7-116
(typical values)
IP1
100 Ω
IFIP1
600 Ω
元器件交易网
Package Dimensions 48 Pin Thin Quad Flat Package
All dimensions shown in mm.
9.0±0.25
7.0±0.1
9.0±0.25
7.0±0.1
0.22 typ.0.5
1.4±0.05
0.05 min., 0.1 max.
0.6+0.15, -0.10
Part Number Ordering Information
Part Number
HPMX-5002-STR
HPMX-5002-TR1
HPMX-5002-TY1
No. of Devices
10
1000
250
Container
Strip
Tape and Reel
Tray
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元器件交易网
Tape Dimensions and Product Orientation for Outline TQFP-48
REEL
CARRIER
TAPE
USER
FEED
DIRECTION
COVER TAPE
2.0 (See Note 7)
0.30 ± 0.05
4.0 (See Note 2)
1.5+0.1/-0.0 DIA
1.75
R 0.5 (2)
1.6 (2)
5.0
B
O
7.5 (See Note 7)
16.0 ± 0.3
HPMX–50029433
6435
019
K
1
K
O
1.5 Min.
6.4 (2)
A
O
12.0
Cover tape width = 13.3 ± 0.1 mm
Cover tape thickness = 0.051 mm (0.002 inch)
NOTES:
1. Dimensions are in millimeters
2. 10 sprocket hole pitch cumulative tolerance ±0.2
3. Chamber not to exceed 1 mm in 100 mm
4. Material: black conductive Advantek™ polystyrene
5. A
O
and B
O
measured on a plane 0.3 mm above the bottom of the pocket.
6. K
O
measured from a plane on the inside bottom of the pocket to the top surface of the carrier.
7. Pocket position relative to sprocket hole measured as true position of pocket, not pocket hole.
A
O
= 9.3 mm
B
O
= 9.3 mm
K
O
= 2.2 mm
K
1
= 1.6 mm
7-118