2024年6月13日发(作者：阮策)
Related Documentation
•Virtex-5 Family Overview or the Virtex-5Q Family Overview
♦
The features and product selection of the Virtex-5 family are outlined in this
overview.
•Virtex-5 FPGA User Guide
This guide includes chapters on:
♦
♦
♦
♦
♦
♦
♦
♦
Clocking Resources
Clock Management Technology (CMT)
Phase-Locked Loops (PLLs)
Block RAM
Configurable Logic Blocks (CLBs)
SelectIO™ Resources
SelectIO Logic Resources
Advanced SelectIO Logic Resources
•Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
This data sheet contains the DC and Switching Characteristic specifications for the
Virtex-5 family.
•Virtex-5 FPGA RocketIO GTP Transceiver User Guide
This guide describes the RocketIO™ GTP transceivers available in the Virtex-5 LXT
and SXT platforms.
•Virtex-5 FPGA RocketIO GTX Transceiver User Guide
This guide describes the RocketIO GTX transceivers available in the Virtex-5 TXT and
FXT platforms.
•Virtex-5 FPGA Embedded Processor Block for Virtex-5 FPGAs
This reference guide is a description of the embedded processor block available in the
Virtex-5 FXT platform.
•Virtex-5 FPGA Embedded Tri-Mode Ethernet MAC User Guide
This guide describes the dedicated Tri-Mode Ethernet Media Access Controller
available in the Virtex-5 LXT, SXT, TXT and FXT platforms.
•Virtex-5 FPGA Integrated Endpoint Block User Guide for PCI Express Designs
This guide describes the integrated Endpoint blocks in the Virtex-5 LXT, SXT, TXT and
FXT platforms used for PCI Express® designs.
•Virtex-5 FPGA XtremeDSP Design Considerations
This guide describes the XtremeDSP™ slice and includes reference designs for using
the DSP48E slice.
Virtex-5 FPGA Packaging and Pinout Specification
FF1136 Package—LX50T, FX70T, LX85T, LX110T, LX155T, SX50T, SX95T, and FX100T
Table 2-5:FF1136 Package—LX50T, FX70T, LX85T, LX110T, LX155T, SX50T, SX95T
and FX100T (Continued)
Bank
6
6
6
6
6
6
6
6
6
6
6
6
6
Pin DescriptionPin Number
AK14
AK23
AK22
AL15
AL14
AJ21
AJ20
AJ16
AJ15
AK16
AL16
AL21
AK21
No Connect (NC)
LX50T, LX85T, SX50T
LX50T, LX85T, SX50T
LX50T, LX85T, SX50T
LX50T, LX85T, SX50T
LX50T, LX85T, SX50T
LX50T, LX85T, SX50T
LX50T, LX85T, SX50T
LX50T, LX85T, SX50T
LX50T, LX85T, SX50T
LX50T, LX85T, SX50T
LX50T, LX85T, SX50T
LX50T, LX85T, SX50T
LX50T, LX85T, SX50T
IO_L5N_6
IO_L6P_6
IO_L6N_6
IO_L7P_6
IO_L7N_6
IO_L8P_CC_6
IO_L8N_CC_6
(2)
IO_L9P_CC_6
IO_L9N_CC_6
(2)
IO_L10P_CC_6
IO_L10N_CC_6
(2)
IO_L11P_CC_6
IO_L11N_CC_6
(2)
Virtex-5 FPGA Packaging and Pinout Specification
2024年6月13日发(作者：阮策)
Related Documentation
•Virtex-5 Family Overview or the Virtex-5Q Family Overview
♦
The features and product selection of the Virtex-5 family are outlined in this
overview.
•Virtex-5 FPGA User Guide
This guide includes chapters on:
♦
♦
♦
♦
♦
♦
♦
♦
Clocking Resources
Clock Management Technology (CMT)
Phase-Locked Loops (PLLs)
Block RAM
Configurable Logic Blocks (CLBs)
SelectIO™ Resources
SelectIO Logic Resources
Advanced SelectIO Logic Resources
•Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
This data sheet contains the DC and Switching Characteristic specifications for the
Virtex-5 family.
•Virtex-5 FPGA RocketIO GTP Transceiver User Guide
This guide describes the RocketIO™ GTP transceivers available in the Virtex-5 LXT
and SXT platforms.
•Virtex-5 FPGA RocketIO GTX Transceiver User Guide
This guide describes the RocketIO GTX transceivers available in the Virtex-5 TXT and
FXT platforms.
•Virtex-5 FPGA Embedded Processor Block for Virtex-5 FPGAs
This reference guide is a description of the embedded processor block available in the
Virtex-5 FXT platform.
•Virtex-5 FPGA Embedded Tri-Mode Ethernet MAC User Guide
This guide describes the dedicated Tri-Mode Ethernet Media Access Controller
available in the Virtex-5 LXT, SXT, TXT and FXT platforms.
•Virtex-5 FPGA Integrated Endpoint Block User Guide for PCI Express Designs
This guide describes the integrated Endpoint blocks in the Virtex-5 LXT, SXT, TXT and
FXT platforms used for PCI Express® designs.
•Virtex-5 FPGA XtremeDSP Design Considerations
This guide describes the XtremeDSP™ slice and includes reference designs for using
the DSP48E slice.
Virtex-5 FPGA Packaging and Pinout Specification
FF1136 Package—LX50T, FX70T, LX85T, LX110T, LX155T, SX50T, SX95T, and FX100T
Table 2-5:FF1136 Package—LX50T, FX70T, LX85T, LX110T, LX155T, SX50T, SX95T
and FX100T (Continued)
Bank
6
6
6
6
6
6
6
6
6
6
6
6
6
Pin DescriptionPin Number
AK14
AK23
AK22
AL15
AL14
AJ21
AJ20
AJ16
AJ15
AK16
AL16
AL21
AK21
No Connect (NC)
LX50T, LX85T, SX50T
LX50T, LX85T, SX50T
LX50T, LX85T, SX50T
LX50T, LX85T, SX50T
LX50T, LX85T, SX50T
LX50T, LX85T, SX50T
LX50T, LX85T, SX50T
LX50T, LX85T, SX50T
LX50T, LX85T, SX50T
LX50T, LX85T, SX50T
LX50T, LX85T, SX50T
LX50T, LX85T, SX50T
LX50T, LX85T, SX50T
IO_L5N_6
IO_L6P_6
IO_L6N_6
IO_L7P_6
IO_L7N_6
IO_L8P_CC_6
IO_L8N_CC_6
(2)
IO_L9P_CC_6
IO_L9N_CC_6
(2)
IO_L10P_CC_6
IO_L10N_CC_6
(2)
IO_L11P_CC_6
IO_L11N_CC_6
(2)
Virtex-5 FPGA Packaging and Pinout Specification