2024年7月16日发(作者：旗意)
Package Thermal Characterization Methods and Conditions
The new JEDEC standard JESD51-14 specifies the TDI measurement method of the
junction-to-case thermal resistance without a case temperature measurement. The thermal
impedance or Zth-function Zθ
JC
(t) of a semiconductor device that is heated with constant
power (P
H
) starting at time t = 0 while its case surface is connected to a heatsink is defined
as:
Zθ
JC
(t) = (T
J
(t) – T
J
(t = 0))/P
H
Thus, the thermal impedance equals the time-dependent change of the junction
temperature T
J
(t) divided by the heating power. If the cooling condition at the package
case is changed, this should have no influence on the thermal impedance until the
temperature starts to increase at the package case where the contact to the heatsink is
located. However, a measurement with a different contact resistance changes the total
thermal resistance at steady state and therefore separates the impedance curves of different
measurements starting from the point where the external contact resistance begins, which
can be identified as the package case interface.
Two thermal impedance measurements are made with different contact resistances for
cooling the package case surface connected to the heatsink to identify this surface in
transient measurements. The cumulative thermal resistance at the separation point of these
two measurements is defined as Rθ
JC
(θ
JC
).
Junction-to-Ambient Measurement — θ
JA
X-Ref Target - Figure 3-10
UG112_C3_04_111208
Figure 3-10:θ
JA
Measurement Setup
SEMI method: Some of the data reported are based on the SEMI standard methods and
associated board standards. θ
JA
data reported as based on SEMI were measured on
FR4-based PC boards measuring 4.5 inx6.0 inx.0625 in (114.3mmx152.4mmx1.6mm)
with edge connectors. Several versions are available to handle various surface mount
(SMT) devices. They are, however, grouped into two main types. Type I board (the
equivalent of the JEDEC low-conductivity board) is single layer with two signal planes
(one on each surface) and no internal Power/GND planes. This is the 2L/0P or 2S/0P
board and the trace density on this board is less than 10% per side. The type II board (the
equivalent of the JEDEC 2S/2P board) has two internal copper planes — one power and
one ground. These planes are in addition to the two signal trace layers on both surfaces.
This is the 4L/2P (four-layer, also referred to as 2S/2P) board.
JEDEC measurements: Packages are measured in a one foot-cube enclosure based on
JEDS51-2. Test boards are fashioned per test board specification JESD51-3 and JESD51-7.
Device Package User Guide
UG112 (v3.7) September 5, 2012
2024年7月16日发(作者：旗意)
Package Thermal Characterization Methods and Conditions
The new JEDEC standard JESD51-14 specifies the TDI measurement method of the
junction-to-case thermal resistance without a case temperature measurement. The thermal
impedance or Zth-function Zθ
JC
(t) of a semiconductor device that is heated with constant
power (P
H
) starting at time t = 0 while its case surface is connected to a heatsink is defined
as:
Zθ
JC
(t) = (T
J
(t) – T
J
(t = 0))/P
H
Thus, the thermal impedance equals the time-dependent change of the junction
temperature T
J
(t) divided by the heating power. If the cooling condition at the package
case is changed, this should have no influence on the thermal impedance until the
temperature starts to increase at the package case where the contact to the heatsink is
located. However, a measurement with a different contact resistance changes the total
thermal resistance at steady state and therefore separates the impedance curves of different
measurements starting from the point where the external contact resistance begins, which
can be identified as the package case interface.
Two thermal impedance measurements are made with different contact resistances for
cooling the package case surface connected to the heatsink to identify this surface in
transient measurements. The cumulative thermal resistance at the separation point of these
two measurements is defined as Rθ
JC
(θ
JC
).
Junction-to-Ambient Measurement — θ
JA
X-Ref Target - Figure 3-10
UG112_C3_04_111208
Figure 3-10:θ
JA
Measurement Setup
SEMI method: Some of the data reported are based on the SEMI standard methods and
associated board standards. θ
JA
data reported as based on SEMI were measured on
FR4-based PC boards measuring 4.5 inx6.0 inx.0625 in (114.3mmx152.4mmx1.6mm)
with edge connectors. Several versions are available to handle various surface mount
(SMT) devices. They are, however, grouped into two main types. Type I board (the
equivalent of the JEDEC low-conductivity board) is single layer with two signal planes
(one on each surface) and no internal Power/GND planes. This is the 2L/0P or 2S/0P
board and the trace density on this board is less than 10% per side. The type II board (the
equivalent of the JEDEC 2S/2P board) has two internal copper planes — one power and
one ground. These planes are in addition to the two signal trace layers on both surfaces.
This is the 4L/2P (four-layer, also referred to as 2S/2P) board.
JEDEC measurements: Packages are measured in a one foot-cube enclosure based on
JEDS51-2. Test boards are fashioned per test board specification JESD51-3 and JESD51-7.
Device Package User Guide
UG112 (v3.7) September 5, 2012