2024年7月23日发(作者：汗闳)

7Series FPGAs Data Sheet: Overview

Digital Signal Processing — DSP Slice

Some highlights of the DSP functionality include:

•

•

•

25×18 two's complement multiplier/accumulator high-resolution (48bit) signal processor

Power saving pre-adder to optimize symmetrical filter applications

Advanced features: optional pipelining, optional ALU, and dedicated buses for cascading

DSP applications use many binary multipliers and accumulators, best implemented in dedicated DSP slices. All 7series

FPGAs have many dedicated, full custom, low-power DSP slices, combining high speed with small size while retaining

system design flexibility.

Each DSP slice fundamentally consists of a dedicated 25×18 bit two's complement multiplier and a 48-bit accumulator,

both capable of operating up to 741MHz. The multiplier can be dynamically bypassed, and two 48-bit inputs can feed a

single-instruction-multiple-data (SIMD) arithmetic unit (dual 24-bit add/subtract/accumulate or quad 12-bit

add/subtract/accumulate), or a logic unit that can generate any one of ten different logic functions of the two operands.

The DSP includes an additional pre-adder, typically used in symmetrical filters. This pre-adder improves performance in

densely packed designs and reduces the DSP slice count by up to 50%. The DSP also includes a 48-bit-wide Pattern

Detector that can be used for convergent or symmetric rounding. The pattern detector is also capable of implementing

96-bit-wide logic functions when used in conjunction with the logic unit.

The DSP slice provides extensive pipelining and extension capabilities that enhance the speed and efficiency of many

applications beyond digital signal processing, such as wide dynamic bus shifters, memory address generators, wide bus

multiplexers, and memory-mapped I/O register files. The accumulator can also be used as a synchronous up/down counter.

Input/Output

Some highlights of the input/output functionality include:

•

•

•

High-performance SelectIO technology with support for 1,866Mb/s DDR3

High-frequency decoupling capacitors within the package for enhanced signal integrity

Digitally Controlled Impedance that can be 3-stated for lowest power, high-speed I/O operation

The number of I/O pins varies depending on device and package size. Each I/O is configurable and can comply with a large

number of I/O standards. With the exception of the supply pins and a few dedicated configuration pins, all other package pins

have the same I/O capabilities, constrained only by certain banking rules. The I/O in 7series FPGAs are classed as high

range (HR) or high performance (HP). The HR I/Os offer the widest range of voltage support, from 1.2V to 3.3V. The HP I/Os

are optimized for highest performance operation, from 1.2V to 1.8V.

HR and HP I/O pins in 7 series FPGAs are organized in banks, with 50 pins per bank. Each bank has one common V

CCO

output supply, which also powers certain input buffers. Some single-ended input buffers require an internally generated or an

externally applied reference voltage (V

REF

). There are two V

REF

pins per bank (except configuration bank 0). A single bank

can have only one V

REF

voltage value.

Xilinx 7series FPGAs use a variety of package types to suit the needs of the user, including small form factor wire-bond

packages for lowest cost; conventional, high performance flip-chip packages; and bare-die

flip-chip packages that balance

smaller form factor with high performance. In the flip-chip packages, the silicon device is attached to the package substrate

using a high-performance flip-chip process. Controlled ESR discrete decoupling capacitors are mounted on the package

substrate to optimize signal integrity under simultaneous switching of outputs (SSO) conditions.

DS180 (v2.6.1) September 8, 2020

Product Specification

2024年7月23日发(作者：汗闳)

7Series FPGAs Data Sheet: Overview

Digital Signal Processing — DSP Slice

Some highlights of the DSP functionality include:

•

•

•

25×18 two's complement multiplier/accumulator high-resolution (48bit) signal processor

Power saving pre-adder to optimize symmetrical filter applications

Advanced features: optional pipelining, optional ALU, and dedicated buses for cascading

DSP applications use many binary multipliers and accumulators, best implemented in dedicated DSP slices. All 7series

FPGAs have many dedicated, full custom, low-power DSP slices, combining high speed with small size while retaining

system design flexibility.

Each DSP slice fundamentally consists of a dedicated 25×18 bit two's complement multiplier and a 48-bit accumulator,

both capable of operating up to 741MHz. The multiplier can be dynamically bypassed, and two 48-bit inputs can feed a

single-instruction-multiple-data (SIMD) arithmetic unit (dual 24-bit add/subtract/accumulate or quad 12-bit

add/subtract/accumulate), or a logic unit that can generate any one of ten different logic functions of the two operands.

The DSP includes an additional pre-adder, typically used in symmetrical filters. This pre-adder improves performance in

densely packed designs and reduces the DSP slice count by up to 50%. The DSP also includes a 48-bit-wide Pattern

Detector that can be used for convergent or symmetric rounding. The pattern detector is also capable of implementing

96-bit-wide logic functions when used in conjunction with the logic unit.

The DSP slice provides extensive pipelining and extension capabilities that enhance the speed and efficiency of many

applications beyond digital signal processing, such as wide dynamic bus shifters, memory address generators, wide bus

multiplexers, and memory-mapped I/O register files. The accumulator can also be used as a synchronous up/down counter.

Input/Output

Some highlights of the input/output functionality include:

•

•

•

High-performance SelectIO technology with support for 1,866Mb/s DDR3

High-frequency decoupling capacitors within the package for enhanced signal integrity

Digitally Controlled Impedance that can be 3-stated for lowest power, high-speed I/O operation

The number of I/O pins varies depending on device and package size. Each I/O is configurable and can comply with a large

number of I/O standards. With the exception of the supply pins and a few dedicated configuration pins, all other package pins

have the same I/O capabilities, constrained only by certain banking rules. The I/O in 7series FPGAs are classed as high

range (HR) or high performance (HP). The HR I/Os offer the widest range of voltage support, from 1.2V to 3.3V. The HP I/Os

are optimized for highest performance operation, from 1.2V to 1.8V.

HR and HP I/O pins in 7 series FPGAs are organized in banks, with 50 pins per bank. Each bank has one common V

CCO

output supply, which also powers certain input buffers. Some single-ended input buffers require an internally generated or an

externally applied reference voltage (V

REF

). There are two V

REF

pins per bank (except configuration bank 0). A single bank

can have only one V

REF

voltage value.

Xilinx 7series FPGAs use a variety of package types to suit the needs of the user, including small form factor wire-bond

packages for lowest cost; conventional, high performance flip-chip packages; and bare-die

flip-chip packages that balance

smaller form factor with high performance. In the flip-chip packages, the silicon device is attached to the package substrate

using a high-performance flip-chip process. Controlled ESR discrete decoupling capacitors are mounted on the package

substrate to optimize signal integrity under simultaneous switching of outputs (SSO) conditions.

DS180 (v2.6.1) September 8, 2020

Product Specification