2024年9月12日发(作者：海娴)

ISL9000AM

NOT RECOMMENDED FOR

NEW DESIGNS

NO RECOMMENDED REPLAC

EMENT

contact our Technical Suppor

t Center at

1-888-INTERSIL or w

/tsc

DATASHEET

FN6620

Rev 1.00

November 11, 2011

Dual LDO with Low Noise, Very High PSRR and Low I

Q

ISL9000AMRNCP is a high performance dual LDO capable

of sourcing 100mA current from each output. It has a low

standby current and very high PSRR and is stable with

output capacitance of 1µF to 10µF with ESR of up to 200m.

The device integrates an individual Power-On-Reset (POR)

function for each output. The POR delay for VO2 can be

externally programmed by connecting a timing capacitor to

the CPOR pin. The POR delay for VO1 is internally fixed at

approximately 2ms. A reference bypass pin is also provided

for connecting a noise filtering capacitor for low noise and

high-PSRR applications.

The quiescent current is typically only 42µA with both LDO’s

enabled and active. Separate enable pins control each

individual LDO output. When both enable pins are low, the

device is in shutdown, typically drawing less than 0.1µA.

Output voltage for the LDO are VOUT1 = 3.3V and

VOUT2=1.8V.

Features

•Integrates Two 100mA High Performance LDO’s

•I

OUT

per Channel is 50mA at T

J

= +150°C

•Excellent Transient Response to Large Current Steps

•±1.8% Accuracy Over all Operating Conditions

•Excellent Load Regulation:

< 0.1% Voltage Change Across Full Range of Load

Current

•Low Output Noise: Typically 30µV

rms

@ 100µA (1.5V)

•Very High PSRR: 90dB @ 1kHz

•Extremely Low Quiescent Current: 42µA (both LDOs

active)

•Wide Input Voltage Capability: 2.3V to 5.5V

•Low Dropout Voltage: Typically 200mV @ 100mA

•Stable with 1µF to 10µF Ceramic Capacitors

•Separate Enable and POR Pins for Each LDO

•Soft-Start and Staged Turn-On to Limit Input Current

Surge During Enable

•Current Limit and Overheat Protection

•Tiny 10 Ld 3x3mm DFN Package

•-55°C to +125°C Operating Temperature Range

Device Information

The specifications for an Enhanced Product (EP) device are

defined in a Vendor Item Drawing (VID), which is controlled

by the Defense Logistics Agency (DLA). “Hot-links” to the

applicable VID and other supporting application information

are provided on our website.

Pinout

ISL9000AMNCEP

(10 LD 3X3 DFN)

TOP VIEW

VIN

1

EN1

2

EN2

3

CBYP

4

CPOR

5

10

VO1

9

8

7

6

VO2

POR2

POR1

GND

Applications

•PDAs, Cell Phones and Smart Phones

•Portable Instruments, MP3 Players

•Handheld Devices including Medical Handheld

Ordering Information

VENDOR PART

NUMBER

(Notes 1, 2)

ISL9000AMRNCEP

NOTES:

-T to part number for tape and reel.

s must be procured to the VENDOR PART NUMBER.

VENDOR ITEM

DRAWING

V62/08609-01XB

PART

MARKING

DKTA

VO2

VO1

VOLTAGE

VOLTAGETEMP RANGE

(V)(°C)

(V)

3.31.8-55 to +125

PACKAGE

10 Ld 3x3 DFN

PKG

DWG. #

L10.3x3C

FN6620Rev 1.00

November 11, 2011

Page 1 of 2

ISL9000AM

Dual Flat No-Lead Plastic Package (DFN)

2X

0.10CA

A

D

2X

0.10CB

L10.3x3C

10 LEAD DUAL FLAT NO-LEAD PLASTIC PACKAGE

MILLIMETERS

SYMBOL

A

A1

MIN

0.85

-

NOMINAL

0.90

-

0.20 REF

0.200.25

3.00 BSC

2.332.38

3.00 BSC

1.591.64

0.50 BSC

0.20

0.35

-

0.40

10

5

-

0.45

1.69

2.43

0.30

MAX

0.95

0.05

NOTES

-

-

-

5, 8

-

7, 8

-

7, 8

-

-

8

2

3

Rev. 14/06

NOTES:

ioning and tolerancing conform to ASME Y14.5-1994.

2.N is the number of terminals.

refers to the number of terminals on D.

dimensions are in millimeters. Angles are in degrees.

ion b applies to the metallized terminal and is measured

between 0.15mm and 0.30mm from the terminal tip.

configuration of the pin #1 identifier is optional, but must be

located within the zone indicated. The pin #1 identifier may be

either a mold or mark feature.

E

6

INDEX

AREA

TOP VIEW

B

A3

b

D

D2

E

//0.10C

0.08C

E2

e

A

C

SEATING

PLANE

SIDE VIEW

A3

k

L

N

D2

(DATUM B)

6

12

D2/2

78

Nd

INDEX

AREA

(DATUM A)

NX k

E2

E2/2

NX L

N

8

N-1

NX b

5

0.10

M

CAB

e

(Nd-1)Xe

REF.

BOTTOM VIEW

C

L

ions D2 and E2 are for the exposed pads which provide

improved electrical and thermal performance.

l dimensions are provided to assist with PCB Land

Pattern Design efforts, see Intersil Technical Brief TB389.

ANT TO JEDEC MO-229-WEED-3 except for

dimensions E2 & D2.

NX (b)

5

(A1)

9

L

SECTION "C-C"

CC

e

TERMINAL TIP

FOR ODD TERMINAL/SIDE

© Copyright Intersil Americas LLC 2007-2011. All Rights Reserved.

All trademarks and registered trademarks are the property of their respective owners.

For additional products, see /en/

Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted

in the quality certifications found at /en/support/

Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such

modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are

current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its

subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or

otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see

FN6620Rev 1.00

November 11, 2011

Page 2 of 2

2024年9月12日发(作者：海娴)

ISL9000AM

NOT RECOMMENDED FOR

NEW DESIGNS

NO RECOMMENDED REPLAC

EMENT

contact our Technical Suppor

t Center at

1-888-INTERSIL or w

/tsc

DATASHEET

FN6620

Rev 1.00

November 11, 2011

Dual LDO with Low Noise, Very High PSRR and Low I

Q

ISL9000AMRNCP is a high performance dual LDO capable

of sourcing 100mA current from each output. It has a low

standby current and very high PSRR and is stable with

output capacitance of 1µF to 10µF with ESR of up to 200m.

The device integrates an individual Power-On-Reset (POR)

function for each output. The POR delay for VO2 can be

externally programmed by connecting a timing capacitor to

the CPOR pin. The POR delay for VO1 is internally fixed at

approximately 2ms. A reference bypass pin is also provided

for connecting a noise filtering capacitor for low noise and

high-PSRR applications.

The quiescent current is typically only 42µA with both LDO’s

enabled and active. Separate enable pins control each

individual LDO output. When both enable pins are low, the

device is in shutdown, typically drawing less than 0.1µA.

Output voltage for the LDO are VOUT1 = 3.3V and

VOUT2=1.8V.

Features

•Integrates Two 100mA High Performance LDO’s

•I

OUT

per Channel is 50mA at T

J

= +150°C

•Excellent Transient Response to Large Current Steps

•±1.8% Accuracy Over all Operating Conditions

•Excellent Load Regulation:

< 0.1% Voltage Change Across Full Range of Load

Current

•Low Output Noise: Typically 30µV

rms

@ 100µA (1.5V)

•Very High PSRR: 90dB @ 1kHz

•Extremely Low Quiescent Current: 42µA (both LDOs

active)

•Wide Input Voltage Capability: 2.3V to 5.5V

•Low Dropout Voltage: Typically 200mV @ 100mA

•Stable with 1µF to 10µF Ceramic Capacitors

•Separate Enable and POR Pins for Each LDO

•Soft-Start and Staged Turn-On to Limit Input Current

Surge During Enable

•Current Limit and Overheat Protection

•Tiny 10 Ld 3x3mm DFN Package

•-55°C to +125°C Operating Temperature Range

Device Information

The specifications for an Enhanced Product (EP) device are

defined in a Vendor Item Drawing (VID), which is controlled

by the Defense Logistics Agency (DLA). “Hot-links” to the

applicable VID and other supporting application information

are provided on our website.

Pinout

ISL9000AMNCEP

(10 LD 3X3 DFN)

TOP VIEW

VIN

1

EN1

2

EN2

3

CBYP

4

CPOR

5

10

VO1

9

8

7

6

VO2

POR2

POR1

GND

Applications

•PDAs, Cell Phones and Smart Phones

•Portable Instruments, MP3 Players

•Handheld Devices including Medical Handheld

Ordering Information

VENDOR PART

NUMBER

(Notes 1, 2)

ISL9000AMRNCEP

NOTES:

-T to part number for tape and reel.

s must be procured to the VENDOR PART NUMBER.

VENDOR ITEM

DRAWING

V62/08609-01XB

PART

MARKING

DKTA

VO2

VO1

VOLTAGE

VOLTAGETEMP RANGE

(V)(°C)

(V)

3.31.8-55 to +125

PACKAGE

10 Ld 3x3 DFN

PKG

DWG. #

L10.3x3C

FN6620Rev 1.00

November 11, 2011

Page 1 of 2

ISL9000AM

Dual Flat No-Lead Plastic Package (DFN)

2X

0.10CA

A

D

2X

0.10CB

L10.3x3C

10 LEAD DUAL FLAT NO-LEAD PLASTIC PACKAGE

MILLIMETERS

SYMBOL

A

A1

MIN

0.85

-

NOMINAL

0.90

-

0.20 REF

0.200.25

3.00 BSC

2.332.38

3.00 BSC

1.591.64

0.50 BSC

0.20

0.35

-

0.40

10

5

-

0.45

1.69

2.43

0.30

MAX

0.95

0.05

NOTES

-

-

-

5, 8

-

7, 8

-

7, 8

-

-

8

2

3

Rev. 14/06

NOTES:

ioning and tolerancing conform to ASME Y14.5-1994.

2.N is the number of terminals.

refers to the number of terminals on D.

dimensions are in millimeters. Angles are in degrees.

ion b applies to the metallized terminal and is measured

between 0.15mm and 0.30mm from the terminal tip.

configuration of the pin #1 identifier is optional, but must be

located within the zone indicated. The pin #1 identifier may be

either a mold or mark feature.

E

6

INDEX

AREA

TOP VIEW

B

A3

b

D

D2

E

//0.10C

0.08C

E2

e

A

C

SEATING

PLANE

SIDE VIEW

A3

k

L

N

D2

(DATUM B)

6

12

D2/2

78

Nd

INDEX

AREA

(DATUM A)

NX k

E2

E2/2

NX L

N

8

N-1

NX b

5

0.10

M

CAB

e

(Nd-1)Xe

REF.

BOTTOM VIEW

C

L

ions D2 and E2 are for the exposed pads which provide

improved electrical and thermal performance.

l dimensions are provided to assist with PCB Land

Pattern Design efforts, see Intersil Technical Brief TB389.

ANT TO JEDEC MO-229-WEED-3 except for

dimensions E2 & D2.

NX (b)

5

(A1)

9

L

SECTION "C-C"

CC

e

TERMINAL TIP

FOR ODD TERMINAL/SIDE

© Copyright Intersil Americas LLC 2007-2011. All Rights Reserved.

All trademarks and registered trademarks are the property of their respective owners.

For additional products, see /en/

Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted

in the quality certifications found at /en/support/

Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such

modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are

current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its

subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or

otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see

FN6620Rev 1.00

November 11, 2011

Page 2 of 2