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2024年3月17日发(作者：蓝幼丝)

A4950

Full-Bridge DMOS PWM Motor Driver

Features and Benefits

• Low R

DS(on)

outputs

• Overcurrent protection (OCP)

▫ Motor short protection

▫ Motor lead short to ground protection

▫ Motor lead short to battery protection

• Low Power Standby mode

• Adjustable PWM current limit

• Synchronous rectification

• Internal undervoltage lockout (UVLO)

• Crossover-current protection

• A4950K is AEC-Q100 Grade 1 qualified

• Commercial temperature grade (A4950E: –40°C to 85°C )

• Automotive temperature grade (A4950K: –40°C to 125°C)

Description

Designed for pulse width modulated (PWM) control of DC

motors, the A4950 is capable of peak output currents to ±3.5 A

and operating voltages to 40 V.

Input terminals are provided for use in controlling the speed and

direction of a DC motor with externally applied PWM control

signals. Internal synchronous rectification control circuitry is

provided to lower power dissipation during PWM operation.

Internal circuit protection includes overcurrent protection,

motor lead short to ground or supply, thermal shutdown with

hysteresis, undervoltage monitoring of V

, and crossover-

current protection.

For high ambient operating temperature applications, an

automotive grade device is offered (A4950K). The K grade

device is tested across extended temperature and voltage

ranges to ensure compliance in automotive or industrial

applications.

The A4950 is provided in a low-profile 8-pin SOICN package

with exposed thermal pad (suffix LJ) that is lead (Pb) free, with

100% matte tin leadframe plating.

Package: 8-pin SOICN with exposed

thermal pad (suffix LJ)

Not to scale

Functional Block Diagram

Load

Supply

OSC

Charge

Pump

VBB

IN1

Control

Logic

Disable

TSD

UVLO

OUT1

OUT2

IN2

GND

LSS

VREF

(Optional)

A4950-DS, Rev. 4

A4950

Selection Guide

Part Number

A4950ELJTR-T

A4950KLJTR-T

Full-Bridge DMOS PWM Motor Driver

Packing

3000 pieces per 13-in. reel

Ambient Operating Temperature, T

–40°C to 85°C

–40°C to 125°C

Absolute Maximum Ratings

Characteristic

Load Supply Voltage

Logic Input Voltage Range

REF

Input Voltage Range

Sense Voltage (LSS pin)

Motor Outputs Voltage

Output Current

Transient Output Current

Operating Temperature Range

Maximum Junction Temperature

Storage Temperature Range

Symbol

REF

OUT

(max)

stg

Duty cycle = 100%

< 500 ns

Temperature Range E

Temperature Range K

NotesRating

–0.3 to 6

–0.5 to 0.5

–2 to 42

3.5

–40 to 85

–40 to 125

150

–55 to 150

Unit

°C

Thermal Characteristics

may require derating at maximum conditions, see application information

Characteristic

Package Thermal Resistance

Symbol

θJA

Test Conditions*

On 2-layer PCB with 0.8 in

. exposed 2-oz. copper each side

On 4-layer PCB based on JEDEC standard

Value

Unit

ºC/W

*Additional thermal information available on the Allegro website.

Terminal List Table

NumberName

GND

IN2

IN1

VREF

VBB

OUT1

LSS

OUT2

PAD

Ground

Logic input 2

Logic input 1

Analog input

Load supply voltage

DMOS full bridge output 1

Power return – sense resistor connection

DMOS full bridge output 2

Exposed pad for enhanced thermal dissipation

Function

Pin-out Diagram

GND

IN2

IN1

VREF

PAD

OUT2

LSS

OUT1

VBB

–

Allegro MicroSystems, Inc.

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000;

A4950

Full-Bridge DMOS PWM Motor Driver

version at T

= –40°C to 150°C, V

= 8 to 40 V, unless otherwise specified

Characteristic

General

Load Supply Voltage Range

DS(on)

Sink + Source Total

Load Supply Current

Body Diode Forward Voltage

Logic Inputs

IN(1)

Logic Input Voltage RangeV

IN(0)

IN(STANDBY)

Low Power Standby mode

ELECTRICAL CHARACTERISTICS

Valid for Temperature Range E version at T

= 25°C and for Temperature Range K

Symbol

DS(on)

OUT

= |2.5 A|, T

= 25°C

OUT

= |2.5 A|, T

= 150°C

PWM

< 30 kHz

Low Power Standby mode

Source diode, I

= –2.5 A

Sink diode, I

= 2.5 A

Test ConditionsMin.

–

2.0

–

REF

/ I

, V

REF

= 5 V

Current Gain

Blank Time

Constant Off-time

Standby Timer

Power-Up Delay

Protection Circuits

UVLO Enable Threshold

UVLO Hysteresis

Thermal Shutdown Temperature

Thermal Shutdown Hysteresis

BBUVLO

BBUVLOhys

JTSD

TSDhys

Temperature increasing

Recovery = T

JTSD

– T

TSDhys

increasing7

–

7.5

500

160

7.95

–

°C

BLANK

off

IN1 = IN2 < V

IN(STANDBY)

REF

/ I

, V

REF

= 2.5 V

REF

/ I

, V

REF

= 1 V

9.5

9.0

8.0

–

= 2.0 V

= 0.8 V

Typ.

–

0.6

1.1

–

250

–

Max.

0.8

1.5

–

0.8

0.4

100

–

550

500

10.5

10.0

1.5

Unit

μA

kΩ

V/V

μs

Logic Input Current

Logic Input Pull-Down Resistance

Input Hysteresis

Timing

Crossover Delay

REF

Input Voltage Range

IN(1)

IN(0

)

HYS

COD

REF

LOGIC(PD)

= 0 V = IN1 = IN2

Allegro MicroSystems, Inc.

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000;

A4950

Full-Bridge DMOS PWM Motor Driver

Characteristic Performance

PWM Control Timing Diagram

IN(1)

IN1

GND

IN(1)

IN2

GND

REG

OUT(x)

0 A

-I

REG

Forward/

Fast Decay

Reverse/

Fast Decay

Forward/

Slow Decay

Reverse/

Slow Decay

PWM Control Truth Table

IN1

IN2

10×V

> V

REF

False

True

False

OUT1

H/L

OUT2

H/L

Reverse

Forward

Chop (mixed decay), reverse

Chop (mixed decay), forward

Brake (slow decay)

Coast, enters Low Power Standby mode after 1 ms

Function

Note: Z indicates high impedance.

Allegro MicroSystems, Inc.

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000;

A4950

Full-Bridge DMOS PWM Motor Driver

Functional Description

TripMAX

(A), which is set by:

Device Operation

The A4950 is designed to operate DC motors. The output drivers

are all low-R

DS(on)

, N-channel DMOS drivers that feature inter-

REF

TripMAX

nal synchronous rectification to reduce power dissipation. The

current in the output full bridge is regulated with fixed off-time

pulse width modulated (PWM) control circuitry. The IN1 and IN2

where V

REF

is the input voltage on the VREF pin (V) and R

the resistance of the sense resistor (Ω) on the LSS terminal.

inputs allow two-wire control for the bridge.

Protection circuitry includes internal thermal shutdown, and pro-

tection against shorted loads, or against output shorts to ground

or supply. Undervoltage lockout prevents damage by keeping the

outputs off until the driver has enough voltage to operate nor-

mally.

Standby Mode

Low Power Standby mode is activated when both input (INx)

pins are low for longer than 1 ms. Low Power Standby mode

disables most of the internal circuitry, including the charge pump

and the regulator. When the A4950 is coming out of standby

mode, the charge pump should be allowed to reach its regulated

voltage (a maximum delay of 200 μs) before any PWM com-

mands are issued to the device.

Internal PWM Current Control

Initially, a diagonal pair of source and sink FET outputs are

enabled and current flows through the motor winding and the

optional external current sense resistor, R

. When the voltage

across R

equals the comparator trip value, then the current sense

comparator resets the PWM latch. The latch then turns off the

sink and source FETs (Mixed Decay mode).

REF

The maximum value of current limiting is set by the selection of

and the voltage at the VREF pin. The transconductance func-

tion is approximated by the maximum value of current limiting,

Overcurrent Protection

A current monitor will protect the IC from damage due to output

shorts. If a short is detected, the IC will latch the fault and disable

the outputs. The fault latch can only be cleared by coming out of

Low Power Standby mode or by cycling the power to VBB. Dur-

ing OCP events, Absolute Maximum Ratings may be exceeded

for a short period of time before the device latches.

Shutdown

If the die temperature increases to approximately 160°C, the full

bridge outputs will be disabled until the internal temperature falls

below a hysteresis, T

TSDhys

, of 15°C. Internal UVLO is present

on VBB to prevent the output drivers from turning-on below the

UVLO threshold.

Braking

The braking function is implemented by driving the device in

Slow Decay mode, which is done by applying a logic high to both

inputs, after a bridge-enable Chop command (see PWM Control

Truth Table). Because it is possible to drive current in both direc-

tions through the DMOS switches, this configuration effectively

shorts-out the motor-generated BEMF, as long as the Chop com-

mand is asserted. The maximum current can be approximated by

BEMF

/ R

. Care should be taken to ensure that the maximum

ratings of the device are not exceeded in worse case braking situ-

ations: high speed and high-inertia loads.

Allegro MicroSystems, Inc.

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000;

A4950

Full-Bridge DMOS PWM Motor Driver

Mixed Decay Operation

The bridges operate in Mixed Decay mode. Referring to the

lower panel of the figure below, as the trip point is reached, the

device goes into fast decay mode for 50% of the fixed off-time

period. After this fast decay portion the device switches to slow

decay mode for the remainder of the off-time. During transitions

from fast decay to slow decay, the drivers are forced off for the

Crossover Delay, t

COD

. This feature is added to prevent shoot-

through in the bridge. During this “dead time” portion, synchro-

nous rectification is not active, and the device operates in fast

decay and slow decay only.

Synchronous Rectification

When a PWM off-cycle is triggered by an internal fixed off-time

cycle, load current will recirculate. The A4950 synchronous rec-

tification feature turns-on the appropriate DMOSFETs during the

current decay, and effectively shorts out the body diodes with the

low R

DS(on)

driver. This significantly lowers power dissipation.

When a zero current level is detected, synchronous rectification is

turned off to prevent reversal of the load current.

Mixed Decay Mode Operation

PHASE

OUT

See Enlargement A

–

Enlargement A

Fixed Off-Time, t

off

= 25 μs

0.50 × t

off

0.50 × t

off

Trip

OUT

Fast DecaySlow Decay

COD

Allegro MicroSystems, Inc.

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000;

A4950

Full-Bridge DMOS PWM Motor Driver

Application Information

Sense Pin (LSS)

In order to use PWM current control, a low-value resistor is

placed between the LSS pin and ground for current sensing pur-

poses. To minimize ground-trace IR drops in sensing the output

current level, the current sensing resistor should have an indepen-

dent ground return to the star ground point. This trace should be

as short as possible. For low-value sense resistors, the IR drops in

the PCB can be significant, and should be taken into account.

When selecting a value for the sense resistor be sure not to

exceed the maximum voltage on the LSS pin of ±500 mV at

maximum load. During overcurrent events, this rating may be

exceeded for short durations.

of the device makes a good location for the star ground point. The

exposed pad can be connected to ground for this purpose.

Layout

The PCB should have a thick ground plane. For optimum

electrical and thermal performance, the A4950 must be soldered

directly onto the board. On the underside of the A4950 package is

an exposed pad, which provides a path for enhanced thermal dis-

sipation. The thermal pad must be soldered directly to an exposed

surface on the PCB in order to achieve optimal thermal conduc-

tion. Thermal vias are used to transfer heat to other layers of the

PCB.

The load supply pin, VBB, should be decoupled with an electro-

Ground

A star ground should be located as close to the A4950 as possible.

lytic capacitor (typically 100 μF) in parallel with a lower valued

The copper ground plane directly under the exposed thermal pad ceramic capacitor placed as close as practicable to the device.

GND

A4950

Solder

Trace (2 oz.)

Signal (1 oz.)

Ground (1 oz.)

Thermal (2 oz.)

PCB

OUT2

Thermal Vias

OUT1

A4950

BULK

CAPACITANCE

GND

VBB

OUT2

IN2

IN1

VREF

PAD

LSS

OUT1

VBB

GND

Bill of Materials

Item

Reference

Value

0.25

(for V

REF

= 5 V, I

OUT

= 2 A)

0.22

100

Units

μF

Description

2512, 1 W, 1% or better,

carbon film chip resistor

X5R minimum, 50 V or greater

Electrolytic, 50 V or greater

Allegro MicroSystems, Inc.

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000;

A4950

Full-Bridge DMOS PWM Motor Driver

Package LJ, 8-Pin SOICN

with exposed thermal pad

4.90 ±0.10

8°

0°

0.25

0.17

0.65

1.75

1.27

2.41 NOM

3.90 ±0.10 6.00 ±0.20

1.04 REF

2.415.60

3.30 NOM

1.27

0.40

0.25 BSC

Branded Face

SEATING PLANE

GAUGE PLANE

3.30

PCB Layout Reference View

0.10C

0.51

0.31

1.27 BSC

SEATING

PLANE

1.70 MAX

0.15

0.00

For Reference Only; not for tooling use (reference MS-012BA)

Dimensions in millimeters

Dimensions exclusive of mold flash, gate burrs, and dambar protrusions

Exact case and lead configuration at supplier discretion within limits shown

Terminal #1 mark area

Exposed thermal pad (bottom surface); dimensions may vary with device

Reference land pattern layout (reference IPC7351

SOIC127P600X175-9AM); all pads a minimum of 0.20 mm from all

adjacent pads; adjust as necessary to meet application process

requirements and PCB layout tolerances; when mounting on a multilayer

PCB, thermal vias at the exposed thermal pad land can improve thermal

dissipation (reference EIA/JEDEC Standard JESD51-5)

Allegro MicroSystems, Inc.

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000;

A4950

Full-Bridge DMOS PWM Motor Driver

Revision History

Revision

Rev. 4

Revision Date

August 6, 2012

Description of Revision

Add AEC qualification; update PWM table

Allegro MicroSystems, Inc. reserves the right to make, from time to time, such de par tures from the detail spec i fi ca tions as may be required to per-

mit improvements in the per for mance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the

information being relied upon is current.

Allegro’s products are not to be used in life support devices or systems, if a failure of an Allegro product can reasonably be expected to cause the

failure of that life support device or system, or to affect the safety or effectiveness of that device or system.

The in for ma tion in clud ed herein is believed to be ac cu rate and reliable. How ev er, Allegro MicroSystems, Inc. assumes no re spon si bil ity for its use;

nor for any in fringe ment of patents or other rights of third parties which may result from its use.

For the latest version of this document, visit our website:

Allegro MicroSystems, Inc.

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000;

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