2024年3月22日发(作者：掌夜绿)
Pin Name
MGTHAVCC
MGTHAVCCRX
MGTHAVTT
MGTHAVCCPLL
Direction
Input
Input
Input
Input
Description
Analog supply for the receiver and transmitter internal circuits. In Virtex-6 HXT
devices containing GTH transceivers.
Analog supply for the PLL and the receiver equalizers. In Virtex-6 HXT devices
containing GTH transceivers.
Analog supply for the transmit driver. In Virtex-6 HXT devices containing GTH
transceivers.
Analog supply for the reference clock buffer and the PLL. In Virtex-6 HXT
devices containing GTH transceivers.
GND reference for the GTH transceiver internal circuitry. These pins should be
connected to the PCB power supply GND reference plane. In Virtex-6 HXT
devices containing GTH transceivers.
GTH Quad positive differential reference clock. In Virtex-6 HXT devices
containing GTH transceivers.
GTH Quad negative differential reference clock. In Virtex-6 HXT devices
containing GTH transceivers.
GTXE1 positive differential reference clock.
GTXE1 negative differential reference clock.
Precision reference resistor pin for internal calibration termination. Always
located in Bank 115.
(4)
Precision reference resistor pin for internal calibration termination. Always
located in Bank 115.
(4)
Internal precision current, voltage, and resistor references for the GTH Quad.
Connect this pin to a 1KΩ resistor with the other terminal of the resistor
connected to GND. In Virtex-6 HXT devices containing GTH transceivers.
Reserved. No Connection; leave floating. In Virtex-6 HXT devices containing
GTH transceivers.
MGTHAGNDInput
MGTREFCLKP
MGTREFCLKN
MGTREFCLK0/1P
MGTREFCLK0/1N
MGTAVTTRCAL
MGTRREF
Input
Input
Input
Input
N/A
Input
MGTRBIASInput
RSVD
Notes:
N/A
dedicated pins (JTAG and configuration) are powered by V
CC_CONFIG
(V
CC_0
).
2.V
CCO
pins in unbonded banks must be connected to the V
CCO
for that bank for package migration. Do NOT connect unbonded
V
CCO
pins to different supplies. Without a package migration requirement, V
CCO
pins in unbonded banks can be left unconnected
or tied to a common supply (V
CCO
or ground).
more information on connecting the System Monitor pins, see Virtex-6 FPGA System Monitor User Guide.
FF484 and FF784 contain MGTAVCC and MGTAVTT pins. All other packages contain MGTAVCC_N/_S pins. All the respective
MGTAV* supply pins are connected via planes in the package to the GTXs. The MGTAVCC and MGTAVTT supply all GTXs in a
device. The MGTAVCC_N and MGTAVTT_N supply all GTXs in the upper half (North) and MGTAVCC_S and MGTAVTT_S supply
all GTXs in the lower half (South). If no GTXs are used in the lower half, then the *_S supply pins can be connected to GND. All *_N
pins must always be connected to a supply because the calibration resistor resides in the upper half of the part (bank_115). For more
information consult the Virtex-6 FPGA RocketIO GTX Transceiver User Guide.
Virtex-6 FPGA Packaging
UG365 (v2.6) October 3, 2018
Die Level Bank Numbering and Clock Pins Overview
Figure1-10 shows the I/O and transceiver banks for the XC6VHX380T. The black dots
denote the global clock banks.
GTX/GTH
Banks
108
(2,5)
108
(2,5)
HROW
IOCL
Banks
28
(1)
28
(1)
27
(1)
27
(1)
26
(1)
26
(1)
25
25
24
24
23
23
22
(3)
22
(3)
21
(1,3)
21
(1,3)
20
(1,3,7)
20
(1,3,7)
Center
Bank
CLB
CLB
CLB
CLB
CLB
CLB
0
CFG
0
CFG
0
CFG
0
CFG
CLB
CLB
CLB
CLB
CLB
CLB
CLB
CLB
MMCM17
IOCR
Banks
38
(1)
38
(1)
37
(1)
37
(1)
36
(1)
36
(1)
35
35
34
34
33
(3)
33
(3)
32
(3)
32
(3)
31
(1,3)
31
(1,3)
30
(1,3,7)
30
(1,3,7)
GTX/GTH
Banks
118
(2)
118
(2)
117
(2)
117
(2)
116
(2)
116
(2)
115
115
114
114
113
113
112
(4)
112
(4)
111
(4,6)
111
(4,6)
110
(4,6)
110
(4,6)
MGTAVTTRCAL
MGTRREF
Quad
GTX
Quad
GTH
CMT
MMCM16
MMCM15
107
(2,5)
107
(2,5)
106
(2,5)
106
(2,5)
CMT
MMCM14
MMCM13
CMT
MMCM12
MMCM11
MGTAVTTRCAL
MGTRREF
105
105
104
104
103
103
102
(4)
102
(4)
101
(4)
101
(4)
100
(4)
100
(4)
CMT
MMCM10
MMCM09
CMT
MMCM08
MMCM07
CMT
MMCM06
MMCM05
CMT
MMCM04
MMCM03
CMT
MMCM02
MMCM01
CMT
MMCM00
Virtex-6 FPGA Packaging
UG365 (v2.6) October 3, 2018
2024年3月22日发(作者：掌夜绿)
Pin Name
MGTHAVCC
MGTHAVCCRX
MGTHAVTT
MGTHAVCCPLL
Direction
Input
Input
Input
Input
Description
Analog supply for the receiver and transmitter internal circuits. In Virtex-6 HXT
devices containing GTH transceivers.
Analog supply for the PLL and the receiver equalizers. In Virtex-6 HXT devices
containing GTH transceivers.
Analog supply for the transmit driver. In Virtex-6 HXT devices containing GTH
transceivers.
Analog supply for the reference clock buffer and the PLL. In Virtex-6 HXT
devices containing GTH transceivers.
GND reference for the GTH transceiver internal circuitry. These pins should be
connected to the PCB power supply GND reference plane. In Virtex-6 HXT
devices containing GTH transceivers.
GTH Quad positive differential reference clock. In Virtex-6 HXT devices
containing GTH transceivers.
GTH Quad negative differential reference clock. In Virtex-6 HXT devices
containing GTH transceivers.
GTXE1 positive differential reference clock.
GTXE1 negative differential reference clock.
Precision reference resistor pin for internal calibration termination. Always
located in Bank 115.
(4)
Precision reference resistor pin for internal calibration termination. Always
located in Bank 115.
(4)
Internal precision current, voltage, and resistor references for the GTH Quad.
Connect this pin to a 1KΩ resistor with the other terminal of the resistor
connected to GND. In Virtex-6 HXT devices containing GTH transceivers.
Reserved. No Connection; leave floating. In Virtex-6 HXT devices containing
GTH transceivers.
MGTHAGNDInput
MGTREFCLKP
MGTREFCLKN
MGTREFCLK0/1P
MGTREFCLK0/1N
MGTAVTTRCAL
MGTRREF
Input
Input
Input
Input
N/A
Input
MGTRBIASInput
RSVD
Notes:
N/A
dedicated pins (JTAG and configuration) are powered by V
CC_CONFIG
(V
CC_0
).
2.V
CCO
pins in unbonded banks must be connected to the V
CCO
for that bank for package migration. Do NOT connect unbonded
V
CCO
pins to different supplies. Without a package migration requirement, V
CCO
pins in unbonded banks can be left unconnected
or tied to a common supply (V
CCO
or ground).
more information on connecting the System Monitor pins, see Virtex-6 FPGA System Monitor User Guide.
FF484 and FF784 contain MGTAVCC and MGTAVTT pins. All other packages contain MGTAVCC_N/_S pins. All the respective
MGTAV* supply pins are connected via planes in the package to the GTXs. The MGTAVCC and MGTAVTT supply all GTXs in a
device. The MGTAVCC_N and MGTAVTT_N supply all GTXs in the upper half (North) and MGTAVCC_S and MGTAVTT_S supply
all GTXs in the lower half (South). If no GTXs are used in the lower half, then the *_S supply pins can be connected to GND. All *_N
pins must always be connected to a supply because the calibration resistor resides in the upper half of the part (bank_115). For more
information consult the Virtex-6 FPGA RocketIO GTX Transceiver User Guide.
Virtex-6 FPGA Packaging
UG365 (v2.6) October 3, 2018
Die Level Bank Numbering and Clock Pins Overview
Figure1-10 shows the I/O and transceiver banks for the XC6VHX380T. The black dots
denote the global clock banks.
GTX/GTH
Banks
108
(2,5)
108
(2,5)
HROW
IOCL
Banks
28
(1)
28
(1)
27
(1)
27
(1)
26
(1)
26
(1)
25
25
24
24
23
23
22
(3)
22
(3)
21
(1,3)
21
(1,3)
20
(1,3,7)
20
(1,3,7)
Center
Bank
CLB
CLB
CLB
CLB
CLB
CLB
0
CFG
0
CFG
0
CFG
0
CFG
CLB
CLB
CLB
CLB
CLB
CLB
CLB
CLB
MMCM17
IOCR
Banks
38
(1)
38
(1)
37
(1)
37
(1)
36
(1)
36
(1)
35
35
34
34
33
(3)
33
(3)
32
(3)
32
(3)
31
(1,3)
31
(1,3)
30
(1,3,7)
30
(1,3,7)
GTX/GTH
Banks
118
(2)
118
(2)
117
(2)
117
(2)
116
(2)
116
(2)
115
115
114
114
113
113
112
(4)
112
(4)
111
(4,6)
111
(4,6)
110
(4,6)
110
(4,6)
MGTAVTTRCAL
MGTRREF
Quad
GTX
Quad
GTH
CMT
MMCM16
MMCM15
107
(2,5)
107
(2,5)
106
(2,5)
106
(2,5)
CMT
MMCM14
MMCM13
CMT
MMCM12
MMCM11
MGTAVTTRCAL
MGTRREF
105
105
104
104
103
103
102
(4)
102
(4)
101
(4)
101
(4)
100
(4)
100
(4)
CMT
MMCM10
MMCM09
CMT
MMCM08
MMCM07
CMT
MMCM06
MMCM05
CMT
MMCM04
MMCM03
CMT
MMCM02
MMCM01
CMT
MMCM00
Virtex-6 FPGA Packaging
UG365 (v2.6) October 3, 2018