2024年3月28日发(作者：问飞航)

OCT calibration is automatically performed at power-up for OCT-enabled I/Os.

Table1–13 lists OCT variation with temperature and voltage after power-up

calibration. Use Table1–13 to determine the OCT variation after power-up calibration

and Equation1–1 to determine the OCT variation without re-calibration.

Equation1– Variation Without Re-Calibration

(1)

,

(2)

,

(3)

,

(4)

,

(5)

,

(6)

dRdR

-

V



R

OCT

=R

SCAL



1+

------

T

------



dTdV

Notes to Equation1–1:

(1)The R

OCT

value calculated from Equation1–1 shows the range of OCT resistance with the variation of temperature

and V

CCIO

.

(2)R

SCAL

is the OCT resistance value at power-up.

(3)T is the variation of temperature with respect to the temperature at power-up.

(4)V is the variation of voltage with respect to the V

CCIO

at power-up.

(5)dR/dT is the percentage change of R

SCAL

with temperature.

(6)dR/dV is the percentage change of R

SCAL

with voltage.

Table1–13 lists the OCT variation after the power-up calibration.

Table1– Variation after Power-Up Calibration

(1)

SymbolDescriptionV

CCIO

(V)

3.0

dR/dV

OCT variation with voltage without

re-calibration

2.5

1.8

1.5

1.2

3.0

dR/dT

OCT variation with temperature

without re-calibration

2.5

1.8

1.5

1.2

Note to Table1–13:

(1)Valid for V

CCIO

range of ±5% and temperature range of 0° to 85°C.

Typical

0.0297

0.0344

0.0499

0.0744

0.1241

0.189

0.208

0.266

0.273

0.317

Unit

%/mV

%/°C

Pin Capacitance

Table1–14 lists the Stratix IV device family pin capacitance.

Table1– Capacitance for Stratix IV Devices (Part 1 of 2)

Symbol

C

IOTB

C

IOLR

C

CLKTB

C

CLKLR

Description

Input capacitance on the top and bottom I/O pins

Input capacitance on the left and right I/O pins

Input capacitance on the top and bottom non-dedicated clock input pins

Input capacitance on the left and right non-dedicated clock input pins

Value

4

4

4

4

Unit

pF

pF

pF

pF

Stratix IV Device Handbook

Volume 4: Device Datasheet and Addendum

Chapter 1:DC and Switching Characteristics for Stratix IV Devices

Switching Characteristics

Table1–eiver Block Jitter Specifications for Stratix IV GX Devices

(1)

,

(2)

(Part 9 of 9)

–2 Commercial

Speed Grade

MinTyp

Jitter Frequency = 21.8

KHz

Sinusoidal Jitter

tolerance at 3072Mbps

Pattern = CJPAT

Jitter Frequency =

1843.2MHz to 20MHz

Pattern = CJPAT

Notes to Table1–30:

Symbol/

Description

Conditions

–3 Commercial/

Industrial

and –2× Commercial

Speed Grade

MinTyp

>8.5

Max

–3 Military

(3)

and

–4 Commercial/

Industrial Speed

Grade

MinTyp

>8.5

Max

Unit

Max

>8.5UI

>0.1>0.1>0.1UI

Stratix IV Device Handbook

Volume 4: Device Datasheet and Addendum

Chapter 1:DC and Switching Characteristics for Stratix IV Devices

Switching Characteristics

Stratix IV Device Handbook

Volume 4: Device Datasheet and Addendum

Chapter 1:DC and Switching Characteristics for Stratix IV Devices

Switching Characteristics

Table1–eiver Jitter Specifications for Protocols by Stratix IV GT Devices (Part 2 of 2)

Symbol/

Description

Conditions

Jitter Frequency = 40KHz

Pattern = PRBS-31

Equalization = Disabled

Sinusoidal Jitter

tolerance

BER = 1E-12

Jitter Frequency 4MHz

Pattern = PRBS-31

Equalization = Disabled

BER = 1E-12

>0.05>0.05—UI

>5>5—UI

–1 Industrial Speed –2 Industrial Speed –3 Industrial Speed

GradeGradeGrade

MinTypMaxMinTypMaxMinTypMax

Unit

Stratix IV Device Handbook

Volume 4: Device Datasheet and Addendum

Chapter 1:DC and Switching Characteristics for Stratix IV Devices

Switching Characteristics

Table1–uration Mode Specifications for Stratix IV Devices

Programming Mode

Remote update only in fast AS mode

Note to Table1–37:

(1)This denotes the maximum frequency supported in the FPP configuration scheme. The frequency supported for

each device may vary depending on device density. For more information, refer to the Configuration, Design

Security, and Remote System Upgrades in Stratix IV Devices chapter.

DCLK F

MAX

Min

4.3

Typ

5.3

Max

10

Unit

MHz

Table1–38 lists the JTAG timing parameters and values for Stratix IV devices.

Table1– Timing Parameters and Values for Stratix IV Devices

Symbol

t

JCP

t

JCH

t

JCL

t

JPSU (TDI)

t

JPSU (TMS)

t

JPH

t

JPCO

t

JPZX

t

JPXZ

Description

TCK clock period

TCK clock high time

TCK clock low time

TDI JTAG port setup time

TMS JTAG port setup time

JTAG port hold time

JTAG port clock to output

JTAG port high impedance to valid output

JTAG port valid output to high impedance

Min

30

14

14

1

3

5

—

—

—

Max

—

—

—

—

—

—

11

(1)

14

(1)

14

(1)

Unit

ns

ns

ns

ns

ns

ns

ns

ns

ns

Note to Table1–38:

(1)A 1 ns adder is required for each V

CCIO

voltage step down from 3.0 V. For example, t

JPCO

= 12 ns if V

CCIO

of the TDO

I/O bank = 2.5 V, or 13 ns if it equals 1.8 V.

Temperature Sensing Diode Specifications

Table1–39 lists the specifications for the Stratix IV temperature sensing diode.

Table1–al Temperature Sensing Diode Specifications for StratixIV Devices

Description

I

bias

, diode source current

V

bias,

voltage across diode

Series resistance

Diode ideality factor

Min

8

0.3

—

1.026

Typ

—

—

—

1.028

Max

500

0.9

< 5

1.030

Unit

A

V



—

Table1–40 lists the specifications for the Stratix IV internal temperature sensing diode.

Table1–al Temperature Sensing Diode Specifications for StratixIV Devices

Temperature

Accuracy

Range

–40 to 100°C±8°C

Offset Calibrated

Option

No

Sampling Rate

Frequency:

500kHz, 1MHz

Conversion

Time

<100ms

Resolution

8bits

Minimum Resolution

with No Missing Codes

8bits

Stratix IV Device Handbook

Volume 4: Device Datasheet and Addendum

2024年3月28日发(作者：问飞航)

OCT calibration is automatically performed at power-up for OCT-enabled I/Os.

Table1–13 lists OCT variation with temperature and voltage after power-up

calibration. Use Table1–13 to determine the OCT variation after power-up calibration

and Equation1–1 to determine the OCT variation without re-calibration.

Equation1– Variation Without Re-Calibration

(1)

,

(2)

,

(3)

,

(4)

,

(5)

,

(6)

dRdR

-

V



R

OCT

=R

SCAL



1+

------

T

------



dTdV

Notes to Equation1–1:

(1)The R

OCT

value calculated from Equation1–1 shows the range of OCT resistance with the variation of temperature

and V

CCIO

.

(2)R

SCAL

is the OCT resistance value at power-up.

(3)T is the variation of temperature with respect to the temperature at power-up.

(4)V is the variation of voltage with respect to the V

CCIO

at power-up.

(5)dR/dT is the percentage change of R

SCAL

with temperature.

(6)dR/dV is the percentage change of R

SCAL

with voltage.

Table1–13 lists the OCT variation after the power-up calibration.

Table1– Variation after Power-Up Calibration

(1)

SymbolDescriptionV

CCIO

(V)

3.0

dR/dV

OCT variation with voltage without

re-calibration

2.5

1.8

1.5

1.2

3.0

dR/dT

OCT variation with temperature

without re-calibration

2.5

1.8

1.5

1.2

Note to Table1–13:

(1)Valid for V

CCIO

range of ±5% and temperature range of 0° to 85°C.

Typical

0.0297

0.0344

0.0499

0.0744

0.1241

0.189

0.208

0.266

0.273

0.317

Unit

%/mV

%/°C

Pin Capacitance

Table1–14 lists the Stratix IV device family pin capacitance.

Table1– Capacitance for Stratix IV Devices (Part 1 of 2)

Symbol

C

IOTB

C

IOLR

C

CLKTB

C

CLKLR

Description

Input capacitance on the top and bottom I/O pins

Input capacitance on the left and right I/O pins

Input capacitance on the top and bottom non-dedicated clock input pins

Input capacitance on the left and right non-dedicated clock input pins

Value

4

4

4

4

Unit

pF

pF

pF

pF

Stratix IV Device Handbook

Volume 4: Device Datasheet and Addendum

Chapter 1:DC and Switching Characteristics for Stratix IV Devices

Switching Characteristics

Table1–eiver Block Jitter Specifications for Stratix IV GX Devices

(1)

,

(2)

(Part 9 of 9)

–2 Commercial

Speed Grade

MinTyp

Jitter Frequency = 21.8

KHz

Sinusoidal Jitter

tolerance at 3072Mbps

Pattern = CJPAT

Jitter Frequency =

1843.2MHz to 20MHz

Pattern = CJPAT

Notes to Table1–30:

Symbol/

Description

Conditions

–3 Commercial/

Industrial

and –2× Commercial

Speed Grade

MinTyp

>8.5

Max

–3 Military

(3)

and

–4 Commercial/

Industrial Speed

Grade

MinTyp

>8.5

Max

Unit

Max

>8.5UI

>0.1>0.1>0.1UI

Stratix IV Device Handbook

Volume 4: Device Datasheet and Addendum

Chapter 1:DC and Switching Characteristics for Stratix IV Devices

Switching Characteristics

Stratix IV Device Handbook

Volume 4: Device Datasheet and Addendum

Chapter 1:DC and Switching Characteristics for Stratix IV Devices

Switching Characteristics

Table1–eiver Jitter Specifications for Protocols by Stratix IV GT Devices (Part 2 of 2)

Symbol/

Description

Conditions

Jitter Frequency = 40KHz

Pattern = PRBS-31

Equalization = Disabled

Sinusoidal Jitter

tolerance

BER = 1E-12

Jitter Frequency 4MHz

Pattern = PRBS-31

Equalization = Disabled

BER = 1E-12

>0.05>0.05—UI

>5>5—UI

–1 Industrial Speed –2 Industrial Speed –3 Industrial Speed

GradeGradeGrade

MinTypMaxMinTypMaxMinTypMax

Unit

Stratix IV Device Handbook

Volume 4: Device Datasheet and Addendum

Chapter 1:DC and Switching Characteristics for Stratix IV Devices

Switching Characteristics

Table1–uration Mode Specifications for Stratix IV Devices

Programming Mode

Remote update only in fast AS mode

Note to Table1–37:

(1)This denotes the maximum frequency supported in the FPP configuration scheme. The frequency supported for

each device may vary depending on device density. For more information, refer to the Configuration, Design

Security, and Remote System Upgrades in Stratix IV Devices chapter.

DCLK F

MAX

Min

4.3

Typ

5.3

Max

10

Unit

MHz

Table1–38 lists the JTAG timing parameters and values for Stratix IV devices.

Table1– Timing Parameters and Values for Stratix IV Devices

Symbol

t

JCP

t

JCH

t

JCL

t

JPSU (TDI)

t

JPSU (TMS)

t

JPH

t

JPCO

t

JPZX

t

JPXZ

Description

TCK clock period

TCK clock high time

TCK clock low time

TDI JTAG port setup time

TMS JTAG port setup time

JTAG port hold time

JTAG port clock to output

JTAG port high impedance to valid output

JTAG port valid output to high impedance

Min

30

14

14

1

3

5

—

—

—

Max

—

—

—

—

—

—

11

(1)

14

(1)

14

(1)

Unit

ns

ns

ns

ns

ns

ns

ns

ns

ns

Note to Table1–38:

(1)A 1 ns adder is required for each V

CCIO

voltage step down from 3.0 V. For example, t

JPCO

= 12 ns if V

CCIO

of the TDO

I/O bank = 2.5 V, or 13 ns if it equals 1.8 V.

Temperature Sensing Diode Specifications

Table1–39 lists the specifications for the Stratix IV temperature sensing diode.

Table1–al Temperature Sensing Diode Specifications for StratixIV Devices

Description

I

bias

, diode source current

V

bias,

voltage across diode

Series resistance

Diode ideality factor

Min

8

0.3

—

1.026

Typ

—

—

—

1.028

Max

500

0.9

< 5

1.030

Unit

A

V



—

Table1–40 lists the specifications for the Stratix IV internal temperature sensing diode.

Table1–al Temperature Sensing Diode Specifications for StratixIV Devices

Temperature

Accuracy

Range

–40 to 100°C±8°C

Offset Calibrated

Option

No

Sampling Rate

Frequency:

500kHz, 1MHz

Conversion

Time

<100ms

Resolution

8bits

Minimum Resolution

with No Missing Codes

8bits

Stratix IV Device Handbook

Volume 4: Device Datasheet and Addendum