2024年4月6日发(作者：长孙奇正)

Spartan-6 Family Overview

The bitstream configuration information is generated by the ISE® software using a program called BitGen. The configuration

process typically executes the following sequence:

•

•

•

•

•

Detects power-up (power-on reset) or PROGRAM_B when Low.

Clears the whole configuration memory.

Samples the mode pins to determine the configuration mode: master or slave, bit-serial or parallel.

Loads the configuration data starting with the bus-width detection pattern followed by a synchronization word, checks

for the proper device code, and ends with a cyclic redundancy check (CRC) of the complete bitstream.

Starts a user-defined sequence of events: releasing the internal reset (or preset) of flip-flops, optionally waiting for the

DCMs and/or PLLs to lock, activating the output drivers, and transitioning the DONE pin to High.

The Master Serial Peripheral Interface (SPI) and the Master Byte-wide Peripheral Interface (BPI) are two common methods

used for configuring the FPGA. The Spartan-6 FPGA configures itself from a directly attached industry-standard SPI serial

flash PROM. The Spartan-6 FPGA can configure itself via BPI when connected to an industry-standard parallel NOR flash.

Note that BPI configuration is not supported in the XC6SLX4, XC6SLX25, and XC6SLX25T nor is BPI available when using

Spartan-6 FPGAs in TQG144 and CPG196 packages.

Spartan-6 FPGAs support MultiBoot configuration, where two or more FPGA configuration bitstreams can be stored in a

single configuration source. The FPGA application controls which configuration to load next and when to load it.

Spartan-6 FPGAs also include a unique, factory-programmed Device DNA identifier that is useful for tracking purposes, anti-

cloning designs, or IP protection. In the largest devices, bitstreams can be copy protected using AES encryption.

Readback

Most configuration data can be read back without affecting the system’s operation.

CLBs, Slices, and LUTs

Each configurable logic block (CLB) in Spartan-6 FPGAs consists of two slices, arranged side-by-side as part of two vertical

columns. There are three types of CLB slices in the Spartan-6 architecture: SLICEM, SLICEL, and SLICEX. Each slice

contains four LUTs, eight flip-flops, and miscellaneous logic. The LUTs are for general-purpose combinatorial and

sequential logic support. Synthesis tools take advantage of these highly efficient logic, arithmetic, and memory features.

Expert designers can also instantiate them.

SLICEM

One quarter (25%) of Spartan-6 FPGA slices are SLICEMs. Each of the four SLICEM LUTs can be configured as either a

6-input LUT with one output, or as dual 5-input LUTs with identical 5-bit addresses and two independent outputs. These

LUTs can also be used as distributed 64-bit RAM with 64 bits or two times 32 bits per LUT, as a single 32-bit shift register

(SRL32), or as two 16-bit shift registers (SRL16s) with addressable length. Each LUT output can be registered in a flip-flop

within the CLB. For arithmetic operations, a high-speed carry chain propagates carry signals upwards in a column of slices.

SLICEL

One quarter (25%) of Spartan-6 FPGA slices are SLICELs, which contain all the features of the SLICEM except the

memory/shift register function.

SLICEX

One half (50%) of Spartan-6 FPGA slices are SLICEXs. The SLICEXs have the same structure as SLICELs except the

arithmetic carry option and the wide multiplexers.

DS160 (v2.0) October 25, 2011

Product Specification

2024年4月6日发(作者：长孙奇正)

Spartan-6 Family Overview

The bitstream configuration information is generated by the ISE® software using a program called BitGen. The configuration

process typically executes the following sequence:

•

•

•

•

•

Detects power-up (power-on reset) or PROGRAM_B when Low.

Clears the whole configuration memory.

Samples the mode pins to determine the configuration mode: master or slave, bit-serial or parallel.

Loads the configuration data starting with the bus-width detection pattern followed by a synchronization word, checks

for the proper device code, and ends with a cyclic redundancy check (CRC) of the complete bitstream.

Starts a user-defined sequence of events: releasing the internal reset (or preset) of flip-flops, optionally waiting for the

DCMs and/or PLLs to lock, activating the output drivers, and transitioning the DONE pin to High.

The Master Serial Peripheral Interface (SPI) and the Master Byte-wide Peripheral Interface (BPI) are two common methods

used for configuring the FPGA. The Spartan-6 FPGA configures itself from a directly attached industry-standard SPI serial

flash PROM. The Spartan-6 FPGA can configure itself via BPI when connected to an industry-standard parallel NOR flash.

Note that BPI configuration is not supported in the XC6SLX4, XC6SLX25, and XC6SLX25T nor is BPI available when using

Spartan-6 FPGAs in TQG144 and CPG196 packages.

Spartan-6 FPGAs support MultiBoot configuration, where two or more FPGA configuration bitstreams can be stored in a

single configuration source. The FPGA application controls which configuration to load next and when to load it.

Spartan-6 FPGAs also include a unique, factory-programmed Device DNA identifier that is useful for tracking purposes, anti-

cloning designs, or IP protection. In the largest devices, bitstreams can be copy protected using AES encryption.

Readback

Most configuration data can be read back without affecting the system’s operation.

CLBs, Slices, and LUTs

Each configurable logic block (CLB) in Spartan-6 FPGAs consists of two slices, arranged side-by-side as part of two vertical

columns. There are three types of CLB slices in the Spartan-6 architecture: SLICEM, SLICEL, and SLICEX. Each slice

contains four LUTs, eight flip-flops, and miscellaneous logic. The LUTs are for general-purpose combinatorial and

sequential logic support. Synthesis tools take advantage of these highly efficient logic, arithmetic, and memory features.

Expert designers can also instantiate them.

SLICEM

One quarter (25%) of Spartan-6 FPGA slices are SLICEMs. Each of the four SLICEM LUTs can be configured as either a

6-input LUT with one output, or as dual 5-input LUTs with identical 5-bit addresses and two independent outputs. These

LUTs can also be used as distributed 64-bit RAM with 64 bits or two times 32 bits per LUT, as a single 32-bit shift register

(SRL32), or as two 16-bit shift registers (SRL16s) with addressable length. Each LUT output can be registered in a flip-flop

within the CLB. For arithmetic operations, a high-speed carry chain propagates carry signals upwards in a column of slices.

SLICEL

One quarter (25%) of Spartan-6 FPGA slices are SLICELs, which contain all the features of the SLICEM except the

memory/shift register function.

SLICEX

One half (50%) of Spartan-6 FPGA slices are SLICEXs. The SLICEXs have the same structure as SLICELs except the

arithmetic carry option and the wide multiplexers.

DS160 (v2.0) October 25, 2011

Product Specification