2024年5月31日发(作者：塞吉月)

赛灵思半导体（深圳）

Artix-7 FPGA Feature Summary

Table 4:Artix-7 FPGA Feature Summary by Device

Logic

Cells

Configurable Logic Blocks

(CLBs)

Slices

(1)

2,000

2,600

3,650

5,200

8,150

11,800

15,850

33,650

Max

Distributed

RAM (Kb)

171

200

313

400

600

892

1,188

2,888

Block RAM Blocks

(3)

DSP48E1

Slices

(2)

18Kb

40

50

90

100

150

210

270

730

36Kb

20

25

45

50

75

105

135

365

Max

(Kb)

720

900

1,620

1,800

2,700

3,780

4,860

13,140

CMTs

(4)

7Series FPGAs Data Sheet: Overview

DevicePCIe

(5)

GTPs

XADC

Blocks

Total I/O

Banks

(6)

Max User

I/O

(7)

XC7A12T

XC7A15T

XC7A25T

XC7A35T

XC7A50T

XC7A75T

XC7A100T

XC7A200T

12,800

16,640

23,360

33,280

52,160

75,520

101,440

215,360

40

45

80

90

120

180

240

740

3

5

3

5

5

6

6

10

1

1

1

1

1

1

1

1

2

4

4

4

4

8

8

16

1

1

1

1

1

1

1

1

3

5

3

5

5

6

6

10

150

250

150

250

250

300

300

500

Notes:

7series FPGA slice contains four LUTs and eight flip-flops; only some slices can use their LUTs as distributed RAM or SRLs.

DSP slice contains a pre-adder, a 25x18 multiplier, an adder, and an accumulator.

RAMs are fundamentally 36Kb in size; each block can also be used as two independent 18Kb blocks.

CMT contains one MMCM and one PLL.

-7 FPGA Interface Blocks for PCI Express support up to x4 Gen 2.

not include configuration Bank 0.

number does not include GTP transceivers.

Table 5:Artix-7 FPGA Device-Package Combinations and Maximum I/Os

Package

(1)

Size (mm)

Ball Pitch

(mm)

Device

XC7A12T

XC7A15T

XC7A25T

XC7A35T

XC7A50T

XC7A75T

XC7A100T

XC7A200T

2

2

106

106

2106

2112

0

0

0

0

210

210

210

210

GTP

(4)

CPG236

10 x 10

0.5

I/O

HR

(5)

CPG238

10 x 10

0.5

GTP

(4)

CSG324

15 x 15

0.8

CSG325

15 x 15

0.8

FTG256

17 x 17

1.0

SBG484

19 x 19

0.8

FGG484

(2)

23 x 23

1.0

FBG484

(2)

23 x 23

1.0

FGG676

(3)

27 x 27

1.0

FBG676

(3)

27 x 27

1.0

FFG1156

35 x 35

1.0

I/O

HR

(5)

GTP

(4)

I/O

HR

(5)

GTP

(4)

I/O

HR

(5)

GTP

(4)

I/O

HR

(5)

GTP

I/O

HR

(5)

GTP

(4)

I/O

HR

(5)

GTP

I/O

HR

(5)

GTP

(4)

I/O

HR

(5)

GTP

I/O

HR

(5)

GTP

I/O

HR

(5)

2112

0210

2

4

4

4

4

150

150

150

150

150

0

0

0

0

170

170

170

170

4285

4

4

4

4

250

250

285

285

4285

8

8

300

300

840016500

01704250

Notes:

packages listed are Pb-free (SBG, FBG, FFG with exemption 15). Some packages are available in Pb option.

s in FGG484 and FBG484 are footprint compatible.

s in FGG676 and FBG676 are footprint compatible.

transceivers in CP, CS, FT, and FG packages support data rates up to 6.25Gb/s.

= High-range I/O with support for I/O voltage from 1.2V to 3.3V.

DS180 (v2.6) February 27, 2018

Product Specification

赛灵思半导体（深圳）

质量等级领域:宇航级IC、特军级IC、超军级IC、普军级IC、禁运IC、工

业级IC，军级二三极管，功率管等;

应用领域:航空航天、船舶、汽车电子、军用计算机、铁路、医疗电子、通

信网络、电力工业以及大型工业设备

祝您:工作顺利，生活愉快!

以赛灵思半导体（深圳）有限公司提供的参数为例，以下为XC7K160T-2FBG676I的详细参数，仅供参考

2024年5月31日发(作者：塞吉月)

赛灵思半导体（深圳）

Artix-7 FPGA Feature Summary

Table 4:Artix-7 FPGA Feature Summary by Device

Logic

Cells

Configurable Logic Blocks

(CLBs)

Slices

(1)

2,000

2,600

3,650

5,200

8,150

11,800

15,850

33,650

Max

Distributed

RAM (Kb)

171

200

313

400

600

892

1,188

2,888

Block RAM Blocks

(3)

DSP48E1

Slices

(2)

18Kb

40

50

90

100

150

210

270

730

36Kb

20

25

45

50

75

105

135

365

Max

(Kb)

720

900

1,620

1,800

2,700

3,780

4,860

13,140

CMTs

(4)

7Series FPGAs Data Sheet: Overview

DevicePCIe

(5)

GTPs

XADC

Blocks

Total I/O

Banks

(6)

Max User

I/O

(7)

XC7A12T

XC7A15T

XC7A25T

XC7A35T

XC7A50T

XC7A75T

XC7A100T

XC7A200T

12,800

16,640

23,360

33,280

52,160

75,520

101,440

215,360

40

45

80

90

120

180

240

740

3

5

3

5

5

6

6

10

1

1

1

1

1

1

1

1

2

4

4

4

4

8

8

16

1

1

1

1

1

1

1

1

3

5

3

5

5

6

6

10

150

250

150

250

250

300

300

500

Notes:

7series FPGA slice contains four LUTs and eight flip-flops; only some slices can use their LUTs as distributed RAM or SRLs.

DSP slice contains a pre-adder, a 25x18 multiplier, an adder, and an accumulator.

RAMs are fundamentally 36Kb in size; each block can also be used as two independent 18Kb blocks.

CMT contains one MMCM and one PLL.

-7 FPGA Interface Blocks for PCI Express support up to x4 Gen 2.

not include configuration Bank 0.

number does not include GTP transceivers.

Table 5:Artix-7 FPGA Device-Package Combinations and Maximum I/Os

Package

(1)

Size (mm)

Ball Pitch

(mm)

Device

XC7A12T

XC7A15T

XC7A25T

XC7A35T

XC7A50T

XC7A75T

XC7A100T

XC7A200T

2

2

106

106

2106

2112

0

0

0

0

210

210

210

210

GTP

(4)

CPG236

10 x 10

0.5

I/O

HR

(5)

CPG238

10 x 10

0.5

GTP

(4)

CSG324

15 x 15

0.8

CSG325

15 x 15

0.8

FTG256

17 x 17

1.0

SBG484

19 x 19

0.8

FGG484

(2)

23 x 23

1.0

FBG484

(2)

23 x 23

1.0

FGG676

(3)

27 x 27

1.0

FBG676

(3)

27 x 27

1.0

FFG1156

35 x 35

1.0

I/O

HR

(5)

GTP

(4)

I/O

HR

(5)

GTP

(4)

I/O

HR

(5)

GTP

(4)

I/O

HR

(5)

GTP

I/O

HR

(5)

GTP

(4)

I/O

HR

(5)

GTP

I/O

HR

(5)

GTP

(4)

I/O

HR

(5)

GTP

I/O

HR

(5)

GTP

I/O

HR

(5)

2112

0210

2

4

4

4

4

150

150

150

150

150

0

0

0

0

170

170

170

170

4285

4

4

4

4

250

250

285

285

4285

8

8

300

300

840016500

01704250

Notes:

packages listed are Pb-free (SBG, FBG, FFG with exemption 15). Some packages are available in Pb option.

s in FGG484 and FBG484 are footprint compatible.

s in FGG676 and FBG676 are footprint compatible.

transceivers in CP, CS, FT, and FG packages support data rates up to 6.25Gb/s.

= High-range I/O with support for I/O voltage from 1.2V to 3.3V.

DS180 (v2.6) February 27, 2018

Product Specification

赛灵思半导体（深圳）

质量等级领域:宇航级IC、特军级IC、超军级IC、普军级IC、禁运IC、工

业级IC，军级二三极管，功率管等;

应用领域:航空航天、船舶、汽车电子、军用计算机、铁路、医疗电子、通

信网络、电力工业以及大型工业设备

祝您:工作顺利，生活愉快!

以赛灵思半导体（深圳）有限公司提供的参数为例，以下为XC7K160T-2FBG676I的详细参数，仅供参考