2024年11月5日发(作者：刁樱)

BL24C04F 4Kbits (512×8)

Features



Compatible with all I²C bidirectional data

transfer protocol





–

Partial Page Writes Allowed

Write Protect Pin for Hardware Data Protection

Schmitt Trigger, Filtered Inputs for Noise

Suppression

High-reliability

–

–



Memory array:

–

–

4 Kbits (512bytes) of EEPROM

Page size: 16 bytes

1MHZ

Random and sequential Read modes

Byte Write within 3 ms

Page Write within 3 ms







Single supply voltage and high speed:

–

–

Endurance: 1 Million Write Cycles

Data Retention: 100 Years

HBM 6000V

Enhanced ESD/Latch-up protection

–



Write:

–

–



8-lead PDIP/SOP/TSSOP/ UDFN and TSOT23-

5packages

Description



The BL24C04F provides 2048 bits of serial



The device is optimized for use in many industrial

electrically erasable and programmable read-

only memory (EEPROM), organized as 256 words

of 8 bits each.

and commercial applications where low-power

and low-voltage operation are essential.

Pin Configuration

８-lead PDIP８-lead SOP８-lead TSSOP８-pad DFN

5-lead TSOT23-5

WPVCC

1NC

2A1

3A2

4GND

１２３

５４

NC

A1

A2

GND

１

２

３

４

8

7

6

5

VCC

WP

SCL

SDA

NC

A1

A2

GND

１

２

３

４

8

7

6

5

VCC

WP

SCL

SDA

NC

A1

A2

GND

１

２

３

４

8

7

6

5

VCC

WP

SCL

SDA

VCC

WP

8

7

SCL6

SDA5

Bottem view

SCLGNDSDA

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BL24C04F 4Kbits (512×8)

Pin Descriptions

Pin Name

A1-A2

SDA

SCL

WP

GND

Vcc

Type

I

I/O

I

I

P

P

Table 1

Functions

Address Inputs

Serial Data

Serial Clock Input

Write Protect

Ground

Power Supply

Block Diagram

Vcc

GND

WP

SCL

SDA

START STOP

LOGIC

EN

SERIAL CONTROL

LOGIC

LOAD

CCMP

DEVICE ADDRESS

COMPARATOR

LOADINC

DATA RECOVERY

HIGH VOLTAGE

PUMP/TIMING

X DECODER

A1

A2

DATA WORD

ADRESS COUNTER

EEPROM

Y DECODERSERIAL MUX

DIN

DOUT/ACKNOWLEDGE

DOUT

Figure 1

DEVICE/PAGE ADDRESSES (A2, A1 and A0): The A2, A1 and A0 pins are device address inputs that are hard

wire for the BL24C04F. Eight 2K devices may be addressed on a single bus system (device addressing is

discussed in detail under the Device Addressing section).

SERIAL DATA (SDA): The SDA pin is bi-directional for serial data transfer. This pin is open-drain driven

and may be wire-ORed with any number of other open-drain or open- collector devices.

SERIAL CLOCK (SCL): The SCL input is used to positive edge clock data into each EEPROM device and

negative edge clock data out of each device.

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BL24C04F 4Kbits (512×8)

WRITE PROTECT (WP): The BL24C04F has a Write Protect pin that provides hardware data protection.

The Write Protect pin allows normal read/write operations when connected to ground (GND). When the

Write Protection pin is connected to Vcc, the write protection feature is enabled and operates as shown

in the following Table 2.

WP Pin Status

At VCC

At GND

BL24C04F

Full(4K)Array

Normal Read/Write Operations

Table 2

Functional Description

1. Memory Organization

BL24C04F, 4K SERIAL EEPROM: Internally organized with 32 pages of 16 bytes each, the 4K requires a 9-

bit data word address for random word addressing.

2. Device Operation

CLOCK and DATA TRANSITIONS: The SDA pin is normally pulled high with an external device. Data on the

SDA pin may change only during SCL low time periods (see Figure 2). Data changes during SCL high

periods will indicate a start or stop condition as defined below.

START CONDITION: A high-to-low transition of SDA with SCL high is a start condition which must precede

any other command (see Figure 3).

STOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition. After a read

sequence, the stop command will place the EEPROM in a standby power mode (see Figure 3).

ACKNOWLEDGE: All addresses and data words are serially transmitted to and from the EEPROM in 8-bit

words. The EEPROM sends a "0" to acknowledge that it has received each word. This happens during

the ninth clock cycle.

STANDBY MODE: The BL24C04F features a low-power standby mode which is enabled: (a) upon power-up

and (b) after the receipt of the STOP bit and the completion of any internal operations.

MEMORY RESET: After an interruption in protocol, power loss or system reset, any two-wire part can be

reset by following these steps:

1. Clock up to 9 cycles.

2. Look for SDA high in each cycle while SCL is high.

3. Create a start condition.

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BL24C04F 4Kbits (512×8)

SDA

SCL

DATA STABLE

DATA CHANGE

DATA STABLE

Figure 2. Data Validity

SDA

SCL

START

STOP

Figure 3. Start and Stop Definition

SCL189

DATA IN

DATA OUT

START

ACKNOWLEDGE

Figure 4. Output Acknowledge

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BL24C04F 4Kbits (512×8)

3. Device Addressing

The 4K EEPROM devices all require an 8-bit device address word following a start condition to enable

the chip for a read or write operation (see Figure 5)

MSB

1010A2A1B8

LSB

R/W

Figure 5. Device Address

The device address word consists of a mandatory "1", "0" sequence for the first four most significant

bits as shown. This is common to all the Serial EEPROM devices.

The 4K EEPROM uses A2 and A1 device address bits to allow as much as for devices on the same bus.

These 2 bits must be compared to their corresponding hardwired input pins. The A2 and A1 pins use an

internal proprietary circuit that biases them to a logic low condition if the pins are allowed to float.

The eighth bit of the device address is the read/write operation select bit. A read operation is initiated if

this bit is high and a write operation is initiated if this bit is low.

Upon a compare of the device address, the EEPROM will output a "0". If a compare is not made, the

chip will return to a standby state.

DATA SECURITY: The BL24C04F has a hardware data protection scheme that allows the user to write

protect the entire memory when the WP pin is at VCC.

4. Write Operations

BYTE WRITE: A write operation requires an 9-bit data word address following the device address word

and acknowledgment. Upon receipt of this address, the EEPROM will again respond with a "0" and then

clock in the first 8-bit data word. Following receipt of the 8-bit data word, the EEPROM will output a "0"

and the addressing device, such as a microcontroller, must terminate the write sequence with a stop

condition. At this time the EEPROM enters an internally timed write cycle, tWR, to the nonvolatile

memory. All inputs are disabled during this write cycle and the EEPROM will not respond until the write

is complete (see Figure 7).

MSB

1010A2A1B8

LSB

R/W

B7B6B5B4B3B2B1B0

Figure 6. ADDRESS

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BL24C04F 4Kbits (512×8)

S

T

A

R

T

SDA

LINE

M

S

B

DEVICE

ADDRESS

W

R

I

T

E

ADDRESSDATA

S

T

O

P

LRA

S/C

BWK

LA

SC

BK

LA

SC

BK

Figure 7. Byte Write

PAGE WRITE: The 4K EEPROM is capable of an 16-byte page write. A page write is initiated the same as

a byte write, but the microcontroller does not send a stop condition after the first data word is clocked

in. Instead, after the EEPROM acknowledges receipt of the first data word, the microcontroller can

transmit up to seven more data words. The EEPROM will respond with a "0" after each data word

received. The microcontroller must terminate the page write sequence with a stop condition (see

Figure 8).

S

T

A

R

T

SDA

LINE

M

S

B

LRA

S/C

BWK

LA

SC

BK

LA

SC

BK

A

C

K

A

C

K

DEVICE

ADDRESS

W

R

I

T

E

ADDRESSDATA(n)DATA(n+1)DATA(n+1)

S

T

O

P

Figure 8. Page Write

The data word address lower three bits are internally incremented following the receipt of each data

word. The higher data word address bits are not incremented, retaining the memory page row location.

When the word address, internally generated, reaches the page boundary, the following byte is placed

at the beginning of the same page. If more than eight data words are transmitted to the EEPROM, the

data word address will "roll over" and previous data will be overwritten.

ACKNOWLEDGE POLLING: Once the internally timed write cycle has started and the EEPROM inputs are

disabled, acknowledge polling can be initiated. This involves sending a start condition followed by the

device address word. The read/write bit is representative of the operation desired. Only if the internal

write cycle has completed will the EEPROM respond with a "0", allowing the read or write sequence to

continue.

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5. Read Operations

Read operations are initiated the same way as write operations with the exception that the

read/write select bit in the device address word is set to "1". There are three read operations: current

address read, random address read and sequential read.

CURRENT ADDRESS READ: The internal data word address counter maintains the last address accessed

during the last read or write operation, incremented by one. This address stays valid between

operations as long as the chip power is maintained. The address "roll over" during read is from the last

byte of the last memory page to the first byte of the first page. The address "roll over" during write is

from the last byte of the current page to the first byte of the same page. Once the device address with

the read/write select bit set to "1" is clocked in and acknowledged by the EEPROM, the current address

data word is serially clocked out. The microcontroller does not respond with an input "0" but does

generate a following stop condition (see Figure 9).

S

T

A

R

T

SDA

LINE

M

S

B

LRA

S/C

BWK

NO

ACK

DEVICE

ADDRESS

R

E

A

D

DATA

S

T

O

P

Figure 9. Current Address Read

RANDOM READ: A random read requires a "dummy" byte write sequence to load in the data word

address. Once the device address word and data word address are clocked in and acknowledged by the

EEPROM, the microcontroller must generate another start condition. The microcontroller now initiates a

current address read by sending a device address with the read/write select bit high. The EEPROM

acknowledges the device address and serially clocks out the data word. The microcontroller does not

respond with a "0" but does generate a following stop condition (see Figure 10)

S

T

A

R

T

SDA

LINE

M

S

B

LRA

S/C

BWK

LA

SC

BK

A

C

K

NO

ACK

W

R

I

T

E

S

T

A

R

T

DEVICE

ADDRESS

ADDRESS

DEVICE

ADDRESS

R

E

A

D

DATA(n)

S

T

O

P

DUMMY WRITE

Note.1*=DON'T CARE bits

Figure 10. Random Read

SEQUENTIAL READ: Sequential reads are initiated by either a current address read or a random address

read. After the microcontroller receives a data word, it responds with an acknowledge. As long as the

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BL24C04F 4Kbits (512×8)

EEPROM receives an acknowledge, it will continue to increment the data word address and serially

clock out sequential data words. When the memory address limit is reached, the data word address will

"roll over" and the sequential read will continue. The sequential read operation is terminated when the

microcontroller does not respond with a "0" but does generate a following stop condition (see Figure

11).

DEVICE

ADDRESS

SDA

LINE

R

E

A

D

DATA(n)DATA(n+1)DATA(n+2)DATA(n+x)

S

T

O

P

RA

/C

WK

A

C

K

A

C

K

A

C

K

NO

ACK

Figure 11. Sequential Read

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BL24C04F 4Kbits (512×8)

Electrical Characteristics

Absolute Maximum Stress Ratings：











DC Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6.5V

Input / Output Voltage . . . . . . . . . . . . . GND-0.3V to VCC+0.3V

Operating Ambient Temperature . . . . . . . . . . . . -40℃ to +85℃

Storage Temperature . . . . . . . . . . . . . . . . . . . . .-65℃ to +150℃

Electrostatic pulse (Human Body model) . . . . . . . . . . . . . 6000V

Comments:

Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to this

device. These are stress ratings only. Functional operation of this device at these or any other

conditions above those indicated in the operational sections of this specification is not implied or

intended. Exposure to the absolute maximum rating conditions for extended periods may affect device

reliability.

DC Electrical Characteristics

Applicable over recommended operating range from: TA = -40℃ to +85℃, VCC = +1.7V to +5.5V

(unless otherwise noted)

Parameter

Supply Voltage

Supply Current VCC=5.0V

Supply Current VCC=5.0V

Supply Current VCC=5.0V

Input Leakage Current

Output Leakage Current

Input Low Level

Input High Level

Output Low Level VCC=1.7V

Output Low Level VCC=5.0V

Pin Capacitance

Symbol

V

CC1

I

CC1

I

CC2

I

SB1

I

L1

I

LO

V

IL1

V

IH1

V

OL1

V

OL2

Min

1.7

-

-

-

-

-

-0.3

V

CC

×0.7

-

-

Typ

-

0.14

0.28

0.03

0.10

0.05

-

-

-

-

Max

5.5

0.3

0.5

0.5

1.0

1.0

V

CC

×0.3

V

CC

+0.3

0.2

0.4

Unit

V

mA

mA

μA

μA

μA

V

V

V

V

-

Condition

READ at 400KHZ

WRITE at 400KHZ

V

IN

=V

CC

or V

SS

V

IN

=V

CC

or V

SS

V

OUT

=V

CC

or V

SS

V

CC

=1.7V to 5.5V

V

CC

=1.7V to 5.5V

I

OL

=0.15mA

I

OL

=3.0mA

Table 3

Applicable over recommended operating range from TA = 25℃, f = 1.0 MHz, VCC = +1.7V

Parameter

Input/Output Capacitance(SDA)

Input Capacitance(A0,A1,A2,SCL)

Symbol

C

I/O

C

IN

Min

-

-

Typ

-

-

Max

8

6

Unit

pF

pF

Condition

V

IO

=0V

V

IN

=0V

Table 4

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BL24C04F 4Kbits (512×8)

AC Electrical Characteristics

Applicable over recommended operating range from TA = -40℃ to +85℃, VCC = +1.8V to +5.5V, CL =

1 TTL Gate and 100 pF (unless otherwise noted)

Parameter

Clock Frequency,SCL

Clock Pulse Width Low

Clock Pulse Width High

Noise Suppression Time

Clock Low to Data Out Valid

Time the bus must be free

before a new transmission can

start

Start Hold Time

Start Setup Time

Data In Hold Time

Data in Setup Time

Input Rise Time(1)

Input Fall Time(1)

Stop Setup Time

Data Out Hold Time

Write Cycle Time

5.0V,25℃,Byte Mode(1)

Symbol

f

SCL

t

LOW

t

HIGH

t

I

t

AA

t

BUF

t

HD:STA

t

SU:STA

t

HD:DAT

t

SU:DAT

t

R

t

F

t

Su:STO

t

DH

tw

R

1.7V≤V

CC

﹤2.5V

Min

-

1.3

0.6

-

-

1.3

0.6

0.6

0

100

-

-

0.6

50

-

Table 5

2.5V≤V

CC

﹤5.5V

Min

-

0.5

0.26

-

-

0.5

0.25

0.25

0

100

-

-

0.25

50

-

1M

Typ

-

-

-

-

-

-

-

-

-

-

-

-

-

-

1.9

-

Max

1000

-

-

50

0.45

-

-

-

-

-

0.12

0.12

-

-

3

-

Typ

-

-

-

-

-

-

-

-

-

-

-

-

-

-

1.9

-

Max

400

-

-

50

0.9

-

-

-

-

-

0.3

0.3

-

-

3

-

Units

kHz

μs

μs

ns

μs

μs

μs

μs

μs

ns

μs

μs

μs

ns

ms

Write Cycle

Endurance1M

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BL24C04F 4Kbits (512×8)

Bus Timing

t

F

SCL

t

t

LOW

t

t

t

t

t

HIGH

t

LOW

t

R

SDA_IN

t

AA

SDA_OUT

t

DH

t

BUF

Figure 12. SCL: Serial Clock, SDA: Serial Data I/O

Write Cycle Timing

SCL

ACK

SDA

Word n

tWR(1)

STOP

CONDITION

START

CONDITION

Figure 13. SCL: Serial Clock, SDA: Serial Data I/O

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Package Information

PDIP Outline Dimensions

E

E1

C

Top View

eA

End View

COMMON DIMENSIONS

(Unit of Measure=inches)

D1

D

e

A2A

B3

4PLCS

Side View

b2

b

L

SYMBOL

A

A2

b

b2

b3

c

D

D1

E

E1

e

eA

L

MIN

0.115

0.014

0.045

0.030

0.008

0.355

0.005

0.300

0.240

NOM

0.130

0.018

0.060

0.039

0.010

0.365

0.310

0.250

0.100BSC

0.300BSC

0.130

MAX

0.210

0.195

0.022

0.070

0.045

0.014

0.400

0.325

0.280

NOTE

2

5

6

6

3

3

4

3

4

20.1150.150

Figure 14

Notes:

drawing is for general information only; refer to JEDEC Drawing MS-001, Variation BA for additional

information.

2. Dimensions A and L are measured with the package seated in JEDEC seating plane Gauge GS-3.

3. D, D1 and E1 dimensions do not include mold Flash or protrusions. Mold Flash or protrusions shall not exceed

0.010 inch.

4. E and eA measured with the leads constrained to be perpendicular to datum.

5. Pointed or rounded lead tips are preferred to ease insertion.

6. b2 and b3 maximum dimensions do not include Dambar protrusions. Dambar protrusions shall not exceed 0.010

(0.25 mm).

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SOP

1

E

E1

N

Φ

L

COMMON DIMENSIONS

(Unit of Measure=mm)

e

B

A1

A

D

SYMBOL

A

A1

b

C

D

E1

E1

E1

L

Φ

MIN

1.35

0.10

0.31

0.17

4.80

3.81

5.79

0.40

0"

NOM

-

-

-

-

-

-

-

1.27BSC

-

-

MAX

1.75

0.25

0.51

0.25

5.00

3.99

6.20

1.27

8"

NOTE

Figure 15

Notes:

These drawings are for general information only. Refer to JEDEC Drawing MS-012, Variation AA for proper

dimensions, tolerances, datums, etc.

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TSSOP

321

E1E

L1

N

Top View

b

A

End View

L

COMMON DIMENSIONS

Unit of Measure=mm

SYMBOL

D

E

E1

A

A2

b

e

L

L1

MIN

2.90

4.30

-

0.80

0.19

0.45

NOMMAX

3.003.10

6.40BSC

4.404.50

-1.20

1.001.05

-0.30

0.65BSC

0.600.75

1.00REF

NOTE

2,5

3,5

e

A2

4

D

Side View

Figure 16

NOTES:

1. This drawing is for general information only. Refer to JEDEC Drawing MO-153, Variation AA, for proper

dimensions, tolerances, datums, etc.

2. Dimension D does not include mold Flash, protrusions or gate burrs. Mold Flash, protrusions and gate burrs shall

not exceed 0.15 mm (0.006 in) per side.

3. Dimension E1 does not include inter-lead Flash or protrusions. Inter-lead Flash and protrusions shall not exceed

0.25 mm (0.010 in) per side.

4. Dimension b does not include Dambar protrusion. Allowable Dambar protrusion shall be 0.08 mm total in excess

of the b dimension at maximum material condition. Dambar cannot be located on the lower radius of the foot.

Minimum space between protrusion and adjacent lead is 0.07 mm.

5. Dimension D and E1 to be determined at Datum Plane H.

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UDFN

D

D2

L

PIN 1 DOT

BY MARKING

E

E2

PIN #1 IDENTIFICATION

CHAMFER

TOP VIEW

b

e

BOTTOM VIEW

PKG

REF

A

A1

A3

D

E

b

L

D2

E2

e

Figure 17

A

A1

A3

SIDE VIEW

COMMON DIMENSION(MM)

UT:ULTRA THIN

MINNOMMAX

>0.500.550.60

0.00-0.05

0.15REF

1.952.002.05

2.953.003.05

0.200.250.30

0.200.300.40

1.251.401.50

1.151.301.40

0.50BSC

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TSOT23-5

D

e1

L2

R1

Θ1(4X)

R

L

(L1)

Θ2(4X)

E

E1

Θ

Pin 1

b

e

TOP VIEW

0.20

M

B

B

SIDE VIEW

COMMON DIMENSIONS

(UNITS OF MEASURE = MILLIMETER)

SYMBOL

A

A1

A2

A3

c

c1

D

E

E1

e

e1

L

L1

L2

R

R1

Θ

Θ1

Θ2

MIN

-

0.00

0.65

0.35

0.14

0.14

2.85

2.65

1.60

0.90

1.80

0.30

NOM

-

-

0.75

0.40

-

0.15

2.95

2.80

1.65

0.95

1.90

0.45

0.575REF

0.258BSC

-

-

-

5°

12°

MAX

0.90

0.15

0.85

0.45

0.20

0.16

3.05

2.95

1.70

1.00

2.00

0.60

A3

A

A2

0.10

SIDE VIEW

A1

-

-

0°

3°

10°

0.25

0.25

8°

7°

14°

Figure 18

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BL24C04F 4Kbits (512×8)

Marking Diagram

PDIP

BL24C04F

YYWW#ZZ

SSSSSP

YY: year

WW :week

ZZ: assembly house

SSSSS : Lot ID

SOP

BL24C04F

SSSSSP

SSSSS : Lot ID

TSSOP

BL24C04F

SSSSS

SSSSS : Lot ID

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BL24C04F 4Kbits (512×8)

TSOT23-5

24C04F

SSSSSP

SSSSS : Lot ID

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BL24C04F 4Kbits (512×8)

Ordering Information

BL24C04F- 1 2 3

Code Description

Package type

PA: SOP-8L

SF: TSSOP-8L

DA: PDIP-8L

1 NT: UDFN-8L

TC: SOT23-5L

RR: TSOT23-5L

MA: M2.2

MB: M3.2

Packing type

2 R: Tape and Reel

T: Tube

Feature

3 S: Standard (default, Pb Free RoHS Std.)

C: Green (Halogen Free)

Device

BL24C04F

BL24C04F

BL24C04F

BL24C04F

Package

SOP8

TSSOP8L

UDFN

SOT23-5

Shipping(Qty/Packing)

2500/Tape &Reel

3000/Tape &Reel

3000/Tape &Reel

3000/Tape &Reel

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BL24C04F 4Kbits (512×8)

Revision history

Version 1.00 BL24C04F

Initial vision

Version 1.01 BL24C04F 3/7/2017

Update the AC Electrical Characteristics

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2024年11月5日发(作者：刁樱)

BL24C04F 4Kbits (512×8)

Features



Compatible with all I²C bidirectional data

transfer protocol





–

Partial Page Writes Allowed

Write Protect Pin for Hardware Data Protection

Schmitt Trigger, Filtered Inputs for Noise

Suppression

High-reliability

–

–



Memory array:

–

–

4 Kbits (512bytes) of EEPROM

Page size: 16 bytes

1MHZ

Random and sequential Read modes

Byte Write within 3 ms

Page Write within 3 ms







Single supply voltage and high speed:

–

–

Endurance: 1 Million Write Cycles

Data Retention: 100 Years

HBM 6000V

Enhanced ESD/Latch-up protection

–



Write:

–

–



8-lead PDIP/SOP/TSSOP/ UDFN and TSOT23-

5packages

Description



The BL24C04F provides 2048 bits of serial



The device is optimized for use in many industrial

electrically erasable and programmable read-

only memory (EEPROM), organized as 256 words

of 8 bits each.

and commercial applications where low-power

and low-voltage operation are essential.

Pin Configuration

８-lead PDIP８-lead SOP８-lead TSSOP８-pad DFN

5-lead TSOT23-5

WPVCC

1NC

2A1

3A2

4GND

１２３

５４

NC

A1

A2

GND

１

２

３

４

8

7

6

5

VCC

WP

SCL

SDA

NC

A1

A2

GND

１

２

３

４

8

7

6

5

VCC

WP

SCL

SDA

NC

A1

A2

GND

１

２

３

４

8

7

6

5

VCC

WP

SCL

SDA

VCC

WP

8

7

SCL6

SDA5

Bottem view

SCLGNDSDA

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BL24C04F 4Kbits (512×8)

Pin Descriptions

Pin Name

A1-A2

SDA

SCL

WP

GND

Vcc

Type

I

I/O

I

I

P

P

Table 1

Functions

Address Inputs

Serial Data

Serial Clock Input

Write Protect

Ground

Power Supply

Block Diagram

Vcc

GND

WP

SCL

SDA

START STOP

LOGIC

EN

SERIAL CONTROL

LOGIC

LOAD

CCMP

DEVICE ADDRESS

COMPARATOR

LOADINC

DATA RECOVERY

HIGH VOLTAGE

PUMP/TIMING

X DECODER

A1

A2

DATA WORD

ADRESS COUNTER

EEPROM

Y DECODERSERIAL MUX

DIN

DOUT/ACKNOWLEDGE

DOUT

Figure 1

DEVICE/PAGE ADDRESSES (A2, A1 and A0): The A2, A1 and A0 pins are device address inputs that are hard

wire for the BL24C04F. Eight 2K devices may be addressed on a single bus system (device addressing is

discussed in detail under the Device Addressing section).

SERIAL DATA (SDA): The SDA pin is bi-directional for serial data transfer. This pin is open-drain driven

and may be wire-ORed with any number of other open-drain or open- collector devices.

SERIAL CLOCK (SCL): The SCL input is used to positive edge clock data into each EEPROM device and

negative edge clock data out of each device.

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BL24C04F 4Kbits (512×8)

WRITE PROTECT (WP): The BL24C04F has a Write Protect pin that provides hardware data protection.

The Write Protect pin allows normal read/write operations when connected to ground (GND). When the

Write Protection pin is connected to Vcc, the write protection feature is enabled and operates as shown

in the following Table 2.

WP Pin Status

At VCC

At GND

BL24C04F

Full(4K)Array

Normal Read/Write Operations

Table 2

Functional Description

1. Memory Organization

BL24C04F, 4K SERIAL EEPROM: Internally organized with 32 pages of 16 bytes each, the 4K requires a 9-

bit data word address for random word addressing.

2. Device Operation

CLOCK and DATA TRANSITIONS: The SDA pin is normally pulled high with an external device. Data on the

SDA pin may change only during SCL low time periods (see Figure 2). Data changes during SCL high

periods will indicate a start or stop condition as defined below.

START CONDITION: A high-to-low transition of SDA with SCL high is a start condition which must precede

any other command (see Figure 3).

STOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition. After a read

sequence, the stop command will place the EEPROM in a standby power mode (see Figure 3).

ACKNOWLEDGE: All addresses and data words are serially transmitted to and from the EEPROM in 8-bit

words. The EEPROM sends a "0" to acknowledge that it has received each word. This happens during

the ninth clock cycle.

STANDBY MODE: The BL24C04F features a low-power standby mode which is enabled: (a) upon power-up

and (b) after the receipt of the STOP bit and the completion of any internal operations.

MEMORY RESET: After an interruption in protocol, power loss or system reset, any two-wire part can be

reset by following these steps:

1. Clock up to 9 cycles.

2. Look for SDA high in each cycle while SCL is high.

3. Create a start condition.

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BL24C04F 4Kbits (512×8)

SDA

SCL

DATA STABLE

DATA CHANGE

DATA STABLE

Figure 2. Data Validity

SDA

SCL

START

STOP

Figure 3. Start and Stop Definition

SCL189

DATA IN

DATA OUT

START

ACKNOWLEDGE

Figure 4. Output Acknowledge

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BL24C04F 4Kbits (512×8)

3. Device Addressing

The 4K EEPROM devices all require an 8-bit device address word following a start condition to enable

the chip for a read or write operation (see Figure 5)

MSB

1010A2A1B8

LSB

R/W

Figure 5. Device Address

The device address word consists of a mandatory "1", "0" sequence for the first four most significant

bits as shown. This is common to all the Serial EEPROM devices.

The 4K EEPROM uses A2 and A1 device address bits to allow as much as for devices on the same bus.

These 2 bits must be compared to their corresponding hardwired input pins. The A2 and A1 pins use an

internal proprietary circuit that biases them to a logic low condition if the pins are allowed to float.

The eighth bit of the device address is the read/write operation select bit. A read operation is initiated if

this bit is high and a write operation is initiated if this bit is low.

Upon a compare of the device address, the EEPROM will output a "0". If a compare is not made, the

chip will return to a standby state.

DATA SECURITY: The BL24C04F has a hardware data protection scheme that allows the user to write

protect the entire memory when the WP pin is at VCC.

4. Write Operations

BYTE WRITE: A write operation requires an 9-bit data word address following the device address word

and acknowledgment. Upon receipt of this address, the EEPROM will again respond with a "0" and then

clock in the first 8-bit data word. Following receipt of the 8-bit data word, the EEPROM will output a "0"

and the addressing device, such as a microcontroller, must terminate the write sequence with a stop

condition. At this time the EEPROM enters an internally timed write cycle, tWR, to the nonvolatile

memory. All inputs are disabled during this write cycle and the EEPROM will not respond until the write

is complete (see Figure 7).

MSB

1010A2A1B8

LSB

R/W

B7B6B5B4B3B2B1B0

Figure 6. ADDRESS

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BL24C04F 4Kbits (512×8)

S

T

A

R

T

SDA

LINE

M

S

B

DEVICE

ADDRESS

W

R

I

T

E

ADDRESSDATA

S

T

O

P

LRA

S/C

BWK

LA

SC

BK

LA

SC

BK

Figure 7. Byte Write

PAGE WRITE: The 4K EEPROM is capable of an 16-byte page write. A page write is initiated the same as

a byte write, but the microcontroller does not send a stop condition after the first data word is clocked

in. Instead, after the EEPROM acknowledges receipt of the first data word, the microcontroller can

transmit up to seven more data words. The EEPROM will respond with a "0" after each data word

received. The microcontroller must terminate the page write sequence with a stop condition (see

Figure 8).

S

T

A

R

T

SDA

LINE

M

S

B

LRA

S/C

BWK

LA

SC

BK

LA

SC

BK

A

C

K

A

C

K

DEVICE

ADDRESS

W

R

I

T

E

ADDRESSDATA(n)DATA(n+1)DATA(n+1)

S

T

O

P

Figure 8. Page Write

The data word address lower three bits are internally incremented following the receipt of each data

word. The higher data word address bits are not incremented, retaining the memory page row location.

When the word address, internally generated, reaches the page boundary, the following byte is placed

at the beginning of the same page. If more than eight data words are transmitted to the EEPROM, the

data word address will "roll over" and previous data will be overwritten.

ACKNOWLEDGE POLLING: Once the internally timed write cycle has started and the EEPROM inputs are

disabled, acknowledge polling can be initiated. This involves sending a start condition followed by the

device address word. The read/write bit is representative of the operation desired. Only if the internal

write cycle has completed will the EEPROM respond with a "0", allowing the read or write sequence to

continue.

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BL24C04F 4Kbits (512×8)

5. Read Operations

Read operations are initiated the same way as write operations with the exception that the

read/write select bit in the device address word is set to "1". There are three read operations: current

address read, random address read and sequential read.

CURRENT ADDRESS READ: The internal data word address counter maintains the last address accessed

during the last read or write operation, incremented by one. This address stays valid between

operations as long as the chip power is maintained. The address "roll over" during read is from the last

byte of the last memory page to the first byte of the first page. The address "roll over" during write is

from the last byte of the current page to the first byte of the same page. Once the device address with

the read/write select bit set to "1" is clocked in and acknowledged by the EEPROM, the current address

data word is serially clocked out. The microcontroller does not respond with an input "0" but does

generate a following stop condition (see Figure 9).

S

T

A

R

T

SDA

LINE

M

S

B

LRA

S/C

BWK

NO

ACK

DEVICE

ADDRESS

R

E

A

D

DATA

S

T

O

P

Figure 9. Current Address Read

RANDOM READ: A random read requires a "dummy" byte write sequence to load in the data word

address. Once the device address word and data word address are clocked in and acknowledged by the

EEPROM, the microcontroller must generate another start condition. The microcontroller now initiates a

current address read by sending a device address with the read/write select bit high. The EEPROM

acknowledges the device address and serially clocks out the data word. The microcontroller does not

respond with a "0" but does generate a following stop condition (see Figure 10)

S

T

A

R

T

SDA

LINE

M

S

B

LRA

S/C

BWK

LA

SC

BK

A

C

K

NO

ACK

W

R

I

T

E

S

T

A

R

T

DEVICE

ADDRESS

ADDRESS

DEVICE

ADDRESS

R

E

A

D

DATA(n)

S

T

O

P

DUMMY WRITE

Note.1*=DON'T CARE bits

Figure 10. Random Read

SEQUENTIAL READ: Sequential reads are initiated by either a current address read or a random address

read. After the microcontroller receives a data word, it responds with an acknowledge. As long as the

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BL24C04F 4Kbits (512×8)

EEPROM receives an acknowledge, it will continue to increment the data word address and serially

clock out sequential data words. When the memory address limit is reached, the data word address will

"roll over" and the sequential read will continue. The sequential read operation is terminated when the

microcontroller does not respond with a "0" but does generate a following stop condition (see Figure

11).

DEVICE

ADDRESS

SDA

LINE

R

E

A

D

DATA(n)DATA(n+1)DATA(n+2)DATA(n+x)

S

T

O

P

RA

/C

WK

A

C

K

A

C

K

A

C

K

NO

ACK

Figure 11. Sequential Read

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BL24C04F 4Kbits (512×8)

Electrical Characteristics

Absolute Maximum Stress Ratings：











DC Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6.5V

Input / Output Voltage . . . . . . . . . . . . . GND-0.3V to VCC+0.3V

Operating Ambient Temperature . . . . . . . . . . . . -40℃ to +85℃

Storage Temperature . . . . . . . . . . . . . . . . . . . . .-65℃ to +150℃

Electrostatic pulse (Human Body model) . . . . . . . . . . . . . 6000V

Comments:

Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to this

device. These are stress ratings only. Functional operation of this device at these or any other

conditions above those indicated in the operational sections of this specification is not implied or

intended. Exposure to the absolute maximum rating conditions for extended periods may affect device

reliability.

DC Electrical Characteristics

Applicable over recommended operating range from: TA = -40℃ to +85℃, VCC = +1.7V to +5.5V

(unless otherwise noted)

Parameter

Supply Voltage

Supply Current VCC=5.0V

Supply Current VCC=5.0V

Supply Current VCC=5.0V

Input Leakage Current

Output Leakage Current

Input Low Level

Input High Level

Output Low Level VCC=1.7V

Output Low Level VCC=5.0V

Pin Capacitance

Symbol

V

CC1

I

CC1

I

CC2

I

SB1

I

L1

I

LO

V

IL1

V

IH1

V

OL1

V

OL2

Min

1.7

-

-

-

-

-

-0.3

V

CC

×0.7

-

-

Typ

-

0.14

0.28

0.03

0.10

0.05

-

-

-

-

Max

5.5

0.3

0.5

0.5

1.0

1.0

V

CC

×0.3

V

CC

+0.3

0.2

0.4

Unit

V

mA

mA

μA

μA

μA

V

V

V

V

-

Condition

READ at 400KHZ

WRITE at 400KHZ

V

IN

=V

CC

or V

SS

V

IN

=V

CC

or V

SS

V

OUT

=V

CC

or V

SS

V

CC

=1.7V to 5.5V

V

CC

=1.7V to 5.5V

I

OL

=0.15mA

I

OL

=3.0mA

Table 3

Applicable over recommended operating range from TA = 25℃, f = 1.0 MHz, VCC = +1.7V

Parameter

Input/Output Capacitance(SDA)

Input Capacitance(A0,A1,A2,SCL)

Symbol

C

I/O

C

IN

Min

-

-

Typ

-

-

Max

8

6

Unit

pF

pF

Condition

V

IO

=0V

V

IN

=0V

Table 4

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BL24C04F 4Kbits (512×8)

AC Electrical Characteristics

Applicable over recommended operating range from TA = -40℃ to +85℃, VCC = +1.8V to +5.5V, CL =

1 TTL Gate and 100 pF (unless otherwise noted)

Parameter

Clock Frequency,SCL

Clock Pulse Width Low

Clock Pulse Width High

Noise Suppression Time

Clock Low to Data Out Valid

Time the bus must be free

before a new transmission can

start

Start Hold Time

Start Setup Time

Data In Hold Time

Data in Setup Time

Input Rise Time(1)

Input Fall Time(1)

Stop Setup Time

Data Out Hold Time

Write Cycle Time

5.0V,25℃,Byte Mode(1)

Symbol

f

SCL

t

LOW

t

HIGH

t

I

t

AA

t

BUF

t

HD:STA

t

SU:STA

t

HD:DAT

t

SU:DAT

t

R

t

F

t

Su:STO

t

DH

tw

R

1.7V≤V

CC

﹤2.5V

Min

-

1.3

0.6

-

-

1.3

0.6

0.6

0

100

-

-

0.6

50

-

Table 5

2.5V≤V

CC

﹤5.5V

Min

-

0.5

0.26

-

-

0.5

0.25

0.25

0

100

-

-

0.25

50

-

1M

Typ

-

-

-

-

-

-

-

-

-

-

-

-

-

-

1.9

-

Max

1000

-

-

50

0.45

-

-

-

-

-

0.12

0.12

-

-

3

-

Typ

-

-

-

-

-

-

-

-

-

-

-

-

-

-

1.9

-

Max

400

-

-

50

0.9

-

-

-

-

-

0.3

0.3

-

-

3

-

Units

kHz

μs

μs

ns

μs

μs

μs

μs

μs

ns

μs

μs

μs

ns

ms

Write Cycle

Endurance1M

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BL24C04F 4Kbits (512×8)

Bus Timing

t

F

SCL

t

t

LOW

t

t

t

t

t

HIGH

t

LOW

t

R

SDA_IN

t

AA

SDA_OUT

t

DH

t

BUF

Figure 12. SCL: Serial Clock, SDA: Serial Data I/O

Write Cycle Timing

SCL

ACK

SDA

Word n

tWR(1)

STOP

CONDITION

START

CONDITION

Figure 13. SCL: Serial Clock, SDA: Serial Data I/O

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Package Information

PDIP Outline Dimensions

E

E1

C

Top View

eA

End View

COMMON DIMENSIONS

(Unit of Measure=inches)

D1

D

e

A2A

B3

4PLCS

Side View

b2

b

L

SYMBOL

A

A2

b

b2

b3

c

D

D1

E

E1

e

eA

L

MIN

0.115

0.014

0.045

0.030

0.008

0.355

0.005

0.300

0.240

NOM

0.130

0.018

0.060

0.039

0.010

0.365

0.310

0.250

0.100BSC

0.300BSC

0.130

MAX

0.210

0.195

0.022

0.070

0.045

0.014

0.400

0.325

0.280

NOTE

2

5

6

6

3

3

4

3

4

20.1150.150

Figure 14

Notes:

drawing is for general information only; refer to JEDEC Drawing MS-001, Variation BA for additional

information.

2. Dimensions A and L are measured with the package seated in JEDEC seating plane Gauge GS-3.

3. D, D1 and E1 dimensions do not include mold Flash or protrusions. Mold Flash or protrusions shall not exceed

0.010 inch.

4. E and eA measured with the leads constrained to be perpendicular to datum.

5. Pointed or rounded lead tips are preferred to ease insertion.

6. b2 and b3 maximum dimensions do not include Dambar protrusions. Dambar protrusions shall not exceed 0.010

(0.25 mm).

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BL24C04F 4Kbits (512×8)

SOP

1

E

E1

N

Φ

L

COMMON DIMENSIONS

(Unit of Measure=mm)

e

B

A1

A

D

SYMBOL

A

A1

b

C

D

E1

E1

E1

L

Φ

MIN

1.35

0.10

0.31

0.17

4.80

3.81

5.79

0.40

0"

NOM

-

-

-

-

-

-

-

1.27BSC

-

-

MAX

1.75

0.25

0.51

0.25

5.00

3.99

6.20

1.27

8"

NOTE

Figure 15

Notes:

These drawings are for general information only. Refer to JEDEC Drawing MS-012, Variation AA for proper

dimensions, tolerances, datums, etc.

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BL24C04F 4Kbits (512×8)

TSSOP

321

E1E

L1

N

Top View

b

A

End View

L

COMMON DIMENSIONS

Unit of Measure=mm

SYMBOL

D

E

E1

A

A2

b

e

L

L1

MIN

2.90

4.30

-

0.80

0.19

0.45

NOMMAX

3.003.10

6.40BSC

4.404.50

-1.20

1.001.05

-0.30

0.65BSC

0.600.75

1.00REF

NOTE

2,5

3,5

e

A2

4

D

Side View

Figure 16

NOTES:

1. This drawing is for general information only. Refer to JEDEC Drawing MO-153, Variation AA, for proper

dimensions, tolerances, datums, etc.

2. Dimension D does not include mold Flash, protrusions or gate burrs. Mold Flash, protrusions and gate burrs shall

not exceed 0.15 mm (0.006 in) per side.

3. Dimension E1 does not include inter-lead Flash or protrusions. Inter-lead Flash and protrusions shall not exceed

0.25 mm (0.010 in) per side.

4. Dimension b does not include Dambar protrusion. Allowable Dambar protrusion shall be 0.08 mm total in excess

of the b dimension at maximum material condition. Dambar cannot be located on the lower radius of the foot.

Minimum space between protrusion and adjacent lead is 0.07 mm.

5. Dimension D and E1 to be determined at Datum Plane H.

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BL24C04F 4Kbits (512×8)

UDFN

D

D2

L

PIN 1 DOT

BY MARKING

E

E2

PIN #1 IDENTIFICATION

CHAMFER

TOP VIEW

b

e

BOTTOM VIEW

PKG

REF

A

A1

A3

D

E

b

L

D2

E2

e

Figure 17

A

A1

A3

SIDE VIEW

COMMON DIMENSION(MM)

UT:ULTRA THIN

MINNOMMAX

>0.500.550.60

0.00-0.05

0.15REF

1.952.002.05

2.953.003.05

0.200.250.30

0.200.300.40

1.251.401.50

1.151.301.40

0.50BSC

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BL24C04F 4Kbits (512×8)

TSOT23-5

D

e1

L2

R1

Θ1(4X)

R

L

(L1)

Θ2(4X)

E

E1

Θ

Pin 1

b

e

TOP VIEW

0.20

M

B

B

SIDE VIEW

COMMON DIMENSIONS

(UNITS OF MEASURE = MILLIMETER)

SYMBOL

A

A1

A2

A3

c

c1

D

E

E1

e

e1

L

L1

L2

R

R1

Θ

Θ1

Θ2

MIN

-

0.00

0.65

0.35

0.14

0.14

2.85

2.65

1.60

0.90

1.80

0.30

NOM

-

-

0.75

0.40

-

0.15

2.95

2.80

1.65

0.95

1.90

0.45

0.575REF

0.258BSC

-

-

-

5°

12°

MAX

0.90

0.15

0.85

0.45

0.20

0.16

3.05

2.95

1.70

1.00

2.00

0.60

A3

A

A2

0.10

SIDE VIEW

A1

-

-

0°

3°

10°

0.25

0.25

8°

7°

14°

Figure 18

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BL24C04F 4Kbits (512×8)

Marking Diagram

PDIP

BL24C04F

YYWW#ZZ

SSSSSP

YY: year

WW :week

ZZ: assembly house

SSSSS : Lot ID

SOP

BL24C04F

SSSSSP

SSSSS : Lot ID

TSSOP

BL24C04F

SSSSS

SSSSS : Lot ID

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BL24C04F 4Kbits (512×8)

TSOT23-5

24C04F

SSSSSP

SSSSS : Lot ID

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BL24C04F 4Kbits (512×8)

Ordering Information

BL24C04F- 1 2 3

Code Description

Package type

PA: SOP-8L

SF: TSSOP-8L

DA: PDIP-8L

1 NT: UDFN-8L

TC: SOT23-5L

RR: TSOT23-5L

MA: M2.2

MB: M3.2

Packing type

2 R: Tape and Reel

T: Tube

Feature

3 S: Standard (default, Pb Free RoHS Std.)

C: Green (Halogen Free)

Device

BL24C04F

BL24C04F

BL24C04F

BL24C04F

Package

SOP8

TSSOP8L

UDFN

SOT23-5

Shipping(Qty/Packing)

2500/Tape &Reel

3000/Tape &Reel

3000/Tape &Reel

3000/Tape &Reel

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BL24C04F 4Kbits (512×8)

Revision history

Version 1.00 BL24C04F

Initial vision

Version 1.01 BL24C04F 3/7/2017

Update the AC Electrical Characteristics

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