2024年6月4日发(作者：歧平乐)

Chapter1

Packaging Overview

About this Guide

Xilinx® 7 series FPGAs include four FPGA families that are all designed for lowest power to

enable a common design to scale across families for optimal power, performance, and cost.

The Spartan®-7 family is the lowest density with the lowest cost entry point into the

7 series portfolio. The Artix®-7 family is optimized for highest performance-per-watt and

bandwidth-per-watt for cost-sensitive, high-volume applications. The Kintex®-7 family is

an innovative class of FPGAs optimized for the best price-performance. The Virtex®-7

family is optimized for highest system performance and capacity.

This 7 series packaging and pinout product specification, part of an overall set of

documentation on the 7 series FPGAs, is available on the Xilinx website .

Introduction

This section describes the pinouts for the 7 series FPGAs in various fine pitch and flip-chip

1.0 mm pitch BGA packages, 0.8 mm and 0.5 mm pitch chip-scale packages, and 0.5 mm

pitch wire-bond lead frame packages.

Spartan-7, Artix-7, and Kintex-7 devices are offered in low-cost, space-saving packages that

are optimally designed for the maximum number of user I/Os.

Virtex-7 T and Virtex-7 XT devices are offered exclusively in high performance flip-chip BGA

packages that are optimally designed for improved signal integrity and jitter.

For pinout and packaging information on the Virtex-7 HT devices.

Package inductance is minimized as a result of optimal placement and even distribution

as well as an increased number of Power and GND pins.

The FFG, FLG, FHG, FBG, SBG, and RFG flip-chip packages marked with the Pb-free Character

on the upper right of the device are RoHS 6 of 6 compliant. The FFG, FLG, FHG, FBG, SBG, and

RFG flip-chip packages not marked with the Pb-free character are RoHS 6 of 6 compliant,

7 Series FPGAs Packaging

UG475 (v1.18) July 16, 2019

Chapter 1:Packaging Overview

Pin Definitions

Table1-12 lists the pin definitions used in 7series FPGAs packages.

Note:

There are dedicated general purpose user I/O pins listed separately in Table1-12. There are

also multi-function pins where the pin names start with either IO_LXXY_ZZZ_# or IO_XX_ZZZ_#,

where ZZZ represents one or more functions in addition to being general purpose user I/O. If not

used for their special function, these pins can be user I/O.

IMPORTANT:

For Tandem PROM configuration, the configuration PERSIST property is required. In this

case, a dual-purpose I/O that is used for stage 1 and stage 2 configuration cannot be repurposed as

user I/O after stage 2 configuration is complete.

7 Series FPGAs Packaging

UG475 (v1.18) July 16, 2019

2024年6月4日发(作者：歧平乐)

Chapter1

Packaging Overview

About this Guide

Xilinx® 7 series FPGAs include four FPGA families that are all designed for lowest power to

enable a common design to scale across families for optimal power, performance, and cost.

The Spartan®-7 family is the lowest density with the lowest cost entry point into the

7 series portfolio. The Artix®-7 family is optimized for highest performance-per-watt and

bandwidth-per-watt for cost-sensitive, high-volume applications. The Kintex®-7 family is

an innovative class of FPGAs optimized for the best price-performance. The Virtex®-7

family is optimized for highest system performance and capacity.

This 7 series packaging and pinout product specification, part of an overall set of

documentation on the 7 series FPGAs, is available on the Xilinx website .

Introduction

This section describes the pinouts for the 7 series FPGAs in various fine pitch and flip-chip

1.0 mm pitch BGA packages, 0.8 mm and 0.5 mm pitch chip-scale packages, and 0.5 mm

pitch wire-bond lead frame packages.

Spartan-7, Artix-7, and Kintex-7 devices are offered in low-cost, space-saving packages that

are optimally designed for the maximum number of user I/Os.

Virtex-7 T and Virtex-7 XT devices are offered exclusively in high performance flip-chip BGA

packages that are optimally designed for improved signal integrity and jitter.

For pinout and packaging information on the Virtex-7 HT devices.

Package inductance is minimized as a result of optimal placement and even distribution

as well as an increased number of Power and GND pins.

The FFG, FLG, FHG, FBG, SBG, and RFG flip-chip packages marked with the Pb-free Character

on the upper right of the device are RoHS 6 of 6 compliant. The FFG, FLG, FHG, FBG, SBG, and

RFG flip-chip packages not marked with the Pb-free character are RoHS 6 of 6 compliant,

7 Series FPGAs Packaging

UG475 (v1.18) July 16, 2019

Chapter 1:Packaging Overview

Pin Definitions

Table1-12 lists the pin definitions used in 7series FPGAs packages.

Note:

There are dedicated general purpose user I/O pins listed separately in Table1-12. There are

also multi-function pins where the pin names start with either IO_LXXY_ZZZ_# or IO_XX_ZZZ_#,

where ZZZ represents one or more functions in addition to being general purpose user I/O. If not

used for their special function, these pins can be user I/O.

IMPORTANT:

For Tandem PROM configuration, the configuration PERSIST property is required. In this

case, a dual-purpose I/O that is used for stage 1 and stage 2 configuration cannot be repurposed as

user I/O after stage 2 configuration is complete.

7 Series FPGAs Packaging

UG475 (v1.18) July 16, 2019