2024年7月16日发(作者：宇柔谨)
■
■
■
■
On-chip series termination without calibration
On-chip parallel termination with calibration (OCT R
T
)
On-chip differential termination (OCT R
D
)
PCI clamping diode
The I/O registers are composed of the input path for handling data from the pin to the
core, the output path for handling data from the core to the pin, and the output-enable
(OE) path for handling the OE signal for the output buffer. These registers allow faster
source-synchronous register-to-register transfers and resynchronization. The input
path consists of the DDR input registers, alignment and synchronization registers,
and HDR. You can bypass each block of the input path.
Figure7–7 shows the StratixIII IOE structure.
Figure7– Structure for Stratix III Devices(Note1), (2)
Firm Core
DQS Logic Block
OE Register
PRN
DQ
D5_OCT
D6_OCT
Dynamic OCT Control
(2)
OE
from
Core
2
Half Data
Rate Block
Alignment
Registers
OE Register
PRN
DQ
D5, D6
Delay
V
CCIO
V
CCIO
PCI Clamp
Programmable
Pull-Up Resistor
Write
Data
from
Core
Output Register
4
Half Data
Rate Block
Alignment
Registers
PRN
DQ
Programmable
Current
Strength and
Slew Rate
Control
D5, D6
Delay
From OCT
Calibration
Block
Output Buffer
On-Chip
Termination
Output Register
D
PRN
Q
Open Drain
D2 Delay
D3_0
Delay
Input Buffer
clkout
To
Core
To
Core
D3_1
Delay
D1
Delay
Bus-Hold
Circuit
Input Register
PRN
DQ
Read
Data
to
Core
4
Half Data
Rate Block
Alignment and
Synchronization
Registers
Input Register
PRN
DQ
Input Register
PRN
DQ
DQS
CQn
clkin
D4 Delay
Notes to Figure7–7:
(1)
D3_0 and D3_1
delays have the same available settings in the Quartus
®
II software.
(2)One dynamic OCT control is available per DQ/DQS group.
The output and OE paths are divided into output or OE registers, alignment registers,
and HDR blocks. You can bypass each block of the output and OE path.
fFor more information about I/O registers and how they are used for memory
applications, refer to the External Memory Interfaces in StratixIII Devices chapter.
Stratix III Device Handbook, Volume 1
Chapter 7:StratixIII Device I/O Features
StratixIII I/O Structure
Stratix III Device Handbook, Volume 1
Chapter 7:StratixIII Device I/O Features
StratixIII I/O Structure
Programmable Differential Output Voltage
StratixIII LVDS transmitters support programmable V
OD
. The programmable V
OD
settings enable you to adjust output eye height to optimize for trace length and power
consumption. A higher V
OD
swing improves voltage margins at the receiver end while
a smaller V
OD
swing reduces power consumption. The QuartusII software allows four
settings for programmable V
OD
—low, medium low, medium high, and high. The
default setting is medium low.
fFor more information about programmable V
OD
, refer to the High Speed Differential I/O
Interfaces with DPA inthe StratixIII Devices chapter.
MultiVolt I/O Interface
The StratixIII architecture supports the MultiVolt
TM
I/O interface feature that allows
StratixIII devices in all packages to interface with systems of different supply
voltages.
You can connect the V
CCIO
pins to a 1.2-, 1.5-, 1.8-, 2.5-, 3.0 or 3.3-V power supply,
depending on the output requirements. The output levels are compatible with
systems of the same voltage as the power supply. (For example, when V
CCIO
pins are
connected to a 1.5-V power supply, the output levels are compatible with 1.5-V
systems.)
You must connect the StratixIII VCCPD power pins to a 2.5-, 3.0 or 3.3-V power supply.
Using these power pins to supply the pre-driver power to the output buffers increases
the performance of the output pins. Table7–7 summarizes StratixIII MultiVolt I/O
support.
1For V
CCIO
= 3.3 V, V
CCPD
=3.3 V. For V
CCIO
= 3.0 V, V
CCPD
= 3.0 V. For V
CCIO
= 2.5 V or less,
V
CCPD
= 2.5 V.
Table7–olt I/O Support for Stratix III Devices(Note1), (2)
Input Signal (V)
V
CCIO
(V)
1.2
1.5
1.8
2.5
3.0
3.3
1.2
v
—
—
—
—
—
1.5
—
v
v
—
—
—
1.8
—
v (1)
v
—
—
—
2.5
—
—
—
v
v
v
3.0
—
—
—
v (2)
v
v
3.3
—
—
—
v (2)
v
v
1.2
v
—
—
—
—
—
1.5
—
v
—
—
—
—
Output Signal (V)
1.8
—
—
v
—
—
—
2.5
—
—
—
v
—
—
3.0
—
—
—
—
v
—
3.3
—
—
—
—
—
v
Notes to Table7–7:
(1)The pin current may be slightly higher than the default value. You must verify that the driving device’s V
OL
maximum and V
OH
minimum voltages
do not violate the applicable StratixIII V
IL
maximum and V
IH
minimum voltage specifications.
(2)Use on-chip PCI clamp diode for column I/Os or external PCI clamp diode for row I/Os to protect the input pins against overshoot voltage.
(3)Each I/O bank of a Stratix III device has its own VCCIO pins and supports only one V
ccio
, either 1.2, 1.5, 1.8, or 3.0V. The LVDS I/O standard
requires that a V
CCIO
of 2.5V cannot be assigned in a same bank with a 3.0-V or 3.3-V output signal.
Stratix III Device Handbook, Volume 1
Chapter 7:StratixIII Device I/O Features
OCT Support
Dynamic OCT
StratixIII devices support on-off dynamic series and parallel termination for a
bi-directional I/O in all I/O banks. Figure7–11 shows the termination schemes
supported in the StratixIII device. Dynamic parallel termination is enabled only
when the bi-directional I/O acts as a receiver and is disabled when it acts as a driver.
Similarly, dynamic series termination is enabled only when the bi-directional I/O acts
as a driver and is disabled when it acts as a receiver. This feature is useful for
terminating any high-performance bi-directional path because the signal integrity is
optimized depending on the direction of the data.
You should connect a bi-directional pin that uses both 25-Ω or 50-Ω series termination
and 50-Ω input termination to a calibration block that has a 50-Ω external resistor
connected to its RUP
and RDN pins. The 25-Ω series termination on the bi-directional
pin is achieved through internal divide by two circuits.
Figure7–c Parallel OCT in StratixIII Devices
V
CCIO
Transmitter
100
50
100
Z
O
= 50
100
50
V
CCIO
100
Receiver
GND
Stratix III OCT
GND
Stratix III OCT
Receiver
50
V
CCIO
100
Z
O
= 50
100
100
100
VCCIO
50
GND
GND
Stratix III OCT
Transmitter
Stratix III OCT
fFor more information about tolerance specifications for OCT with calibration, refer to
the DC and Switching Characteristics of StratixIII Devices chapter.
Stratix III Device Handbook, Volume 1
Chapter 7:StratixIII Device I/O Features
OCT Support
LVDS Input On-Chip Termination (R
D
)
StratixIII devices support OCT for differential LVDS input buffers with a nominal
resistance value of 10Ω, as shown in Figure7–12. You can enable OCTR
D
in row I/O
banks when V
CCIO
and V
CCPD
are set to 2.5V. The column I/O banks do not support
OCT R
D.
The dedicated clock input pairs CLK[1,3,8,10][p,n],
PLL_L[1,4]_CLK[p,n], and PLL_R[1,4]_CLK[p,n] on the row I/O banks of the
StratixIII devices do not support OCT R
D
. Dedicated clock input pairs
CLK[0,2,9,11][p,n] on row I/O banks support OCT R
D
. Dedicated clock input pairs
CLK[4,5,6,7][p,n] and CLK[12,13,14,15][p,n] on column I/O banks do not
support OCT R
D
.
Figure7–ential Input On-Chip Termination
Transmitter
Receiver
Z
O
= 50 Ω
Z
O
= 50 Ω
100 Ω
fFor more information about OCT R
D
, refer to the High Speed Differential I/O Interfaces
with DPA in StratixIII Devices chapter.
Table7–11 lists the assignment name and its value for OCT R
D
in the QuartusII
software Assignment Editor.
1You must set the V
CCIO
to 2.5V when OCT R
D
is used for the LVDS input buffer, even if
the LVDS input buffer is powered by V
CCPD
.
Table7–-Chip Differential Termination in QuartusII Software Assignment Editor
Assignment NameAllowed Values
Parallel 50Ω with calibration
Input Termination (Accepts wildcards/groups)
Differential
Series 25Ω without
calibration
Series 50Ω without
calibration
Output Termination
Series 25Ω with calibration
Series 40Ω with calibration
Series 50Ω with calibration
Series 60Ω with calibration
Output buffers for
single-ended LVTTL/LVCMOS
and HSTL/SSTL standards as
well as differential HSTL/SSTL
standards.
Applies To
Input buffers for single-ended
and differential-HSTL/SSTL
standards
Input buffers for LVDS
receivers on row I/O banks.
Stratix III Device Handbook, Volume 1
2024年7月16日发(作者：宇柔谨)
■
■
■
■
On-chip series termination without calibration
On-chip parallel termination with calibration (OCT R
T
)
On-chip differential termination (OCT R
D
)
PCI clamping diode
The I/O registers are composed of the input path for handling data from the pin to the
core, the output path for handling data from the core to the pin, and the output-enable
(OE) path for handling the OE signal for the output buffer. These registers allow faster
source-synchronous register-to-register transfers and resynchronization. The input
path consists of the DDR input registers, alignment and synchronization registers,
and HDR. You can bypass each block of the input path.
Figure7–7 shows the StratixIII IOE structure.
Figure7– Structure for Stratix III Devices(Note1), (2)
Firm Core
DQS Logic Block
OE Register
PRN
DQ
D5_OCT
D6_OCT
Dynamic OCT Control
(2)
OE
from
Core
2
Half Data
Rate Block
Alignment
Registers
OE Register
PRN
DQ
D5, D6
Delay
V
CCIO
V
CCIO
PCI Clamp
Programmable
Pull-Up Resistor
Write
Data
from
Core
Output Register
4
Half Data
Rate Block
Alignment
Registers
PRN
DQ
Programmable
Current
Strength and
Slew Rate
Control
D5, D6
Delay
From OCT
Calibration
Block
Output Buffer
On-Chip
Termination
Output Register
D
PRN
Q
Open Drain
D2 Delay
D3_0
Delay
Input Buffer
clkout
To
Core
To
Core
D3_1
Delay
D1
Delay
Bus-Hold
Circuit
Input Register
PRN
DQ
Read
Data
to
Core
4
Half Data
Rate Block
Alignment and
Synchronization
Registers
Input Register
PRN
DQ
Input Register
PRN
DQ
DQS
CQn
clkin
D4 Delay
Notes to Figure7–7:
(1)
D3_0 and D3_1
delays have the same available settings in the Quartus
®
II software.
(2)One dynamic OCT control is available per DQ/DQS group.
The output and OE paths are divided into output or OE registers, alignment registers,
and HDR blocks. You can bypass each block of the output and OE path.
fFor more information about I/O registers and how they are used for memory
applications, refer to the External Memory Interfaces in StratixIII Devices chapter.
Stratix III Device Handbook, Volume 1
Chapter 7:StratixIII Device I/O Features
StratixIII I/O Structure
Stratix III Device Handbook, Volume 1
Chapter 7:StratixIII Device I/O Features
StratixIII I/O Structure
Programmable Differential Output Voltage
StratixIII LVDS transmitters support programmable V
OD
. The programmable V
OD
settings enable you to adjust output eye height to optimize for trace length and power
consumption. A higher V
OD
swing improves voltage margins at the receiver end while
a smaller V
OD
swing reduces power consumption. The QuartusII software allows four
settings for programmable V
OD
—low, medium low, medium high, and high. The
default setting is medium low.
fFor more information about programmable V
OD
, refer to the High Speed Differential I/O
Interfaces with DPA inthe StratixIII Devices chapter.
MultiVolt I/O Interface
The StratixIII architecture supports the MultiVolt
TM
I/O interface feature that allows
StratixIII devices in all packages to interface with systems of different supply
voltages.
You can connect the V
CCIO
pins to a 1.2-, 1.5-, 1.8-, 2.5-, 3.0 or 3.3-V power supply,
depending on the output requirements. The output levels are compatible with
systems of the same voltage as the power supply. (For example, when V
CCIO
pins are
connected to a 1.5-V power supply, the output levels are compatible with 1.5-V
systems.)
You must connect the StratixIII VCCPD power pins to a 2.5-, 3.0 or 3.3-V power supply.
Using these power pins to supply the pre-driver power to the output buffers increases
the performance of the output pins. Table7–7 summarizes StratixIII MultiVolt I/O
support.
1For V
CCIO
= 3.3 V, V
CCPD
=3.3 V. For V
CCIO
= 3.0 V, V
CCPD
= 3.0 V. For V
CCIO
= 2.5 V or less,
V
CCPD
= 2.5 V.
Table7–olt I/O Support for Stratix III Devices(Note1), (2)
Input Signal (V)
V
CCIO
(V)
1.2
1.5
1.8
2.5
3.0
3.3
1.2
v
—
—
—
—
—
1.5
—
v
v
—
—
—
1.8
—
v (1)
v
—
—
—
2.5
—
—
—
v
v
v
3.0
—
—
—
v (2)
v
v
3.3
—
—
—
v (2)
v
v
1.2
v
—
—
—
—
—
1.5
—
v
—
—
—
—
Output Signal (V)
1.8
—
—
v
—
—
—
2.5
—
—
—
v
—
—
3.0
—
—
—
—
v
—
3.3
—
—
—
—
—
v
Notes to Table7–7:
(1)The pin current may be slightly higher than the default value. You must verify that the driving device’s V
OL
maximum and V
OH
minimum voltages
do not violate the applicable StratixIII V
IL
maximum and V
IH
minimum voltage specifications.
(2)Use on-chip PCI clamp diode for column I/Os or external PCI clamp diode for row I/Os to protect the input pins against overshoot voltage.
(3)Each I/O bank of a Stratix III device has its own VCCIO pins and supports only one V
ccio
, either 1.2, 1.5, 1.8, or 3.0V. The LVDS I/O standard
requires that a V
CCIO
of 2.5V cannot be assigned in a same bank with a 3.0-V or 3.3-V output signal.
Stratix III Device Handbook, Volume 1
Chapter 7:StratixIII Device I/O Features
OCT Support
Dynamic OCT
StratixIII devices support on-off dynamic series and parallel termination for a
bi-directional I/O in all I/O banks. Figure7–11 shows the termination schemes
supported in the StratixIII device. Dynamic parallel termination is enabled only
when the bi-directional I/O acts as a receiver and is disabled when it acts as a driver.
Similarly, dynamic series termination is enabled only when the bi-directional I/O acts
as a driver and is disabled when it acts as a receiver. This feature is useful for
terminating any high-performance bi-directional path because the signal integrity is
optimized depending on the direction of the data.
You should connect a bi-directional pin that uses both 25-Ω or 50-Ω series termination
and 50-Ω input termination to a calibration block that has a 50-Ω external resistor
connected to its RUP
and RDN pins. The 25-Ω series termination on the bi-directional
pin is achieved through internal divide by two circuits.
Figure7–c Parallel OCT in StratixIII Devices
V
CCIO
Transmitter
100
50
100
Z
O
= 50
100
50
V
CCIO
100
Receiver
GND
Stratix III OCT
GND
Stratix III OCT
Receiver
50
V
CCIO
100
Z
O
= 50
100
100
100
VCCIO
50
GND
GND
Stratix III OCT
Transmitter
Stratix III OCT
fFor more information about tolerance specifications for OCT with calibration, refer to
the DC and Switching Characteristics of StratixIII Devices chapter.
Stratix III Device Handbook, Volume 1
Chapter 7:StratixIII Device I/O Features
OCT Support
LVDS Input On-Chip Termination (R
D
)
StratixIII devices support OCT for differential LVDS input buffers with a nominal
resistance value of 10Ω, as shown in Figure7–12. You can enable OCTR
D
in row I/O
banks when V
CCIO
and V
CCPD
are set to 2.5V. The column I/O banks do not support
OCT R
D.
The dedicated clock input pairs CLK[1,3,8,10][p,n],
PLL_L[1,4]_CLK[p,n], and PLL_R[1,4]_CLK[p,n] on the row I/O banks of the
StratixIII devices do not support OCT R
D
. Dedicated clock input pairs
CLK[0,2,9,11][p,n] on row I/O banks support OCT R
D
. Dedicated clock input pairs
CLK[4,5,6,7][p,n] and CLK[12,13,14,15][p,n] on column I/O banks do not
support OCT R
D
.
Figure7–ential Input On-Chip Termination
Transmitter
Receiver
Z
O
= 50 Ω
Z
O
= 50 Ω
100 Ω
fFor more information about OCT R
D
, refer to the High Speed Differential I/O Interfaces
with DPA in StratixIII Devices chapter.
Table7–11 lists the assignment name and its value for OCT R
D
in the QuartusII
software Assignment Editor.
1You must set the V
CCIO
to 2.5V when OCT R
D
is used for the LVDS input buffer, even if
the LVDS input buffer is powered by V
CCPD
.
Table7–-Chip Differential Termination in QuartusII Software Assignment Editor
Assignment NameAllowed Values
Parallel 50Ω with calibration
Input Termination (Accepts wildcards/groups)
Differential
Series 25Ω without
calibration
Series 50Ω without
calibration
Output Termination
Series 25Ω with calibration
Series 40Ω with calibration
Series 50Ω with calibration
Series 60Ω with calibration
Output buffers for
single-ended LVTTL/LVCMOS
and HSTL/SSTL standards as
well as differential HSTL/SSTL
standards.
Applies To
Input buffers for single-ended
and differential-HSTL/SSTL
standards
Input buffers for LVDS
receivers on row I/O banks.
Stratix III Device Handbook, Volume 1