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HD74LV4053ARPEL中文资料

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2024年9月9日发(作者:宝梓柔)

元器件交易网

HD74LV4053A

Triple 2-channel Analog Multiplexer / Demultiplexer

REJ03D0339–0300Z

(Previous ADE-205-284A (Z))

Rev.3.00

Jul. 21, 2004

Description

The HD74LV4053A handles both analog and digital signals, and enables signals of either type with amplitudes of up to

5.5 V (peak) to be transmitted in either direction (at V

CC

= 0 V to 5.5 V).

Applications include signal gating, chopping, modulation or demodulation (modem), and signal multiplexing for

analog-to-digital and digital-to-analog conversion systems.

Features

• V

CC

= 2.0 V to 5.5 V operation

• All control inputs V

IH

(Max.) = 5.5 V (@V

CC

= 0 V to 5.5 V)

• Ordering Information

Part Name

HD74LV4053AFPEL

HD74LV4053ARPEL

HD74LV4053ATELL

Package Type

SOP–16 pin (JEITA)

SOP–16 pin (JEDEC)

TSSOP–16 pin

Package Code

FP–16DAV

FP–16DNV

TTP–16DAV

Package

Abbreviation

FP

RP

T

Taping Abbreviation

(Quantity)

EL (2,000 pcs/reel)

EL (2,500 pcs/reel)

ELL (2,000 pcs/reel)

Note: Please consult the sales office for the above package availability.

Function Table

Inputs

INH

L

L

L

L

L

L

L

L

H

Note:H:High level

L:Low level

X:Immaterial

C

L

L

L

L

H

H

H

H

X

B

L

L

H

H

L

L

H

H

X

A

L

H

L

H

L

H

L

H

X

On Channel

1Y0, 2Y0, 3Y0

1Y1, 2Y0, 3Y0

1Y0, 2Y1, 3Y0

1Y1, 2Y1, 3Y0

1Y0, 2Y0, 3Y1

1Y1, 2Y0, 3Y1

1Y0, 2Y1, 3Y1

1Y1, 2Y1, 3Y1

NONE

Rev.3.00 Jul. 21, 2004 page 1 of 12

元器件交易网

HD74LV4053A

Pin Arrangement

2Y1

1

2Y0

3Y1

2

3

16

V

CC

15

2−COM

14

1−COM

13

1Y1

12

1Y0

11

A

10

B

9

C

3−COM

4

3Y0

INH

GND

GND

5

6

7

8

(Top view)

Absolute Maximum Ratings

Item

Supply voltage range

Input voltage range*

1

Output voltage range*

1, 2

Input clamp current

Output clamp current

Continuous output current

Continuous current through

V

CC

or GND

Maximum power dissipation at

Ta = 25°C (in still air)*

3

Storage temperature

Symbol

V

CC

V

I

V

O

I

IK

I

OK

I

O

I

CC

or

I

GND

P

T

Tstg

Ratings

–0.5 to 7.0

–0.5 to 7.0

–0.5 to V

CC

+ 0.5

–20

±50

±25

±50

785

500

–65 to 150

Unit

V

V

V

mA

mA

mA

mA

mW

°C

Conditions

Output: H or L

V

I

< 0

V

O

< 0 or V

O

> V

CC

V

O

= 0 to V

CC

SOP

TSSOP

Notes:The absolute maximum ratings are values, which must not individually be exceeded, and furthermore, no two of

which may be realized at the same time.

input and output voltage ratings may be exceeded even if the input and output clamp-current ratings are

observed.

value is limited to 5.5 V maximum.

maximum package power dissipation was calculated using a junction temperature of 150°C.

Rev.3.00 Jul. 21, 2004 page 2 of 12

元器件交易网

HD74LV4053A

Recommended Operating Conditions

Item

Supply voltage range

Input voltage range

Output voltage range

Input transition rise or fall rate

Symbol

V

CC

V

I

V

I/O

∆t /∆v

Min

2.0*

0

0

0

0

0

–40

1

Max

5.5

5.5

V

CC

200

100

20

85

Unit

V

V

V

ns/V

Conditions

V

CC

= 2.3 to 2.7 V

V

CC

= 3.0 to 3.6 V

V

CC

= 4.5 to 5.5 V

Operating free-air temperatureTa°C

Notes:Unused or floating control inputs must be held high or low.

the supply voltage at or around 2 V, the analog switch on-state resistance loses linearity significantly. It

is recommended that only digital signals be transmitted at these low supply voltages.

Logic Diagram

2−COM

1−COM

A

1Y0

1Y1

B

2Y0

2Y1

C

3Y0

3Y1

INH

3−COM

Rev.3.00 Jul. 21, 2004 page 3 of 12

元器件交易网

HD74LV4053A

DC Electrical Characteristics

Ta = 25°C

Item

Input voltage

Symbol

V

IH

V

CC

(V)

2.0

2.3 to 2.7

3.0 to 3.6

4.5 to 5.5

2.0

2.3 to 2.7

3.0 to 3.6

4.5 to 5.5

2.3

3.0

4.5

2.3

3.0

4.5

2.3

3.0

4.5

5.5

Min

Typ

60

50

40

200

90

50

20

10

7

Max

180

150

75

500

180

100

30

20

15

±0.1

Ta = –40 to 85°C

Min

1.5

V

CC

× 0.7

V

CC

× 0.7

V

CC

× 0.7

Max

0.5

V

CC

× 0.3

V

CC

× 0.3

V

CC

× 0.3

225

190

100

600

225

125

40

30

20

±1.0

Unit

V

Test Conditions

Control input only

V

IL

On-state switch

resistance

Peak on resistance

R

ON

ΩV

IN

= V

CC

or GND

V

INH

= V

IL

I

T

= 2 mA

V

IN

= V

CC

to GND

V

INH

= V

IL

I

T

= 2 mA

V

IN

= V

CC

to GND

V

INH

= V

IL

I

T

= 2 mA

V

IN

= V

CC

,

V

OUT

= GND or

V

IN

= GND,

V

O

= V

CC

,V

INH

= V

IH

V

IN

= V

CC

or GND

V

INH

= V

IL

V

IN

= 5.5 V or GND

V

IN

= V

CC

or GND

R

ON (P)

Difference of on-state

resistance between

switches

Off-state switch

leakage current

∆R

ON

Is (OFF)µA

On-state switch

leakage current

Input current

Quiescent supply

current

Is (ON)

I

IN

I

CC

5.5

0 to 5.5

5.5

±0.1

±0.1

±1.0

±1.0

20

µA

µA

µA

Note:For conditions shown as Min or Max, use the appropriate values under recommended operating conditions.

Rev.3.00 Jul. 21, 2004 page 4 of 12

元器件交易网

HD74LV4053A

Switching Characteristics

V

CC

= 2.5 ± 0.2 V

Ta = 25°C

Item

Propagation

delay time

Enable time

Disable time

Symbol

t

PLH

t

PHL

t

ZH

t

ZL

t

HZ

t

LZ

Min

Typ

2.5

5.0

7.0

9.0

9.0

13.0

Max

10.0

12.0

18.0

28.0

18.0

28.0

Ta = –40 to 85°C

Min

Max

16.0

18.0

23.0

35.0

23.0

35.0

Unit

ns

ns

ns

Test Conditions

C

L

= 15 pF

C

L

= 50 pF

R

L

= 1 kΩ

R

L

= 1 kΩ

C

L

= 15 pF

C

L

= 50 pF

C

L

= 15 pF

C

L

= 50 pF

FROM

(Input)

COM

or Yn

INH

INH

TO

(Output)

Yn or

COM

COM or

Yn

COM or

Yn

V

CC

= 3.3 ± 0.3 V

Ta = 25°C

Item

Propagation

delay time

Enable time

Disable time

Symbol

t

PLH

t

PHL

t

ZH

t

ZL

t

HZ

t

LZ

Min

Typ

2.0

4.0

5.0

7.0

7.0

10.0

Max

6.0

9.0

12.0

20.0

12.0

20.0

Ta = –40 to 85°C

Min

Max

10.0

12.0

15.0

25.0

15.0

25.0

Unit

ns

ns

ns

Test Conditions

C

L

= 15 pF

C

L

= 50 pF

R

L

= 1 kΩ

R

L

= 1 kΩ

C

L

= 15 pF

C

L

= 50 pF

C

L

= 15 pF

C

L

= 50 pF

FROM

(Input)

COM

or Yn

INH

INH

TO

(Output)

Yn or

COM

COM or

Yn

COM or

Yn

V

CC

= 5.0 ± 0.5 V

Ta = 25°C

Item

Propagation

delay time

Enable time

Disable time

Symbol

t

PLH

t

PHL

t

ZH

t

ZL

t

HZ

t

LZ

Min

Typ

1.5

3.0

4.0

5.0

5.0

8.0

Max

4.0

6.0

8.0

14.0

8.0

14.0

Ta = –40 to 85°C

Min

Max

7.0

8.0

10.0

18.0

10.0

18.0

Unit

ns

ns

ns

Test Conditions

C

L

= 15 pF

C

L

= 50 pF

R

L

= 1 kΩ

R

L

= 1 kΩ

C

L

= 15 pF

C

L

= 50 pF

C

L

= 15 pF

C

L

= 50 pF

FROM

(Input)

COM

or Yn

INH

INH

TO

(Output)

Yn or

COM

COM or

Yn

COM or

Yn

Rev.3.00 Jul. 21, 2004 page 5 of 12

元器件交易网

HD74LV4053A

Switching Characteristics (cont.)

Ta = 25°C

Item

Control input

capacitance

Common

terminal

capacitance

Symbol

V

CC

(V)

Min

C

IC

C

IS

Typ

4.5

12.5

Max

Unit

pF

pF

Test Conditions

FROMTO

(Input)(Output)

Switch terminalC

I/O

capacitance

Feedthrough

capacitance

Power

dissipation

capacitance

Frequency

response

(Switch ON)

C

T

C

PD

7.0

0.5

9.0

pF

pF

pF

2.3

3.0

4.5

30.0

35.0

50.0

MHz

Crosstalk

(Between any

switches)

Crosstalk

(Control input

to signal

output)

Feedthrough

attenuation

(Switch OFF)

Sine-wave

distortion

2.3

3.0

4.5

2.3

3.0

4.5

2.3

3.0

4.5

2.3

3.0

4.5

–45.0—

–45.0—

–45.0—

20.0

35.0

65.0

–45

–45

–45

0.1

0.1

0.1

dB

mV

dB

C

L

= 50 pF, R

L

= 600 Ω

Adjust f

in

voltage to obtain 0 dBm

at output when f

in

is 1 MHz (sine

wave). Increase f

in

frequency

until the dB-meter reads –3 dBm.

20 log (V

O

/V

I

) = –3 dBm

C

L

= 50 pF, R

L

= 600 Ω

Adjust f

in

voltage to obtain 0 dBm

at input when f

in

is 1 MHz

(sine wave).

C

L

= 50 pF, R

L

= 600 Ω

Adjust R

L

value to obtain 0 A at

I

IN/OUT

when f

in

is 1 MHz

(square wave).

C

L

= 50 pF, R

L

= 600 Ω

Adjust f

in

voltage to obtain 0 dBm

at input when f

in

is 1 MHz

(sine wave).

C

L

= 50 pF, R

L

= 10 kΩ

f

IN

= 1 kHz (sine wave)

V

I

= 2 V

P-P

, V

CC

= 2.3 V

V

I

= 2.5 V

P-P

, V

CC

= 3.0 V

V

I

= 4 V

P-P

, V

CC

= 4.5 V

COM

or Yn

Yn or

COM

COMYn

INHCOM or

Yn

COM

or Yn

Yn or

COM

%

COM

or Yn

Yn or

COM

Rev.3.00 Jul. 21, 2004 page 6 of 12

元器件交易网

HD74LV4053A

Test Circuits

R : On-state switch resistance

ON

V

CC

V = V

INHIL

V

CC

V = V or GND

INCC

(ON)

GND

V

OUT

V

IN

−V

OUT

2 × 10

−3

R =

ON

2.0 mA

V

V

IN

−V

OUT

(Ω)

Is (OFF): Off-state switch leakage current, Is (ON): On-state switch leakage current

V

CC

V = V

INHIH

V

CC

AA

(OFF)

GND

B

V = V

INHIL

V

CC

V

CC

A

A

(ON)

GND

B

Open

Rev.3.00 Jul. 21, 2004 page 7 of 12

元器件交易网

HD74LV4053A

t , t : Propagation delay time (from switch input to switch output)

PLHPHL

V

CC

V = V

INHIL

V

CC

A

R =

L

50

(ON)

GND

B

C = 15 or

L

50 pF

Switching time

V

CC

R =

L

50

V

INH

S1

V

IN

V

CC

GND

V

OUT

R =

L

1 k

S2

C = 15 or

L

50 pF

TEST

t /t

LZZL

t /t

HZZH

V

CC

V

INH

50%

V

CC

t

ZL

V

OUT

50%

V

CC

V

OL

0 V

≈V

CC

V

OUT

V

INH

S1

GND

V

CC

S2

V

CC

GND

V

CC

50%

V

CC

t

ZH

50%

V

CC

≈0 V

0 V

V

OH

V

CC

V

INH

50%

V

CC

t

LZ

V

OUT

V

OL

+0.3 V

V

OL

0 V

≈V

CC

V

OUT

V

INH

50%

V

CC

t

HZ

V

OH

−0.3 V

V

CC

0 V

V

OH

≈0 V

Rev.3.00 Jul. 21, 2004 page 8 of 12

元器件交易网

HD74LV4053A

Frequency response (Switch ON)

V

CC

V = V

ILINH

0.1 µF

V

IN

R =

L

50

V

CC

(ON)

GND

V

OUT

R =

L

600

V /2

CC

C = 50 pF

L

f = sine wave

in

f

in

Crosstalk (Between any switches)

V = GND

INH

V =V

CCC

or GND

f

in

R =

L

0.1 µF

600

R =

L

50

V

IN

V

CC

V

CC

(ON)

GND

V

OUT1

R =

L

600

V /2

CC

C = 50 pF

L

V = GND

INH

V =V

CCC

or GND

V

CC

V

CC

R =

L

600

V /2

CC

(OFF)

GND

V

OUT2

R =

L

600

V /2

CC

C = 50 pF

L

Rev.3.00 Jul. 21, 2004 page 9 of 12

元器件交易网

HD74LV4053A

Crosstalk (Control input to signal output)

V

CC

R =

L

50

V

INH

V

CC

V

OUT

R =

L

600

V /2

CC

Feedthrough attenuation (Switch OFF)

V

CC

V = V

IH

INH

R =

L

0.1 µF

600

R =

L

50

V

IN

R =

L

600

V /2

CC

Sine-wave distortion

V

CC

V = V

IL

INH

10 µF

V

IN

V

CC

(ON)

GND

V

OUT

R =

L

10 k

V /2

CC

C = 50 pF

L

V

CC

(OFF)

GND

V

OUT

R =

L

600

V /2

CC

C = 50 pF

L

GND

R =

L

600

V /2

CC

C = 50 pF

L

f

in

f

in

Rev.3.00 Jul. 21, 2004 page 10 of 12

元器件交易网

HD74LV4053A

Package Dimensions

As of January, 2003

10.06

10.5 Max

16

9

Unit: mm

1

0.80 Max

*

0

.

2

0

±

0

.

0

5

8

5

.

5

7.80

+ 0.20

– 0.30

1.15

2

.

2

0

M

a

x

1.27

0

.

1

0

±

0

.

1

0

0

˚

– 8

˚

0.70 ± 0.20

*0.40 ± 0.06

0.15

0.12

M

Package Code

JEDEC

JEITA

Mass (reference value)

FP-16DAV

Conforms

0.24 g

*Ni/Pd/Au plating

As of January, 2003

Unit: mm

9.9

10.3 Max

16

9

1

1.27

0.635 Max

8

0

.

1

1

0

.

1

4

+

0

.

0

4

1

.

7

5

M

a

x

3

.

9

5

*

0

.

2

0

±

0

.

0

5

6.10

+ 0.10

– 0.30

1.08

0

˚

– 8

˚

*0.40 ± 0.06

0.15

0.25

M

0.60

+ 0.67

– 0.20

*Ni/Pd/Au plating

Package Code

JEDEC

JEITA

Mass (reference value)

FP-16DNV

Conforms

Conforms

0.15 g

Rev.3.00 Jul. 21, 2004 page 11 of 12

元器件交易网

HD74LV4053A

As of January, 2003

Unit: mm

5.00

5.30 Max

169

1

*

0.20 ± 0.05

8

0.65

0.13

M

0.65 Max

6.40 ± 0.20

0˚ – 8˚

0.50 ± 0.10

1.0

4

.

4

0

*

0

.

1

5

±

0

.

0

5

1

.

1

0

M

a

x

0.10

0

.

0

3

0

.

0

7

+

0

.

0

4

*Ni/Pd/Au plating

Package Code

JEDEC

JEITA

Mass (reference value)

TTP-16DAV

0.05 g

Rev.3.00 Jul. 21, 2004 page 12 of 12

元器件交易网

Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan

1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble

may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage.

Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary

circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap.

Notes regarding these materials

1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's

application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or a third party.

2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data,

diagrams, charts, programs, algorithms, or circuit application examples contained in these materials.

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8. Please contact Renesas Technology Corp. for further details on these materials or the products contained therein.

Keep safety first in your circuit designs!

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26/F., Ruijin Building, No.205 Maoming Road (S), Shanghai 200020, China

Tel: <86> (21) 6472-1001, Fax: <86> (21) 6415-2952

Renesas Technology Singapore Pte. Ltd.

1, Harbour Front Avenue, #06-10, Keppel Bay Tower, Singapore 098632

Tel: <65> 6213-0200, Fax: <65> 6278-8001

© 2004. Renesas Technology Corp., All rights reserved. Printed in Japan.

Colophon .1.0

2024年9月9日发(作者:宝梓柔)

元器件交易网

HD74LV4053A

Triple 2-channel Analog Multiplexer / Demultiplexer

REJ03D0339–0300Z

(Previous ADE-205-284A (Z))

Rev.3.00

Jul. 21, 2004

Description

The HD74LV4053A handles both analog and digital signals, and enables signals of either type with amplitudes of up to

5.5 V (peak) to be transmitted in either direction (at V

CC

= 0 V to 5.5 V).

Applications include signal gating, chopping, modulation or demodulation (modem), and signal multiplexing for

analog-to-digital and digital-to-analog conversion systems.

Features

• V

CC

= 2.0 V to 5.5 V operation

• All control inputs V

IH

(Max.) = 5.5 V (@V

CC

= 0 V to 5.5 V)

• Ordering Information

Part Name

HD74LV4053AFPEL

HD74LV4053ARPEL

HD74LV4053ATELL

Package Type

SOP–16 pin (JEITA)

SOP–16 pin (JEDEC)

TSSOP–16 pin

Package Code

FP–16DAV

FP–16DNV

TTP–16DAV

Package

Abbreviation

FP

RP

T

Taping Abbreviation

(Quantity)

EL (2,000 pcs/reel)

EL (2,500 pcs/reel)

ELL (2,000 pcs/reel)

Note: Please consult the sales office for the above package availability.

Function Table

Inputs

INH

L

L

L

L

L

L

L

L

H

Note:H:High level

L:Low level

X:Immaterial

C

L

L

L

L

H

H

H

H

X

B

L

L

H

H

L

L

H

H

X

A

L

H

L

H

L

H

L

H

X

On Channel

1Y0, 2Y0, 3Y0

1Y1, 2Y0, 3Y0

1Y0, 2Y1, 3Y0

1Y1, 2Y1, 3Y0

1Y0, 2Y0, 3Y1

1Y1, 2Y0, 3Y1

1Y0, 2Y1, 3Y1

1Y1, 2Y1, 3Y1

NONE

Rev.3.00 Jul. 21, 2004 page 1 of 12

元器件交易网

HD74LV4053A

Pin Arrangement

2Y1

1

2Y0

3Y1

2

3

16

V

CC

15

2−COM

14

1−COM

13

1Y1

12

1Y0

11

A

10

B

9

C

3−COM

4

3Y0

INH

GND

GND

5

6

7

8

(Top view)

Absolute Maximum Ratings

Item

Supply voltage range

Input voltage range*

1

Output voltage range*

1, 2

Input clamp current

Output clamp current

Continuous output current

Continuous current through

V

CC

or GND

Maximum power dissipation at

Ta = 25°C (in still air)*

3

Storage temperature

Symbol

V

CC

V

I

V

O

I

IK

I

OK

I

O

I

CC

or

I

GND

P

T

Tstg

Ratings

–0.5 to 7.0

–0.5 to 7.0

–0.5 to V

CC

+ 0.5

–20

±50

±25

±50

785

500

–65 to 150

Unit

V

V

V

mA

mA

mA

mA

mW

°C

Conditions

Output: H or L

V

I

< 0

V

O

< 0 or V

O

> V

CC

V

O

= 0 to V

CC

SOP

TSSOP

Notes:The absolute maximum ratings are values, which must not individually be exceeded, and furthermore, no two of

which may be realized at the same time.

input and output voltage ratings may be exceeded even if the input and output clamp-current ratings are

observed.

value is limited to 5.5 V maximum.

maximum package power dissipation was calculated using a junction temperature of 150°C.

Rev.3.00 Jul. 21, 2004 page 2 of 12

元器件交易网

HD74LV4053A

Recommended Operating Conditions

Item

Supply voltage range

Input voltage range

Output voltage range

Input transition rise or fall rate

Symbol

V

CC

V

I

V

I/O

∆t /∆v

Min

2.0*

0

0

0

0

0

–40

1

Max

5.5

5.5

V

CC

200

100

20

85

Unit

V

V

V

ns/V

Conditions

V

CC

= 2.3 to 2.7 V

V

CC

= 3.0 to 3.6 V

V

CC

= 4.5 to 5.5 V

Operating free-air temperatureTa°C

Notes:Unused or floating control inputs must be held high or low.

the supply voltage at or around 2 V, the analog switch on-state resistance loses linearity significantly. It

is recommended that only digital signals be transmitted at these low supply voltages.

Logic Diagram

2−COM

1−COM

A

1Y0

1Y1

B

2Y0

2Y1

C

3Y0

3Y1

INH

3−COM

Rev.3.00 Jul. 21, 2004 page 3 of 12

元器件交易网

HD74LV4053A

DC Electrical Characteristics

Ta = 25°C

Item

Input voltage

Symbol

V

IH

V

CC

(V)

2.0

2.3 to 2.7

3.0 to 3.6

4.5 to 5.5

2.0

2.3 to 2.7

3.0 to 3.6

4.5 to 5.5

2.3

3.0

4.5

2.3

3.0

4.5

2.3

3.0

4.5

5.5

Min

Typ

60

50

40

200

90

50

20

10

7

Max

180

150

75

500

180

100

30

20

15

±0.1

Ta = –40 to 85°C

Min

1.5

V

CC

× 0.7

V

CC

× 0.7

V

CC

× 0.7

Max

0.5

V

CC

× 0.3

V

CC

× 0.3

V

CC

× 0.3

225

190

100

600

225

125

40

30

20

±1.0

Unit

V

Test Conditions

Control input only

V

IL

On-state switch

resistance

Peak on resistance

R

ON

ΩV

IN

= V

CC

or GND

V

INH

= V

IL

I

T

= 2 mA

V

IN

= V

CC

to GND

V

INH

= V

IL

I

T

= 2 mA

V

IN

= V

CC

to GND

V

INH

= V

IL

I

T

= 2 mA

V

IN

= V

CC

,

V

OUT

= GND or

V

IN

= GND,

V

O

= V

CC

,V

INH

= V

IH

V

IN

= V

CC

or GND

V

INH

= V

IL

V

IN

= 5.5 V or GND

V

IN

= V

CC

or GND

R

ON (P)

Difference of on-state

resistance between

switches

Off-state switch

leakage current

∆R

ON

Is (OFF)µA

On-state switch

leakage current

Input current

Quiescent supply

current

Is (ON)

I

IN

I

CC

5.5

0 to 5.5

5.5

±0.1

±0.1

±1.0

±1.0

20

µA

µA

µA

Note:For conditions shown as Min or Max, use the appropriate values under recommended operating conditions.

Rev.3.00 Jul. 21, 2004 page 4 of 12

元器件交易网

HD74LV4053A

Switching Characteristics

V

CC

= 2.5 ± 0.2 V

Ta = 25°C

Item

Propagation

delay time

Enable time

Disable time

Symbol

t

PLH

t

PHL

t

ZH

t

ZL

t

HZ

t

LZ

Min

Typ

2.5

5.0

7.0

9.0

9.0

13.0

Max

10.0

12.0

18.0

28.0

18.0

28.0

Ta = –40 to 85°C

Min

Max

16.0

18.0

23.0

35.0

23.0

35.0

Unit

ns

ns

ns

Test Conditions

C

L

= 15 pF

C

L

= 50 pF

R

L

= 1 kΩ

R

L

= 1 kΩ

C

L

= 15 pF

C

L

= 50 pF

C

L

= 15 pF

C

L

= 50 pF

FROM

(Input)

COM

or Yn

INH

INH

TO

(Output)

Yn or

COM

COM or

Yn

COM or

Yn

V

CC

= 3.3 ± 0.3 V

Ta = 25°C

Item

Propagation

delay time

Enable time

Disable time

Symbol

t

PLH

t

PHL

t

ZH

t

ZL

t

HZ

t

LZ

Min

Typ

2.0

4.0

5.0

7.0

7.0

10.0

Max

6.0

9.0

12.0

20.0

12.0

20.0

Ta = –40 to 85°C

Min

Max

10.0

12.0

15.0

25.0

15.0

25.0

Unit

ns

ns

ns

Test Conditions

C

L

= 15 pF

C

L

= 50 pF

R

L

= 1 kΩ

R

L

= 1 kΩ

C

L

= 15 pF

C

L

= 50 pF

C

L

= 15 pF

C

L

= 50 pF

FROM

(Input)

COM

or Yn

INH

INH

TO

(Output)

Yn or

COM

COM or

Yn

COM or

Yn

V

CC

= 5.0 ± 0.5 V

Ta = 25°C

Item

Propagation

delay time

Enable time

Disable time

Symbol

t

PLH

t

PHL

t

ZH

t

ZL

t

HZ

t

LZ

Min

Typ

1.5

3.0

4.0

5.0

5.0

8.0

Max

4.0

6.0

8.0

14.0

8.0

14.0

Ta = –40 to 85°C

Min

Max

7.0

8.0

10.0

18.0

10.0

18.0

Unit

ns

ns

ns

Test Conditions

C

L

= 15 pF

C

L

= 50 pF

R

L

= 1 kΩ

R

L

= 1 kΩ

C

L

= 15 pF

C

L

= 50 pF

C

L

= 15 pF

C

L

= 50 pF

FROM

(Input)

COM

or Yn

INH

INH

TO

(Output)

Yn or

COM

COM or

Yn

COM or

Yn

Rev.3.00 Jul. 21, 2004 page 5 of 12

元器件交易网

HD74LV4053A

Switching Characteristics (cont.)

Ta = 25°C

Item

Control input

capacitance

Common

terminal

capacitance

Symbol

V

CC

(V)

Min

C

IC

C

IS

Typ

4.5

12.5

Max

Unit

pF

pF

Test Conditions

FROMTO

(Input)(Output)

Switch terminalC

I/O

capacitance

Feedthrough

capacitance

Power

dissipation

capacitance

Frequency

response

(Switch ON)

C

T

C

PD

7.0

0.5

9.0

pF

pF

pF

2.3

3.0

4.5

30.0

35.0

50.0

MHz

Crosstalk

(Between any

switches)

Crosstalk

(Control input

to signal

output)

Feedthrough

attenuation

(Switch OFF)

Sine-wave

distortion

2.3

3.0

4.5

2.3

3.0

4.5

2.3

3.0

4.5

2.3

3.0

4.5

–45.0—

–45.0—

–45.0—

20.0

35.0

65.0

–45

–45

–45

0.1

0.1

0.1

dB

mV

dB

C

L

= 50 pF, R

L

= 600 Ω

Adjust f

in

voltage to obtain 0 dBm

at output when f

in

is 1 MHz (sine

wave). Increase f

in

frequency

until the dB-meter reads –3 dBm.

20 log (V

O

/V

I

) = –3 dBm

C

L

= 50 pF, R

L

= 600 Ω

Adjust f

in

voltage to obtain 0 dBm

at input when f

in

is 1 MHz

(sine wave).

C

L

= 50 pF, R

L

= 600 Ω

Adjust R

L

value to obtain 0 A at

I

IN/OUT

when f

in

is 1 MHz

(square wave).

C

L

= 50 pF, R

L

= 600 Ω

Adjust f

in

voltage to obtain 0 dBm

at input when f

in

is 1 MHz

(sine wave).

C

L

= 50 pF, R

L

= 10 kΩ

f

IN

= 1 kHz (sine wave)

V

I

= 2 V

P-P

, V

CC

= 2.3 V

V

I

= 2.5 V

P-P

, V

CC

= 3.0 V

V

I

= 4 V

P-P

, V

CC

= 4.5 V

COM

or Yn

Yn or

COM

COMYn

INHCOM or

Yn

COM

or Yn

Yn or

COM

%

COM

or Yn

Yn or

COM

Rev.3.00 Jul. 21, 2004 page 6 of 12

元器件交易网

HD74LV4053A

Test Circuits

R : On-state switch resistance

ON

V

CC

V = V

INHIL

V

CC

V = V or GND

INCC

(ON)

GND

V

OUT

V

IN

−V

OUT

2 × 10

−3

R =

ON

2.0 mA

V

V

IN

−V

OUT

(Ω)

Is (OFF): Off-state switch leakage current, Is (ON): On-state switch leakage current

V

CC

V = V

INHIH

V

CC

AA

(OFF)

GND

B

V = V

INHIL

V

CC

V

CC

A

A

(ON)

GND

B

Open

Rev.3.00 Jul. 21, 2004 page 7 of 12

元器件交易网

HD74LV4053A

t , t : Propagation delay time (from switch input to switch output)

PLHPHL

V

CC

V = V

INHIL

V

CC

A

R =

L

50

(ON)

GND

B

C = 15 or

L

50 pF

Switching time

V

CC

R =

L

50

V

INH

S1

V

IN

V

CC

GND

V

OUT

R =

L

1 k

S2

C = 15 or

L

50 pF

TEST

t /t

LZZL

t /t

HZZH

V

CC

V

INH

50%

V

CC

t

ZL

V

OUT

50%

V

CC

V

OL

0 V

≈V

CC

V

OUT

V

INH

S1

GND

V

CC

S2

V

CC

GND

V

CC

50%

V

CC

t

ZH

50%

V

CC

≈0 V

0 V

V

OH

V

CC

V

INH

50%

V

CC

t

LZ

V

OUT

V

OL

+0.3 V

V

OL

0 V

≈V

CC

V

OUT

V

INH

50%

V

CC

t

HZ

V

OH

−0.3 V

V

CC

0 V

V

OH

≈0 V

Rev.3.00 Jul. 21, 2004 page 8 of 12

元器件交易网

HD74LV4053A

Frequency response (Switch ON)

V

CC

V = V

ILINH

0.1 µF

V

IN

R =

L

50

V

CC

(ON)

GND

V

OUT

R =

L

600

V /2

CC

C = 50 pF

L

f = sine wave

in

f

in

Crosstalk (Between any switches)

V = GND

INH

V =V

CCC

or GND

f

in

R =

L

0.1 µF

600

R =

L

50

V

IN

V

CC

V

CC

(ON)

GND

V

OUT1

R =

L

600

V /2

CC

C = 50 pF

L

V = GND

INH

V =V

CCC

or GND

V

CC

V

CC

R =

L

600

V /2

CC

(OFF)

GND

V

OUT2

R =

L

600

V /2

CC

C = 50 pF

L

Rev.3.00 Jul. 21, 2004 page 9 of 12

元器件交易网

HD74LV4053A

Crosstalk (Control input to signal output)

V

CC

R =

L

50

V

INH

V

CC

V

OUT

R =

L

600

V /2

CC

Feedthrough attenuation (Switch OFF)

V

CC

V = V

IH

INH

R =

L

0.1 µF

600

R =

L

50

V

IN

R =

L

600

V /2

CC

Sine-wave distortion

V

CC

V = V

IL

INH

10 µF

V

IN

V

CC

(ON)

GND

V

OUT

R =

L

10 k

V /2

CC

C = 50 pF

L

V

CC

(OFF)

GND

V

OUT

R =

L

600

V /2

CC

C = 50 pF

L

GND

R =

L

600

V /2

CC

C = 50 pF

L

f

in

f

in

Rev.3.00 Jul. 21, 2004 page 10 of 12

元器件交易网

HD74LV4053A

Package Dimensions

As of January, 2003

10.06

10.5 Max

16

9

Unit: mm

1

0.80 Max

*

0

.

2

0

±

0

.

0

5

8

5

.

5

7.80

+ 0.20

– 0.30

1.15

2

.

2

0

M

a

x

1.27

0

.

1

0

±

0

.

1

0

0

˚

– 8

˚

0.70 ± 0.20

*0.40 ± 0.06

0.15

0.12

M

Package Code

JEDEC

JEITA

Mass (reference value)

FP-16DAV

Conforms

0.24 g

*Ni/Pd/Au plating

As of January, 2003

Unit: mm

9.9

10.3 Max

16

9

1

1.27

0.635 Max

8

0

.

1

1

0

.

1

4

+

0

.

0

4

1

.

7

5

M

a

x

3

.

9

5

*

0

.

2

0

±

0

.

0

5

6.10

+ 0.10

– 0.30

1.08

0

˚

– 8

˚

*0.40 ± 0.06

0.15

0.25

M

0.60

+ 0.67

– 0.20

*Ni/Pd/Au plating

Package Code

JEDEC

JEITA

Mass (reference value)

FP-16DNV

Conforms

Conforms

0.15 g

Rev.3.00 Jul. 21, 2004 page 11 of 12

元器件交易网

HD74LV4053A

As of January, 2003

Unit: mm

5.00

5.30 Max

169

1

*

0.20 ± 0.05

8

0.65

0.13

M

0.65 Max

6.40 ± 0.20

0˚ – 8˚

0.50 ± 0.10

1.0

4

.

4

0

*

0

.

1

5

±

0

.

0

5

1

.

1

0

M

a

x

0.10

0

.

0

3

0

.

0

7

+

0

.

0

4

*Ni/Pd/Au plating

Package Code

JEDEC

JEITA

Mass (reference value)

TTP-16DAV

0.05 g

Rev.3.00 Jul. 21, 2004 page 12 of 12

元器件交易网

Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan

1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble

may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage.

Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary

circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap.

Notes regarding these materials

1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's

application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or a third party.

2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data,

diagrams, charts, programs, algorithms, or circuit application examples contained in these materials.

3. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of

publication of these materials, and are subject to change by Renesas Technology Corp. without notice due to product improvements or other reasons. It is

therefore recommended that customers contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor for the latest product

information before purchasing a product listed herein.

The information described here may contain technical inaccuracies or typographical errors.

Renesas Technology Corp. assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors.

Please also pay attention to information published by Renesas Technology Corp. by various means, including the Renesas Technology Corp. Semiconductor

home page ().

4. When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to

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is potentially at stake. Please contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor when considering the use of a

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cannot be imported into a country other than the approved destination.

Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited.

8. Please contact Renesas Technology Corp. for further details on these materials or the products contained therein.

Keep safety first in your circuit designs!

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Tel: <1> (408) 382-7500 Fax: <1> (408) 382-7501

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7/F., North Tower, World Finance Centre, Harbour City, Canton Road, Hong Kong

Tel: <852> 2265-6688, Fax: <852> 2375-6836

Renesas Technology Taiwan Co., Ltd.

FL 10, #99, Fu-Hsing N. Rd., Taipei, Taiwan

Tel: <886> (2) 2715-2888, Fax: <886> (2) 2713-2999

Renesas Technology (Shanghai) Co., Ltd.

26/F., Ruijin Building, No.205 Maoming Road (S), Shanghai 200020, China

Tel: <86> (21) 6472-1001, Fax: <86> (21) 6415-2952

Renesas Technology Singapore Pte. Ltd.

1, Harbour Front Avenue, #06-10, Keppel Bay Tower, Singapore 098632

Tel: <65> 6213-0200, Fax: <65> 6278-8001

© 2004. Renesas Technology Corp., All rights reserved. Printed in Japan.

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