2024年10月23日发(作者：赫连阳曜)
RT8803A
2/3-Phase PWM Controller for High-Density Power Supply
General Description
The RT8803A is a 2/3-phase synchronous buck controller
specifically designed to power Intel
®
/ AMD next generation
microprocessors. It implements an internal 8-bit DAC that is
identified by VID code of microprocessor directly. RT8803A
generates VID table that conform to Intel
®
VRD10.x and
VRD11 core power with 6.25mV increments and 0.5%
accuracy.
RT8803A adopts innovative time-sharing DCR current sensing
technique to sense phase currents for phase current balance,
load line setting and over current protection. Using a common
GM to sense all phase currents eliminates offset and linearity
variation between GMs in conventional current sensing
methods. As sub-milli-ohm-grade inductors are widely used
in modern motherboards, slight offset and linearity mismatch
will cause considerable current shift between phases. This
technique ensures good current balance at mass production.
Other features include over current protection, programmable
soft start, over voltage protection, and output offset setting.
RT8803A comes to a small footprint package with
VQFN-32L 5x5.
Features
z
z
5V Power Supply
2/3-Phase Power Conversion with Automatic Phase
Selection
8-bit VID Interface, Supporting Intel VRD11/VRD10.x
and AMD K8, K8_M2 CPUs
VR_HOT and VR_FAN Indication
Precision Core Voltage Regulation
Power Stage Thermal Balance by DCR Current
Sensing
Adjustable Soft-start
Over-Voltage Protection
Adjustable Frequency and Typical at 300kHz per
Phase
Power Good Indication
32-Lead VQFN Package
RoHS Compliant and 100% Lead (Pb)-Free
z
z
z
z
z
z
z
z
z
z
Applications
z
z
Ordering Information
RT8803A
Package Type
QV : VQFN-32L 5x5 (V-Type)
Lead Plating System
P : Pb Free
G : Green (Halogen Free and Pb Free)
z
Intel
®
/AMD New generation microprocessor for Desktop
PC and Motherboard
Low Output Voltage, High power density DC-DC
Converters
Voltage Regulator Modules
Pin Configurations
(TOP VIEW)
V
I
D
_
S
E
L
V
I
D
0
V
I
D
1
V
I
D
2
V
I
D
3
V
I
D
4
27
V
I
D
5
26
Note :
3231302928
Richtek products are :
`
RoHS compliant and compatible with the current require-
VTT/EN
VR_Ready
FBRTN
FB
COMP
SS
VR_FAN
VR_HOT
V
I
D
6
25
24
23
22
21
20
19
1
2
3
4
5
6
7
8
916
33
ments of IPC/JEDEC J-STD-020.
`
Suitable for use in SnPb or Pb-free soldering processes.
GND
VID7
VDD
PWM3
PWM2
PWM1
ISP1
ISP2
ISP3
18
17
I
M
A
X
R
T
I
S
N
1
VQFN-32L 5x5
DS8803A-06 April 2011
I
S
N
2
3
T
S
E
N
D
V
D
O
F
S
A
D
J
1
2
V
I
N
B
T
X
_
1
2
V
R
3
3
R
2
7
1
0
1
N
4
1
4
8
C
1
6
1
u
F
Q
1
I
P
D
0
9
N
0
3
L
A
Q
2
I
P
S
0
6
N
0
3
L
A
Q
3
L
1
2
8
0
n
H
R
T
2
N
T
C
2
k
C
5
5
.
6
p
F
R
1
7
0
C
P
U
_
V
C
C
C
1
1
0
.
1
u
F
R
2
8
2
.
2
C
1
7
3
.
3
n
F
R
1
5
C
6
1
5
k
2
.
2
n
F
R
1
6
1
.
5
k
C
4
5
6
n
F
C
7
4
7
0
p
F
1
2
0
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4
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7
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F
4
.
7
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F
C
1
5
4
.
7
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F
B
T
X
_
1
2
V
C
1
2
C
1
3
C
1
4
V
C
O
R
E
1
6
5
4
2
0
2
1
FB
RT8803A
R
1
3
R
1
4
1
2
k
8
.
2
k
Typical Application Circuit
C
3
5
6
n
F
R
1
1
3
0
0
B
T
X
_
5
V
R
1
9
B
T
X
_
1
2
V
C
2
0
4
.
7
u
F
C
2
1
3
6
0
V
C
O
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E
2
3
R
2
9
1
0
1
N
4
1
4
8
C
2
3
1
u
F
I
P
D
0
9
N
0
3
L
A
Q
5
I
P
S
0
6
N
0
3
L
A
Q
6
Q
4
7
5
k
3
6
0
V
C
O
R
E
1
3
1
2
0
0
u
F
4
.
7
u
F
V
I
N
C
1
9
C
2
2
4
.
7
u
F
PWM1
PWM2
COMP
F
o
r
A
M
D
1
0
0
R
1
2
3
0
0
1
3
1
1
1
4
R
1
8
7
5
k
R
2
0
R
2
1
R
2
2
1
B
O
O
T
3
8
N
C
U
G
A
T
E
7
4
V
C
C
P
H
A
S
E
R
T
9
6
1
9
5
L
G
A
T
E
2
P
W
M
P
G
N
D
6
SS
RT
ADJ
IMAX
V
I
D
_
S
E
L
P
W
M
3
2
2
I
S
N
2
3
I
S
N
1
1
5
I
S
P
1
1
9
1
8
I
S
P
2
I
S
P
3
1
7
TSEN
F
o
r
I
n
t
e
l
1
6
V
D
D
I
O
F
o
r
K
8
R
T
8
8
0
3
A
F
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K
8
_
M
2
G
N
D
V
C
O
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E
2
3
V
C
C
V
S
S
G
N
D
V
I
D
0
V
I
D
1
V
I
D
2
V
I
D
3
V
I
D
4
V
I
D
5
V
I
D
6
V
I
D
7
C
1
8
0
.
1
u
F
L
2
2
8
0
n
H
VR_HOT
VR_Ready
VR_FAN
VTT/EN
FBRTN
B
T
X
_
5
V
B
T
X
_
5
V
R
7
C
8
1
u
F
R
2
3
3
6
0
R
3
1
1
0
R
2
4
3
6
0
R
2
6
3
6
0
B
T
X
_
1
2
V
C
9
2
1
u
F
C
1
0
1
u
F
R
2
5
N
C
OFS
R
1
1
0
3
2
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
1
0
V
I
D
_
S
E
L
V
I
D
0
V
I
D
1
V
I
D
2
V
I
D
3
V
I
D
4
V
I
D
5
V
I
D
6
V
I
D
7
V
D
D
D
V
D
C
3
2
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C
4
1
5
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F
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3
0
2
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2
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2
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3
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3
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1
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1
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1
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1
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F
3
1
2
9
C
2
0
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1
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F
1
8
7
2
B
T
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_
1
2
V
R
2
1
0
k
1
B
O
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T
8
N
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A
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4
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C
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9
6
1
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5
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2
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6
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1
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4
1
4
8
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7
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4
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5
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F
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D
R
4
R
5
R
6
1
0
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1
0
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1
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C
3
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1
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F
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0
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N
0
3
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A
C
2
5
0
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1
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V
C
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E
2
3
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7
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3
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8
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3
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A
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9
P
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1
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3
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A
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4
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C
P
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A
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T
9
6
1
9
5
L
G
A
T
E
2
V
I
N
P
G
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D
6
R
3
2
2
.
2
C
3
1
3
.
3
n
F
R
T
1
1
0
k
N
T
C
DS8803A-06 April 2011
R
1
0
0
C
P
U
_
V
S
S
RT8803A
Functional Pin Description
VTT/EN (Pin 1)
The pin is defined as the chip enable, and the VTT is
applied for internal VID pull high power and power sequence
monitoring.
VR_Ready (Pin 2)
Power good open-drain output.
FBRTN (Pin 3)
Feedback return pin. VID DAC and error amplifier reference
for remote sensing of the output voltage.
FB (Pin 4)
Inverting input pin of the internal error amplifier.
COMP (Pin 5)
Output pin of the error amplifier and input pin of the PWM
comparator.
SS (Pin 6)
Connect this SS pin to GND with a capacitor to set the
soft-start time interval.
VR_FAN (Pin 7)
The pin is defined to signal VR thermal information for
external VR thermal dissipation scheme triggering.
VR_HOT (Pin 8)
The pin is defined to signal VR thermal information for
external VR thermal dissipation scheme triggering.
TSEN (Pin 9)
Temperature detect pin for VR_HOT and VR_FAN.
DVD (Pin 10)
Programmable power UVLO detection input. Trip threshold
is 1V at V
DVD
rising.
RT (Pin 11)
The pin is defined to set internal switching operation
frequency. Connect this pin to GND with a resistor R
RT
to
set the frequency F
SW
.
F
SW
=
4.463 e
9
R
RT
+3500
OFS (Pin 12)
The pin is defined for load line offset setting.
ADJ (Pin 13)
Current sense output for active droop adjusting. Connect
a resistor from this pin to GND to set the load droop.
IMAX (Pin 14)
The pin is defined to set threshold of over current.
ISN1 (Pin 15)
Current sense negative input pin for channel 1 current
sensing.
ISN23 (Pin 16)
Current sense negative input pins for channel 2 and
channel 4 current sensing.
ISP1 (Pin 19), ISP2 (Pin 18), ISP3 (Pin 17)
Current sense positive input pins for individual converter
channel current sensing.
PWM1 (Pin 20), PWM2 (Pin 21), PWM3 (Pin 22)
PWM outputs for each driven channel. Connect these pins
to the PWM input of the MOSFET driver. For systems
which using 2/3/4 channels, pull PWM 3/4/5 pins up to
high.
VDD (Pin 23)
IC power supply. Connect this pin to a 5V supply.
VID7 (Pin 24), VID6 (Pin 25), VID5 (Pin 26), VID4 (Pin
27), VID3 (Pin 28), VID2 (Pin 29), VID1 (Pin 30),
VID0 (Pin 31), VID_SEL (32)
DAC voltage identification inputs for VRD10.x / VRD11 /
K8 / K8_M2 . These pins are internally pulled up to VTT.
VIDSEL VID [7] Table
VTT X VR11
GND X VR10.x
VDD NC K8
VDD GND K8_M2
GND [Exposed pad (33)]
The exposed pad must be soldered to a large PCB and
connected to GND for maximum power dissipation.
3
DS8803A-06 April 2011
RT8803A
Function Block Diagram
VDDVTT/ENDVD
SS
VR_Ready
COMP
FB
OFS
VID7
VID6
VID5
VID4
VID3
VID2
VID1
VID0
VID_SEL
FBRTN
Soft Start
& PGOOD
Power On
Reset
Oscillator
&
Ramp
Generator
RT
DAC
TSEN
VR_FAN
VR_HOT
Temperature
Processing
Droop Tune
& Hi-I
Detection
Sample
& Hold
Mux
ADJ
GND
4
+
CSA
-
+
Clamp
EA
Current
Processing
SUM/N
& OCP
Detection
Pulse
Width
Modulator
& Output
Buffer
PWM1
PWM2
PWM3
IMAX
Mux
ISN1
ISN23
ISP1
Mux
ISP2
ISP3
-
DS8803A-06 April 2011
RT8803A
Table 1. Output Voltage Program (VRD10.x + VID6)
Nominal Output Voltage DACOUT
VID4 VID3 VID2 VID1 VID0 VID5 VID6
0 1 0 1 0 1 1
0 1 0 1 0 1 0
0 1 0 1 1 0 1
0 1 0 1 1 0 0
0 1 0 1 1 1 1
0 1 0 1 1 1 0
0 1 1 0 0 0 1
0 1 1 0 0 0 0
0 1 1 0 0 1 1
0 1 1 0 0 1 0
0 1 1 0 1 0 1
0 1 1 0 1 0 0
0 1 1 0 1 1 1
0 1 1 0 1 1 0
0 1 1 1 0 0 1
0 1 1 1 0 0 0
0 1 1 1 0 1 1
0 1 1 1 0 1 0
0 1 1 1 1 0 1
0 1 1 1 1 0 0
0 1 1 1 1 1 1
0 1 1 1 1 1 0
1 0 0 0 0 0 1
1 0 0 0 0 0 0
1 0 0 0 0 1 1
1 0 0 0 0 1 0
1 0 0 0 1 0 1
1 0 0 0 1 0 0
1 0 0 0 1 1 1
1 0 0 0 1 1 0
1 0 0 1 0 0 1
1 0 0 1 0 0 0
1 0 0 1 0 1 1
1 0 0 1 0 1 0
1 0 0 1 1 0 1
1 0 0 1 1 0 0
1 0 0 1 1 1 1
1 0 0 1 1 1 0
1 0 1 0 0 0 1
1.60000V
1.59375V
1.58750V
1.58125V
1.57500V
1.56875V
1.56250V
1.55625V
1.55000V
1.54375V
1.53750V
1.53125V
1.52500V
1.51875V
1.51250V
1.50625V
1.50000V
1.49375V
1.48750V
1.48125V
1.47500V
1.46875V
1.46250V
1.45625V
1.45000V
1.44375V
1.43750V
1.43125V
1.42500V
1.41875V
1.41250V
1.40625V
1.40000V
1.39375V
1.38750V
1.38125V
1.37500V
1.36875V
1.36250V
Pin Name
DS8803A-06 April 2011
To be continued
5
RT8803A
Table 1. Output Voltage Program (VRD10.x + VID6)
Nominal Output Voltage DACOUT
VID4 VID3 VID2 VID1 VID0 VID5 VID6
1 0 1 0 0 0 0
1 0 1 0 0 1 1
1 0 1 0 0 1 0
1 0 1 0 1 0 1
1 0 1 0 1 0 0
1 0 1 0 1 1 1
1 0 1 0 1 1 0
1 0 1 1 0 0 1
1 0 1 1 0 0 0
1 0 1 1 0 1 1
1 0 1 1 0 1 0
1 0 1 1 1 0 1
1 0 1 1 1 0 0
1 0 1 1 1 1 1
1 0 1 1 1 1 0
1 1 0 0 0 0 1
1 1 0 0 0 0 0
1 1 0 0 0 1 1
1 1 0 0 0 1 0
1 1 0 0 1 0 1
1 1 0 0 1 0 0
1 1 0 0 1 1 1
1 1 0 0 1 1 0
1 1 0 1 0 0 1
1 1 0 1 0 0 0
1 1 0 1 0 1 1
1 1 0 1 0 1 0
1 1 0 1 1 0 1
1 1 0 1 1 0 0
1 1 0 1 1 1 1
1 1 0 1 1 1 0
1 1 1 0 0 0 1
1 1 1 0 0 0 0
1 1 1 0 0 1 1
1 1 1 0 0 1 0
1 1 1 0 1 0 1
1 1 1 0 1 0 0
1 1 1 0 1 1 1
1 1 1 0 1 1 0
1.35625V
1.35000V
1.34375V
1.33750V
1.33125V
1.32500V
1.31875V
1.31250V
1.30625V
1.30000V
1.29375V
1.28750V
1.28125V
1.27500V
1.26875V
1.26250V
1.25625V
1.25000V
1.24375V
1.23750V
1.23125V
1.22500V
1.21875V
1.21250V
1.20625V
1.20000V
1.19375V
1.18750V
1.18125V
1.17500V
1.16875V
1.16250V
1,15625V
1.15000V
1.14375V
1.13750V
1.13125V
1.12500V
1.11875V
Pin Name
To be continued
6
DS8803A-06 April 2011
RT8803A
Table 1. Output Voltage Program (VRD10.x + VID6)
Nominal Output Voltage DACOUT
VID4 VID3 VID2 VID1 VID0 VID5 VID6
1 1 1 1 0 0 1
1 1 1 1 0 0 0
1 1 1 1 0 1 1
1 1 1 1 0 1 0
1 1 1 1 1 0 1
1 1 1 1 1 0 0
1 1 1 1 1 1 1
1 1 1 1 1 1 0
0 0 0 0 0 0 1
0 0 0 0 0 0 0
0 0 0 0 0 1 1
0 0 0 0 0 1 0
0 0 0 0 1 0 1
0 0 0 0 1 0 0
0 0 0 0 1 1 1
0 0 0 0 1 1 0
0 0 0 1 0 0 1
0 0 0 1 0 0 0
0 0 0 1 0 1 1
0 0 0 1 0 1 0
0 0 0 1 1 0 1
0 0 0 1 1 0 0
0 0 0 1 1 1 1
0 0 0 1 1 1 0
0 0 1 0 0 0 1
0 0 1 0 0 0 0
0 0 1 0 0 1 1
0 0 1 0 0 1 0
0 0 1 0 1 0 1
0 0 1 0 1 0 0
0 0 1 0 1 1 1
0 0 1 0 1 1 0
0 0 1 1 0 0 1
0 0 1 1 0 0 0
0 0 1 1 0 1 1
0 0 1 1 0 1 0
0 0 1 1 1 0 1
0 0 1 1 1 0 0
0 0 1 1 1 1 1
1.11250V
1.10625V
1.10000V
1.09375V
OFF
OFF
OFF
OFF
1.08750V
1.08125V
1.07500V
1.06875V
1.06250V
1.05625V
1.05000V
1.04375V
1.03750V
1.03125V
1.02500V
1.01875V
1.01250V
1.00625V
1.00000V
0.99375V
0.98750V
0.98125V
0.97500V
0.96875V
0.96250V
0.95625V
0.95000V
0.94375V
0.93750V
0.93125V
0.92500V
0.91875V
0.91250V
0.90625V
0.90000V
Pin Name
DS8803A-06 April 2011
To be continued
7
RT8803A
Table 1. Output Voltage Program (VRD10.x + VID6)
Nominal Output Voltage DACOUT
VID4 VID3 VID2 VID1 VID0 VID5 VID6
0 0 1 1 1 1 0
0 1 0 0 0 0 1
0 1 0 0 0 0 0
0 1 0 0 0 1 1
0 1 0 0 0 1 0
0 1 0 0 1 0 1
0 1 0 0 1 0 0
0 1 0 0 1 1 1
0 1 0 0 1 1 0
0 1 0 1 0 0 1
0 1 0 1 0 0 0
0.89375V
0.88750V
0.88125V
0.87500V
0.86875V
0.86250V
0.85625V
0.85000V
0.84375V
0.83750V
0.83125V
Pin Name
8
DS8803A-06 April 2011
RT8803A
Table 2. Output Voltage Program (VRD11)
Pin Name
Nominal Output Voltage DACOUT
Pin Name
HEX
00 OFF
01 OFF
02 1.60000V
03 1.59375V
04 1.58750V
05 1.58125V
06 1.57500V
07 1.56875V
08 1.56250V
09 1.55625V
0A 1.55000V
0B 1.54375V
0C 1.53750V
0D 1.53125V
0E 1.52500V
0F 1.51875V
10 1.51250V
11 1.50625V
12 1.50000V
13 1.49375V
14 1.48750V
15 1.48125V
16 1.47500V
17 1.46875V
18 1.46250V
19 1.45625V
1A 1.45000V
1B 1.44375V
1C 1.43750V
1D 1.43125V
1E 1.42500V
1F 1.41875V
20 1.41250V
21 1.40625V
22 1.40000V
23 1.39375V
24 1.38750V
25 1.38125V
26 1.37500V
HEX
27 1.36875V
28 1.36250V
29 1.35625V
2A 1.35000V
2B 1.34375V
2C 1.33750V
2D 1.33125V
2E 1.32500V
2F 1.31875V
30 1.31250V
31 1.30625V
32 1.30000V
33 1.29375V
34 1.28750V
35 1.28125V
36 1.27500V
37 1.26875V
38 1.26250V
39 1.25625V
3A 1.25000V
3B 1.24375V
3C 1.23750V
3D 1.23125V
3E 1.22500V
3F 1.21875V
40 1.21250V
41 1.20625V
42 1.20000V
43 1.19375V
44 1.18750V
45 1.18125V
46 1.17500V
47 1.16875V
48 1.16250V
49 1.15625V
4A 1.15000V
4B 1.14375V
4C 1.13750V
4D 1.13125V
Nominal Output Voltage DACOUT
DS8803A-06 April 2011
To be continued
9
RT8803A
Table 2. Output Voltage Program (VRD11)
Pin Name
Nominal Output Voltage DACOUT
Pin Name
Nominal Output Voltage DACOUT
HEX
4E 1.12500V
4F 1.11875V
50 1.11250V
51 1.10625V
52 1.10000V
53 1.09375V
54 1.08750V
55 1.08125V
56 1.07500V
57 1.06875V
58 1.06250V
59 1.05625V
5A 1.05000V
5B 1.04375V
5C 1.03750V
5D 1.03125V
5E 1.02500V
5F 1.01875V
60 1.01250V
61 1.00625V
62 1.00000V
63 0.99375V
64 0.98750V
65 0.98125V
66 0.97500V
67 0.96875V
68 0.96250V
69 0.95625V
6A 0.95000V
6B 0.94375V
6C 0.93750V
6D 0.93125V
6E 0.92500V
6F 0.91875V
70 0.91250V
71 0.90625V
72 0.90000V
73 0.89375V
74 0.88750V
HEX
75 0.88125V
76 0.87500V
77 0.86875V
78 0.86250V
79 0.85625V
7A 0.85000V
7B 0.84375V
7C 0.83750V
7D 0.83125V
7E 0.82500V
7F 0.81875V
80 0.81250V
81 0.80625V
82 0.80000V
83 0.79375V
84 0.78750V
85 0.78125V
86 0.77500V
87 0.76875V
88 0.76250V
89 0.75625V
8A 0.75000V
8B 0.74375V
8C 0.73750V
8D 0.73125V
8E 0.72500V
8F 0.71875V
90 0.71250V
91 0.70625V
92 0.70000V
93 0.69375V
94 0.68750V
95 0.68125V
96 0.67500V
97 0.66875V
98 0.66250V
99 0.65625V
9A 0.65000V
9B 0.64375V
10
To be continued
DS8803A-06 April 2011
RT8803A
Table 2. Output Voltage Program (VRD11)
Pin Name
Nominal Output Voltage DACOUT
Pin Name
Nominal Output Voltage DACOUT
HEX
9C 0.63750V
9D 0.63125V
9E 0.62500V
9F 0.61875V
A0 0.61250V
A1 0.60625V
A2 0.60000V
A3 0.59375V
A4 0.58750V
A5 0.58125V
A6 0.57500V
A7 0.56875V
A8 0.56250V
A9 0.55625V
AA 0.55000V
AB 0.54375V
AC 0.53750V
AD 0.53125V
AE 0.52500V
AF 0.51875V
B0 0.51250V
B1 0.50625V
B2 0.50000V
B3 X
B4 X
B5 X
B6 X
B7 X
B8 X
B9 X
BA X
BB X
BC X
BD X
BE X
BF X
C0 X
C1 X
C2 X
HEX
C3 X
C4 X
C5 X
C6 X
C7 X
C8 X
C9 X
CA X
CB X
CC X
CD X
CE X
CF X
D0 X
D1 X
D2 X
D3 X
D4 X
D5 X
D6 X
D7 X
D8 X
D9 X
DA X
DB X
DC X
DD X
DE X
DF X
E0 X
E1 X
E2 X
E3 X
E4 X
E5 X
E6 X
E7 X
E8 X
E9 X
DS8803A-06 April 2011
To be continued
11
RT8803A
Table 2. Output Voltage Program (VRD11)
Pin Name
Nominal Output Voltage DACOUT
HEX
EA X
EB X
EC X
ED X
EE X
EF X
F0 X
F1 X
F2 X
F3 X
F4 X
F5 X
F6 X
F7 X
F8 X
F9 X
FA X
FB X
FC X
FD X
FE OFF
FF OFF
Note: (1) 0 : Connected to GND
(2) 1 : Open
(3) X : Don
'
t Care
12
DS8803A-06 April 2011
RT8803A
Table 3. Output Voltage Program (K8)
VID4 VID3 VID2 VID1 VID0 Nominal Output Voltage DACOUT
0 0 0 0 0
0 0 0 0 1
0 0 0 1 0
0 0 0 1 1
0 0 1 0 0
0 0 1 0 1
0 0 1 1 0
0 0 1 1 1
0 1 0 0 0
0 1 0 0 1
0 1 0 1 0
0 1 0 1 1
0 1 1 0 0
0 1 1 0 1
0 1 1 1 0
0 1 1 1 1
1 0 0 0 0
1 0 0 0 1
1 0 0 1 0
1 0 0 1 1
1 0 1 0 0
1 0 1 0 1
1 0 1 1 0
1 0 1 1 1
1 1 0 0 0
1 1 0 0 1
1 1 0 1 0
1 1 0 1 1
1 1 1 0 0
1 1 1 0 1
1 1 1 1 0
1 1 1 1 1
Note: (1) 0 : Connected to GND
(2) 1 : Open
1.550
1.525
1.500
1.475
1.450
1.425
1.400
1.375
1.350
1.325
1.200
1.275
1.250
1.225
1.200
1.175
1.150
1.125
1.100
1.075
1.050
1.025
1.000
0.975
0.950
0.925
0.900
0.875
0.850
0.825
0.800
Shutdown
DS8803A-06 April
13
RT8803A
Table 4. Output Voltage Program (K8_M2)
Nominal Output Voltage DACOUT
VID5 VID4 VID3 VID2 VID1 VID0
0 0 0 0 0 0
0 0 0 0 0 1
0 0 0 0 1 0
0 0 0 0 1 1
0 0 0 1 0 0
0 0 0 1 0 1
0 0 0 1 1 0
0 0 0 1 1 1
0 0 1 0 0 0
0 0 1 0 0 1
0 0 1 0 1 0
0 0 1 0 1 1
0 0 1 1 0 0
0 0 1 1 0 1
0 0 1 1 1 0
0 0 1 1 1 1
0 1 0 0 0 0
0 1 0 0 0 1
0 1 0 0 1 0
0 1 0 0 1 1
0 1 0 1 0 0
0 1 0 1 0 1
0 1 0 1 1 0
0 1 0 1 1 1
0 1 1 0 0 0
0 1 1 0 0 1
0 1 1 0 1 0
0 1 1 0 1 1
0 1 1 1 0 0
0 1 1 1 0 1
0 1 1 1 1 0
0 1 1 1 1 1
1 0 0 0 0 0
1 0 0 0 0 1
1.5500
1.5250
1.5000
1.4750
1.4500
1.4250
1.4000
1.3750
1.3500
1.3250
1.3000
1.2750
1.2500
1.2250
1.2000
1.1750
1.1500
1.1250
1.1000
1.0750
1.0500
1.0250
1.0000
0.9750
0.9500
0.9250
0.9000
0.8750
0.8500
0.8250
0.8000
0.7750
0.7625
0.7500
Pin Name
To be continued
14
DS8803A-06 April 2011
RT8803A
Table 4. Output Voltage Program (K8_M2)
Nominal Output Voltage DACOUT
VID5 VID4 VID3 VID2 VID1 VID0
1 0 0 0 1 0
1 0 0 0 1 1
1 0 0 1 0 0
1 0 0 1 0 1
1 0 0 1 1 0
1 0 0 1 1 1
1 0 1 0 0 0
1 0 1 0 0 1
1 0 1 0 1 0
1 0 1 0 1 1
1 0 1 1 0 0
1 0 1 1 0 1
1 0 1 1 1 0
1 0 1 1 1 1
1 1 0 0 0 0
1 1 0 0 0 1
1 1 0 0 1 0
1 1 0 0 1 1
1 1 0 1 0 0
1 1 0 1 0 1
1 1 0 1 1 0
1 1 0 1 1 1
1 1 1 0 0 0
1 1 1 0 0 1
1 1 1 0 1 0
1 1 1 0 1 1
1 1 1 1 0 0
1 1 1 1 0 1
1 1 1 1 1 0
1 1 1 1 1 1
0.7375
0.7250
0.7125
0.7000
0.6875
0.6750
0.6625
0.6500
0.6375
0.6250
0.6125
0.6000
0.5875
0.5750
0.5625
0.5500
0.5375
0.5250
0.5125
0.5000
0.4875
0.4750
0.4625
0.4500
0.4375
0.4250
0.4125
0.4000
0.3875
0.3750
Pin Name
Note: (1) 0 : Connected to GND
(2) 1 : Open
(3) The voltage above are load independent for desktop and server platforms. For mobile platforms the voltage above
correspond to zero load current.
DS8803A-06 April
15
RT8803A
Absolute Maximum Ratings
(Note 1)
z
z
z
z
z
z
z
z
Supply Voltage, V
DD
------------------------------------------------------------------------------------------
Input, Output or I/O Voltage--------------------------------------------------------------------------------
Power Dissipation, P
D
@ T
A
= 25°C
VQFN−32L 5x5------------------------------------------------------------------------------------------------
Package Thermal Resistance (Note 2)
VQFN-32L 5x5, θ
JA
-------------------------------------------------------------------------------------------
Junction Temperature----------------------------------------------------------------------------------------
Lead Temperature (Soldering, 10 sec.)------------------------------------------------------------------
Storage Temperature Range--------------------------------------------------------------------------------
ESD Susceptibility (Note 3)
HBM (Human Body Mode)----------------------------------------------------------------------------------
MM (Machine Mode)-----------------------------------------------------------------------------------------
7V
GND-0.3V to V
DD
+0.3V
2.778W
36°C/W
150°C
260°C
−65°C to 150°C
2kV
200V
Recommended Operating Conditions
(Note 4)
z
z
z
Supply Voltage, V
DD
------------------------------------------------------------------------------------------5V ± 10%
Junction Temperature Range-------------------------------------------------------------------------------−40°C to 125°C
Ambient Temperature Range-------------------------------------------------------------------------------−40°C to 85°C
Electrical Characteristics
(V
DD
= 5V, T
A
= 25°C, unless otherwise specified)
Parameter Symbol Test Conditions Min Typ Max Unit
V
DD
Supply Current
Nominal Supply Current
Power-On Reset
POR Threshold V
DDRTH
Trip (Low to High)
V
DD
Rising 4.0 4.2 4.5 V
V
I
DD
PWM 1,2,3 Open -- 12 16 mA
Hysteresis V
DDHYS
V
DVD
Threshold
V
TT
Threshold
Oscillator
Free Running Frequency
Frequency Adjustable Range
Ramp Amplitude
Ramp Valley
Maximum On-Time of Each Channel
RT Pin Voltage
f
OSC
ΔV
OSC
V
RT
V
DVDTH
Enable
V
TTTH
Enable
Hysteresis V
DVDHYS
Trip (Low to High)
Hysteresis V
TTHYS
0.2 0.5 --
0.9 1.0 1.1 V
-- 60 -- mV
0.75 0.85 0.95
V
-- 0.1 --
R
RT
= 20kΩ 180 200 220 kHz
50 -- 400 kHz f
OSC_ADJ
R
RT
= 20kΩ -- 1.9 -- V
Three Phase Operation 62 67 72 %
V
RV
0.7 1.0 -- V
R
RT
= 20kΩ 0.9 1.0 1.1 V
To be continued
16
DS8803A-06 April 2011
RT8803A
Parameter Symbol Test Conditions Min Typ Max Unit
Reference and DAC
V
DAC
≥ 1V
DACOUT Voltage Accuracy
DAC (VID0-VID125) Input Low
DAC (VID0-VID125) Input High
V
ID
Pull-up Resistance
OFS Pin Voltage
Error Amplifier
DC Gain -- 65 -- dB
ΔV
DAC
V
ILDAC
V
IHDAC
V
OFS
1V ≥ V
DAC
≥ 0.8V
V
DAC
< 0.8V
R
OFS
= 100kΩ
−0.5 -- 0.5 %
−5 -- 5 mV
−8 -- 8 mV
-- -- V
1/2V
TT
− 0.2
1/2V
TT
+ 0.2
-- -- V
12 15 18
kΩ
0.9 1.0 1.1 V
Gain-Bandwidth Product GBW -- 10 -- MHz
Slew Rate
Current Sense GM Amplifier
CSN Full Scale Source Current
CSN Current for OCP
Protection
Over-Voltage Trip (FB-DACOUT) ΔOVT
IMAX Voltage
Power Good
Output Low Voltage V
PGOODL
I
PGOOD
= 4mA -- -- 0.2 V
V
IMAX
100 150 200 mV
0.9 1.0 1.1 V
I
ISPFSS
100 -- --
μA
150 -- --
μA
SR COMP = 10pF -- 8 -- V/μs
R
IMAX
= 20k
Note 1. Stresses listed as the above "Absolute Maximum Ratings" may cause permanent damage to the device. These are for
stress ratings. Functional operation of the device at these or any other conditions beyond those indicated in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended
periods may remain possibility to affect device reliability.
Note 2. θ
JA
is measured in the natural convection at T
A
= 25°C on a low effective thermal conductivity test board of
JEDEC 51-3 thermal measurement standard.
Note 3. Devices are ESD sensitive. Handling precaution recommended.
Note 4. The device is not guaranteed to function outside its operating conditions.
DS8803A-06 April
17
RT8803A
Typical Operating Characteristics
Frequency vs. R
RT
700
600
GM
450
400
350
P
o
s
i
t
i
v
e
D
u
t
y
(
n
s
)
F
r
e
q
u
e
n
c
y
(
k
H
z
)
500
400
300
200
100
0
300
250
200
150
100
50
0
5150175200
PHASE 3
PHASE 1
PHASE 2
(k
ٛ
Ω
)R
RT
(k
ISN (uA)
Output Voltage vs. Temperature
1.264
1.262
322
320
318
Frequency vs. Temperature
O
u
t
p
u
t
V
o
l
t
a
g
e
(
V
)
1.26
F
r
e
q
u
e
n
c
y
(
k
H
z
)
-20
1.258
1.256
1.254
1.252
1.25
1.248
316
314
312
310
308
306
304
-20
Temperature
(°C)
Temperature
(°C)
Power On from DVD
Power Off from DVD
DVD
(1V/Div)
SS
(1V/Div)
V
OUT
(1V/Div)
PHASE 3
(10V/Div)
Time (1ms/Div)
DVD
(1V/Div)
SS
(1V/Div)
V
OUT
(1V/Div)
PHASE 3
(10V/Div)
Time (1μs/Div)
18
DS8803A-06 April 2011
RT8803A
Power On from VCC12Power Off from VCC12
VCC12
(10V/Div)
SS
(1V/Div)
V
OUT
(1V/Div)
PHASE 3
(10V/Div)
Time (1ms/Div)
VCC12
(10V/Div)
SS
(1V/Div)
V
OUT
(1V/Div)
PHASE 3
(10V/Div)
Time (1ms/Div)
Power On from VCC5Power Off from VCC5
VCC5
(5V/Div)
SS
(1V/Div)
V
OUT
(1V/Div)
PHASE 3
(10V/Div)
Time (1ms/Div)
VCC5
(5V/Div)
SS
(1V/Div)
V
OUT
(1V/Div)
PHASE 3
(10V/Div)
Time (25ms/Div)
Power On with OCP
VR_Ready
(1V/Div)
SS
(2V/Div)
V
OUT
1V/Div)
PWM
(5V/Div)
Time (500μs/Div)
VR_Ready
(1V/Div)
SS
(2V/Div)
V
OUT
(1V/Div)
PWM
(5V/Div)
Output Short Circuit
Time (1ms/Div)
DS8803A-06 April
19
RT8803A
V
OUT
Droop
V
OUT
Overshoot
V
OUT
(20mV/Div)
V
OUT
(20mV/Div)
I
OUT
(40A/Div)
Time (2μs/Div)
I
OUT
(40A/Div)
Time (2μs/Div)
Dynamic VID
V
OUT
(200mV/Div)
Dynamic VID
V
OUT
(200mV/Div)
VID0
(500mV/Div)
Time (50μs/Div)
VID0
(500mV/Div)
Time (50μs/Div)
OVP
VR_Ready
(1V/Div)
SS
(2V/Div)
FB
(1V/Div)
PWM
(5V/Div)
Time (10μs/Div)
20
DS8803A-06 April 2011
RT8803A
Applications Information
RT8803A is a multi-phase DC/DC controller specifically
designed to deliver high quality power for next generation
CPU. RT8803A controls a special power-on sequence &
monitors the thermal condition of VR module to meet the
VRD11 requirement. Phase currents are sensed by
innovative time-sharing DCR current sensing technique
for channel current balance, droop tuning, and over current
protection. Using one common GM amplifier for current
sensing eliminates offset errors and linearity variation
between GMs. As sub-milli-ohm-grade inductors are
widely used in modern mother boards, slight mismatch
of GM amplifiers offset and linearity results in considerable
current shift between phases. The time-sharing DCR
current sensing technique is extremely important to
guarantee phase current balance in mass production.
Converter Initialization, Phase Selection, and
Power Good Function
The RT8803A initiates only after 3 pins are ready: VDD
pin power on reset (POR), VTT/EN pin enabled, and DVD
pin is higher than 1V. VDD POR is to make sure RT8803A
is powered by a voltage for normal work. The rising
threshold voltage of VDD POR is 4.2V typically. At VDD
POR, RT8803A checks PWM3, PWM4 and PWM5 status
to determine phase number of operation. Pull high PWM3
for two-phase operation; pull high PWM4 for three-phase
operation; pull high PWM5 for four-phase operation. The
unused current sense pins should be connected to GND
or left floating.
VTT/EN acts as a chip enable pin and receives signal from
FSB or other power management IC.
DVD is to make sure that ATX12V is ready for drivers to
work normally. Connect a voltage divider from ATX12V to
DVD pin as shown in the Typical Application Circuit. Make
sure that DVD pin voltage is below its threshold voltage
before drivers are ready and above its threshold voltage
for minimum ATX12V during normal operation.
If any one of VDD, VTT/EN, and DVD is not ready, RT8803A
keeps its PWM outputs high impedance and the
companion drivers turn off both upper and lower
MOSFETs. After VDD, VTT/EN, and DVD are ready,
RT8803A initiates its soft start cycle that is compliant
with Intel
®
VRD11 specification as shown in Figure 1. A
time-variant internal current source charges the capacitor
connected to SS pin. SS voltage ramps up piecewise
linearly and locks VID_DAC output with a specified voltage
drop. Consequently, V
CORE
is built up according to
VID_DAC output and meet Intel
®
VRD11 requirement.
VR_READY output is pulled high by external resistor when
V
CORE
reaches VID_DAC output with 1~2ms delay. An
SS capacitor about 47nF is recommend for VRD11
compliance.
VDD POR, DVD, and VTT/EN ready
SS
V
CORE
1.1V
VR_Ready
VID on the fly
1~2ms1~2ms1~2ms
1~2ms
1~2ms
Figure 1. Timming Diagram During Soft Start Interval
Voltage Control
CPU V
CORE
voltage is Kelvin sensed by FB and FBRTN
pins and precisely regulated to VID_DAC output by internal
high gain Error Amplifier (EA). The sensed signal is also
used for power good and over voltage function. The typical
OVP trip point is 170mV above VID_DAC output. RT8803A
pulls PWM outputs low and latches up upon OVP trip to
prevent damaging the CPU. It can only restart by resetting
one of VDD, DVD, or VTT/EN pin.
RT8803A supports Intel VRD10.x, VRD11, AMD K8 and
AMD K8_M2 VID specification.
The change of VID_DAC output at VID on the fly is also
smoothed by capacitor connected to SS pin.
Consequently, Vcore shifts to its new position smoothly
as shown in Figure 2.
DS8803A-06 April
21
RT8803A
PWM3
V
CORE
Consequently, the sensing current I
X
is proportional to
inductor current I
LX
and is expressed as :
I×DCRx
I
X
=
LX
R
CSNX
The sensed current I
X
is used for current balance and droop
tuning as described as followed. Since all phases share
one common GM, GM offset and linearity variation effect
is eliminated in practical applications. As sub-milli-ohm-
grade inductors are widely used in modern mother boards,
slight mismatch of GM amplifiers offset and linearity results
in considerable current shift between phases. The time-
sharing DCR current sensing technical is extremely
important to guarantee phase current balance in mass
production.
Phase Current Balance
The sampled and held phase current I
X
are summed and
averaged to get the averaged current . Each phase
I
X
current I
X
then is compared with the averaged current.
The difference between I
X
and is injected to
I
X
corresponding PWM comparator. If phase current I
X
is
smaller than the averaged current , RT8803A increases
the duty cycle of corresponding phase to increase the
phase current accordingly and vice versa.
VID7
Figure 2. Vcore Response at VID on the Fly
DCR Current Sensing
RT8803A adopts an innovative time-sharing DCR current
sensing technique to sense the phase currents for phase
current balance (phase thermal balance) and load line
regulation as shown in Figure 3. Current sensing amplifier
GM samples and holds voltages VCx across the current
sensing capacitor Cx by turns in a switching cycle.
According to the Basic Circuit Theory, if
Lx
=Rx×Cx then VCx=I×DCRx
LX
DCRx
T1
T2
T3
I
X
= I
LX
x DCR
X
/R
CSNX
I
X
S/H CKT
+
CSA
-
L1
DCR1
R1
C1
+ VC1 -
L3
DCR3
ISP1
T1
T1
ISP3
T3
T3
ISN23
R
CSN3
L2
DCR2
ISN1
R
CSN1
R3
C3
+ VC3 -
CSA: Current Sense Amplifier
R2
ISP2
T2
T2
ISN23
C2
+ VC2 -
R
CSN2
Figure 3
22
DS8803A-06 April 2011
RT8803A
I
OFS
4
If
L
X
=(R
X
//R
PX
)×Cx then
DCRx
VCx=
R
PX
×I
LX
×DCRx
Rx+R
PX
V
CORE
R
FB1
-
+
EACOMP
V
ADJ
DAC
+
-
4I
X
R
ADJ
Figure 4. Load Line and Offset Function
Output Voltage Offset Function
To meet Intel
®
requirement of initial offset of load line,
RT8803A provides programmable initial offset function.
External resistor R
OFS
and voltage source at OFS pin
V
generate offset current
I
OFS
=
OFS
R
OFS
, where V
OFS
is 1V typical. One quarter of I
OFS
flows
through R
FB1
as shown in Figure 4. Error amplifier would
hold the inverting pin equal to V
DAC
- V
ADJ
. Thus output
voltage is subtracted from V
DAC
- V
ADJ
for a constant offset
voltage.
R
FB1
V
CORE
= V
DAC
− V
ADJ
−
4×R
OFS
A positive output voltage offset is possible by connecting
R
OFS
to VDD instead of to GND. Please note that when
R
OFS
is connected to VDD, V
OFS
is V
DD
− 2V typically and
half of I
OFS
flows through R
FB1
. V
CORE
is rewritten as :
V
CORE
= V
DAC
− V
ADJ
+
R
FB1
R
OFS
With other phase kept unchanged, this phase would share
(R
PX
+Rx)/R
PX
times current than other phases. Figure 6
and 7 show different current ratio setting for the power
stage when Phase 3 is programmed 2 times current than
other phases. Figure 8 and 9 compare the above current
ratio setting results.
L
X
DCRx
+
VCx
-
I
LX
Rx
Cx
R
PX
V
OUT
+
T
Figure 5
Current Ratio Setting
Current ratio adjustment is possible as described below.
It is important for achieving thermal balance in practical
application where thermal conditions between phases are
not identical. Figure 5 shows the application circuit of GM
for current ratio requirement. According to Basic Circuit
Theory
R
PX
Rx+R
PX
VCx = ×I
LX
×DCRx
SRx×R
PX
×Cx
+1
Rx+R
PX
Figure 6. GM3 Setting for current ratio function
Figure 7. GM1~2 Setting for current ratio function
DS8803A-06 April
23
RT8803A
Current Ratio Function
35
30
25
Load Line without dead zone at light loads
1.31
I
L3
1.3
1.29
w/o Dead Zone Compensation
R
CSN
open
I
L
(
A
)
20
15
10
I
L2
I
L1
V
C
O
R
E
(
V
)
1.28
1.27
1.26
1.25
R
CSN2
= 82k
w/i Dead Zone Compensation
5
0
0
1.24
1.23
I
OUT
(A)
I
OUT
(A)
Figure 8
Figure 10
Lx
Rx
DCRx
Cx
+
VCx
-
V
OUT
Current Balance Function
35
30
25
I
LX
I
L
(
A
)
20
15
10
5
0
02040
I
L3
GMx
+
-
R
CSN
R
CSN2
I
L2
I
L1
Ix
Figure 11. Application circuit of GM
6080100120
I
OUT
(A)
Referring to Figure 11, I
X
is expressed as :
I
X
=
I
LX_66%
×DCRxI
LX_66%
×DCRx
V
OUT
++
R
CSN2
R
CSN2
R
CSN
Figure 9
Dead Zone Elimination
RT8803A samples and holds inductor current at 50%
period by time-sharing sourcing a current I
X
to R
CSN
. At
light load condition when inductor current is not balance,
voltage VCx
across the sensing capacitor would be
negative. It needs a negative I
X
to sense the voltage.
However, RT8803A CANNOT provide a negative I
X
and
consequently cannot sense negative inductor current. This
results in dead zone of load line performance as shown in
Figure 10. Therefore a technique as shown in Figure 11 is
required to eliminate the dead zone of load line at light
load condition.
(1)
where I
LX_50%
is the of inductor current at 50% period. To
make sure RT8803A could sense the inductor current,
right hand side of Equation (1) should always be positive:
I
LX_66%
×DCRxI
LX_66%
×DCRx
V
OUT
++≥0
R
CSN2
R
CSN2
R
CSN
(2)
Since R
CSN
>> DCRx in practical application, Equation (2)
could be simplified as :
I
LX_66%
×DCRx
V
OUT
≥
R
CSN2
R
CSN
24
DS8803A-06 April 2011
RT8803A
For example, assuming the negative inductor current is
I
LX_50%
= −5A at no load, then for
R
CSN
330Ω, R
ADJ
= 160Ω, V
OUT
= 1.300V
If R
ADJ
is connected as in Figure 14, R
ADJ
= R1 + (R2//
R
NTC
), which is a negative temperature correlated
resistance. By properly selecting R1 and R2, the positive
temperature coefficient of DCR can be canceled by the
negative temperature coefficient of R
ADJ
. Thus the load
line will be thermally compensated.
ADJ
1.3V
≥
−5A×1mΩ
R
CSN2
330Ω
R
CSN2
≤ 85.8kΩ
Choose R
CSN2
= 82kΩ
Figure 10 shows that dead zone of load line at light load
is eliminated by applying this technique.
VR_HOT & VR_FAN Setting
V
CC
5V
R1
R
ADJ
R
NTC
R2
Figure 14. R
ADJ
Connection for Thernal Compensation
R1
V
TSEN
R
NTC
0.28 x V
CC
TSEN
0.39 x V
CC
0.33 x V
CC
+
CMP
-
+
CMP
-
+
CMP
-
Q1
Over Current Protection
Phase current OCP
RT8803A uses an external resistor R
IMAX
connected to
IMAX pin to generate a reference current I
IMAX
for over
current protection :
V
I
IMAX
=
IMAX
R
IMAX
where V
IMAX
is typical 1.0V . OCP comparator compares
each sensed phase current I
X
with this reference current
as shown in Figure 15. Equivalently, the maximum phase
current I
LX(MAX)
is calculated as below:
1
1
I
X(MAX)
=
I
IMAX
2
3
V
I
X(MAX)
=
3
I
IMAX
=
3
×
IMAX
2
R
IMAX
2
R
R
V
I
LX(MAX)
=
I
X
×
CSNX
=
3
×
IMAX
×
CSNX
R
LX
2
R
IMAX
DCR
X
OCP Comparator
Q2
Q3
Figure 12
V
TSEN
V
TSEN
is inversely proportional
to Temperature.
0.39 x V
CC
0.33 x V
CC
0.28 x V
CC
VR_FAN
VR_HOT
Temperature
Figure 13. VR_HOT and VR_FAN Signal vs TSEN Voltage
Load Line Setting and Thermal Compensation
V
ADJ
= Sum(I
X
) x R
ADJ
= (DCR x R
ADJ
/ R
CSN
) x I
OUT
= LL x I
OUT
V
OUT
= V
DAC
− V
ADJ
= V
DAC
− LL x I
OUT
LL = DCR(PTC) x R
ADJ
(NTC) / R
CSN
DCR is the inductor DCR which is a PTC resistance.
+
-
1/3 I
X
1/2 I
IMAX
Figure 15. Over Current Comparator
DS8803A-06 April
25
RT8803A
Error Amplifier Characteristic
For fast response of converter to meet stringent output
current transient response, RT8803A provides large slew
rate capability and high gain-bandwidth performance.
B
4.7k
4.7k
-
EA
+
V
REF
A
EA Falling Slew Rate
Figure 18. Gain-Bandwidth Measurement by signal A
divided by signal B
Design Procedure Suggestion
V
FB
a. Output filter pole and zero (Inductor, output capacitor
value & ESR).
b. Error amplifier compensation & saw-tooth wave
amplitude (compensation network).
V
COMP
CH1:(500mV/Div)
CH2:(2V/Div)
c. Kelvin sense for V
CORE
.
Current Loop Setting
a. GM amplifier S/H current (current sense component
DCR, ISP
X
and ISN
X
pin external resistor value).
b. Over-current protection trip point (R
IMAX
resistor).
VRM Load Line Setting
a. Droop amplitude (ADJ pin resistor).
Time (250ns/Div)
Figure 16. EA Rising Transient with 10pF Loading ;
Slew Rate = 10V/μs
EA Rising Slew Rate
V
FB
b. No load offset (R
CSN
)
c. DAC offset voltage setting (OFS pin & compensation
network resistor).
d. Temperature coefficient compensation(TSEN external
resister & thermistor, resistor between ADJ and GND.)
Power Sequence & SS
V
COMP
CH1:(500mV/Div)
CH2:(2V/Div)
DVD pin external resistor and SS pin capacitor.
PCB Layout
sense for current sense GM amplifier input.
to layout guide for other items.
Time (250ns/Div)
Figure 17. EA Falling Transient with 10pF Loading ;
Slew Rate = 8V/μs
26
DS8803A-06 April 2011
RT8803A
Outline Dimension
D
D2
SEE DETAIL A
L
1
E
E2
e
b
1
2
1
2
A
A3
A1
DETAIL A
Pin #1 ID and Tie Bar Mark Options
Note : The configuration of the Pin #1 identifier is optional,
but must be located within the zone indicated.
Symbol
Dimensions In Millimeters Dimensions In Inches
Min Max Min Max
A 0.800 1.000 0.031 0.039
A1 0.000 0.050 0.000 0.002
A3 0.175 0.250 0.007 0.010
b 0.180 0.300 0.007 0.012
D 4.950 5.050 0.195 0.199
D2 3.400 3.750 0.134 0.148
E 4.950 5.050 0.195 0.199
E2 3.400 3.750 0.134 0.148
e 0.500 0.020
L 0.350 0.450
0.014 0.018
V-Type 32L QFN 5x5 Package
Richtek Technology Corporation
Headquarter
5F, No. 20, Taiyuen Street, Chupei City
Hsinchu, Taiwan, R.O.C.
Tel: (8863)5526789 Fax: (8863)5526611
Richtek Technology Corporation
Taipei Office (Marketing)
5F, No. 95, Minchiuan Road, Hsintien City
Taipei County, Taiwan, R.O.C.
Tel: (8862)86672399 Fax: (8862)86672377
Email:*********************
Information that is provided by Richtek Technology Corporation is believed to be accurate and reliable. Richtek reserves the right to make any change in circuit
design, specification or other related things if necessary without notice at any time. No third party intellectual property infringement of the applications should be
guaranteed by users when integrating Richtek products into any application. No legal responsibility for any said applications is assumed by Richtek.
DS8803A-06 April
27
2024年10月23日发(作者：赫连阳曜)
RT8803A
2/3-Phase PWM Controller for High-Density Power Supply
General Description
The RT8803A is a 2/3-phase synchronous buck controller
specifically designed to power Intel
®
/ AMD next generation
microprocessors. It implements an internal 8-bit DAC that is
identified by VID code of microprocessor directly. RT8803A
generates VID table that conform to Intel
®
VRD10.x and
VRD11 core power with 6.25mV increments and 0.5%
accuracy.
RT8803A adopts innovative time-sharing DCR current sensing
technique to sense phase currents for phase current balance,
load line setting and over current protection. Using a common
GM to sense all phase currents eliminates offset and linearity
variation between GMs in conventional current sensing
methods. As sub-milli-ohm-grade inductors are widely used
in modern motherboards, slight offset and linearity mismatch
will cause considerable current shift between phases. This
technique ensures good current balance at mass production.
Other features include over current protection, programmable
soft start, over voltage protection, and output offset setting.
RT8803A comes to a small footprint package with
VQFN-32L 5x5.
Features
z
z
5V Power Supply
2/3-Phase Power Conversion with Automatic Phase
Selection
8-bit VID Interface, Supporting Intel VRD11/VRD10.x
and AMD K8, K8_M2 CPUs
VR_HOT and VR_FAN Indication
Precision Core Voltage Regulation
Power Stage Thermal Balance by DCR Current
Sensing
Adjustable Soft-start
Over-Voltage Protection
Adjustable Frequency and Typical at 300kHz per
Phase
Power Good Indication
32-Lead VQFN Package
RoHS Compliant and 100% Lead (Pb)-Free
z
z
z
z
z
z
z
z
z
z
Applications
z
z
Ordering Information
RT8803A
Package Type
QV : VQFN-32L 5x5 (V-Type)
Lead Plating System
P : Pb Free
G : Green (Halogen Free and Pb Free)
z
Intel
®
/AMD New generation microprocessor for Desktop
PC and Motherboard
Low Output Voltage, High power density DC-DC
Converters
Voltage Regulator Modules
Pin Configurations
(TOP VIEW)
V
I
D
_
S
E
L
V
I
D
0
V
I
D
1
V
I
D
2
V
I
D
3
V
I
D
4
27
V
I
D
5
26
Note :
3231302928
Richtek products are :
`
RoHS compliant and compatible with the current require-
VTT/EN
VR_Ready
FBRTN
FB
COMP
SS
VR_FAN
VR_HOT
V
I
D
6
25
24
23
22
21
20
19
1
2
3
4
5
6
7
8
916
33
ments of IPC/JEDEC J-STD-020.
`
Suitable for use in SnPb or Pb-free soldering processes.
GND
VID7
VDD
PWM3
PWM2
PWM1
ISP1
ISP2
ISP3
18
17
I
M
A
X
R
T
I
S
N
1
VQFN-32L 5x5
DS8803A-06 April 2011
I
S
N
2
3
T
S
E
N
D
V
D
O
F
S
A
D
J
1
2
V
I
N
B
T
X
_
1
2
V
R
3
3
R
2
7
1
0
1
N
4
1
4
8
C
1
6
1
u
F
Q
1
I
P
D
0
9
N
0
3
L
A
Q
2
I
P
S
0
6
N
0
3
L
A
Q
3
L
1
2
8
0
n
H
R
T
2
N
T
C
2
k
C
5
5
.
6
p
F
R
1
7
0
C
P
U
_
V
C
C
C
1
1
0
.
1
u
F
R
2
8
2
.
2
C
1
7
3
.
3
n
F
R
1
5
C
6
1
5
k
2
.
2
n
F
R
1
6
1
.
5
k
C
4
5
6
n
F
C
7
4
7
0
p
F
1
2
0
0
u
F
4
.
7
u
F
4
.
7
u
F
C
1
5
4
.
7
u
F
B
T
X
_
1
2
V
C
1
2
C
1
3
C
1
4
V
C
O
R
E
1
6
5
4
2
0
2
1
FB
RT8803A
R
1
3
R
1
4
1
2
k
8
.
2
k
Typical Application Circuit
C
3
5
6
n
F
R
1
1
3
0
0
B
T
X
_
5
V
R
1
9
B
T
X
_
1
2
V
C
2
0
4
.
7
u
F
C
2
1
3
6
0
V
C
O
R
E
2
3
R
2
9
1
0
1
N
4
1
4
8
C
2
3
1
u
F
I
P
D
0
9
N
0
3
L
A
Q
5
I
P
S
0
6
N
0
3
L
A
Q
6
Q
4
7
5
k
3
6
0
V
C
O
R
E
1
3
1
2
0
0
u
F
4
.
7
u
F
V
I
N
C
1
9
C
2
2
4
.
7
u
F
PWM1
PWM2
COMP
F
o
r
A
M
D
1
0
0
R
1
2
3
0
0
1
3
1
1
1
4
R
1
8
7
5
k
R
2
0
R
2
1
R
2
2
1
B
O
O
T
3
8
N
C
U
G
A
T
E
7
4
V
C
C
P
H
A
S
E
R
T
9
6
1
9
5
L
G
A
T
E
2
P
W
M
P
G
N
D
6
SS
RT
ADJ
IMAX
V
I
D
_
S
E
L
P
W
M
3
2
2
I
S
N
2
3
I
S
N
1
1
5
I
S
P
1
1
9
1
8
I
S
P
2
I
S
P
3
1
7
TSEN
F
o
r
I
n
t
e
l
1
6
V
D
D
I
O
F
o
r
K
8
R
T
8
8
0
3
A
F
o
r
K
8
_
M
2
G
N
D
V
C
O
R
E
2
3
V
C
C
V
S
S
G
N
D
V
I
D
0
V
I
D
1
V
I
D
2
V
I
D
3
V
I
D
4
V
I
D
5
V
I
D
6
V
I
D
7
C
1
8
0
.
1
u
F
L
2
2
8
0
n
H
VR_HOT
VR_Ready
VR_FAN
VTT/EN
FBRTN
B
T
X
_
5
V
B
T
X
_
5
V
R
7
C
8
1
u
F
R
2
3
3
6
0
R
3
1
1
0
R
2
4
3
6
0
R
2
6
3
6
0
B
T
X
_
1
2
V
C
9
2
1
u
F
C
1
0
1
u
F
R
2
5
N
C
OFS
R
1
1
0
3
2
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
1
0
V
I
D
_
S
E
L
V
I
D
0
V
I
D
1
V
I
D
2
V
I
D
3
V
I
D
4
V
I
D
5
V
I
D
6
V
I
D
7
V
D
D
D
V
D
C
3
2
t
o
C
4
1
5
6
0
u
F
x
1
0
R
3
0
2
.
2
C
2
4
3
.
3
n
F
C
4
2
t
o
C
5
9
1
0
u
F
x
1
8
C
1
0
.
1
u
F
3
1
2
9
C
2
0
.
1
u
F
1
8
7
2
B
T
X
_
1
2
V
R
2
1
0
k
1
B
O
O
T
8
N
C
U
G
A
T
E
7
4
V
C
C
P
H
A
S
E
R
T
9
6
1
9
5
L
G
A
T
E
2
V
I
N
P
G
N
D
6
V
I
N
E
n
a
b
l
e
R
3
1
.
1
k
C
2
6
C
2
7
1
2
0
0
u
F
4
.
7
u
F
1
N
4
1
4
8
C
2
8
4
.
7
u
F
C
2
9
4
.
7
u
F
V
T
T
F
o
r
I
n
t
e
l
V
D
D
I
O
R
8
N
C
B
T
X
_
5
V
F
o
r
A
M
D
R
4
R
5
R
6
1
0
k
1
0
k
1
0
k
C
3
0
1
u
F
I
P
D
0
9
N
0
3
L
A
C
2
5
0
.
1
u
F
V
C
O
R
E
2
3
Q
7
L
3
2
8
0
n
H
Q
8
I
P
S
0
6
N
0
3
L
A
Q
9
P
G
O
O
D
R
9
N
C
1
B
O
O
T
3
8
N
C
U
G
A
T
E
7
4
V
C
C
P
H
A
S
E
R
T
9
6
1
9
5
L
G
A
T
E
2
V
I
N
P
G
N
D
6
R
3
2
2
.
2
C
3
1
3
.
3
n
F
R
T
1
1
0
k
N
T
C
DS8803A-06 April 2011
R
1
0
0
C
P
U
_
V
S
S
RT8803A
Functional Pin Description
VTT/EN (Pin 1)
The pin is defined as the chip enable, and the VTT is
applied for internal VID pull high power and power sequence
monitoring.
VR_Ready (Pin 2)
Power good open-drain output.
FBRTN (Pin 3)
Feedback return pin. VID DAC and error amplifier reference
for remote sensing of the output voltage.
FB (Pin 4)
Inverting input pin of the internal error amplifier.
COMP (Pin 5)
Output pin of the error amplifier and input pin of the PWM
comparator.
SS (Pin 6)
Connect this SS pin to GND with a capacitor to set the
soft-start time interval.
VR_FAN (Pin 7)
The pin is defined to signal VR thermal information for
external VR thermal dissipation scheme triggering.
VR_HOT (Pin 8)
The pin is defined to signal VR thermal information for
external VR thermal dissipation scheme triggering.
TSEN (Pin 9)
Temperature detect pin for VR_HOT and VR_FAN.
DVD (Pin 10)
Programmable power UVLO detection input. Trip threshold
is 1V at V
DVD
rising.
RT (Pin 11)
The pin is defined to set internal switching operation
frequency. Connect this pin to GND with a resistor R
RT
to
set the frequency F
SW
.
F
SW
=
4.463 e
9
R
RT
+3500
OFS (Pin 12)
The pin is defined for load line offset setting.
ADJ (Pin 13)
Current sense output for active droop adjusting. Connect
a resistor from this pin to GND to set the load droop.
IMAX (Pin 14)
The pin is defined to set threshold of over current.
ISN1 (Pin 15)
Current sense negative input pin for channel 1 current
sensing.
ISN23 (Pin 16)
Current sense negative input pins for channel 2 and
channel 4 current sensing.
ISP1 (Pin 19), ISP2 (Pin 18), ISP3 (Pin 17)
Current sense positive input pins for individual converter
channel current sensing.
PWM1 (Pin 20), PWM2 (Pin 21), PWM3 (Pin 22)
PWM outputs for each driven channel. Connect these pins
to the PWM input of the MOSFET driver. For systems
which using 2/3/4 channels, pull PWM 3/4/5 pins up to
high.
VDD (Pin 23)
IC power supply. Connect this pin to a 5V supply.
VID7 (Pin 24), VID6 (Pin 25), VID5 (Pin 26), VID4 (Pin
27), VID3 (Pin 28), VID2 (Pin 29), VID1 (Pin 30),
VID0 (Pin 31), VID_SEL (32)
DAC voltage identification inputs for VRD10.x / VRD11 /
K8 / K8_M2 . These pins are internally pulled up to VTT.
VIDSEL VID [7] Table
VTT X VR11
GND X VR10.x
VDD NC K8
VDD GND K8_M2
GND [Exposed pad (33)]
The exposed pad must be soldered to a large PCB and
connected to GND for maximum power dissipation.
3
DS8803A-06 April 2011
RT8803A
Function Block Diagram
VDDVTT/ENDVD
SS
VR_Ready
COMP
FB
OFS
VID7
VID6
VID5
VID4
VID3
VID2
VID1
VID0
VID_SEL
FBRTN
Soft Start
& PGOOD
Power On
Reset
Oscillator
&
Ramp
Generator
RT
DAC
TSEN
VR_FAN
VR_HOT
Temperature
Processing
Droop Tune
& Hi-I
Detection
Sample
& Hold
Mux
ADJ
GND
4
+
CSA
-
+
Clamp
EA
Current
Processing
SUM/N
& OCP
Detection
Pulse
Width
Modulator
& Output
Buffer
PWM1
PWM2
PWM3
IMAX
Mux
ISN1
ISN23
ISP1
Mux
ISP2
ISP3
-
DS8803A-06 April 2011
RT8803A
Table 1. Output Voltage Program (VRD10.x + VID6)
Nominal Output Voltage DACOUT
VID4 VID3 VID2 VID1 VID0 VID5 VID6
0 1 0 1 0 1 1
0 1 0 1 0 1 0
0 1 0 1 1 0 1
0 1 0 1 1 0 0
0 1 0 1 1 1 1
0 1 0 1 1 1 0
0 1 1 0 0 0 1
0 1 1 0 0 0 0
0 1 1 0 0 1 1
0 1 1 0 0 1 0
0 1 1 0 1 0 1
0 1 1 0 1 0 0
0 1 1 0 1 1 1
0 1 1 0 1 1 0
0 1 1 1 0 0 1
0 1 1 1 0 0 0
0 1 1 1 0 1 1
0 1 1 1 0 1 0
0 1 1 1 1 0 1
0 1 1 1 1 0 0
0 1 1 1 1 1 1
0 1 1 1 1 1 0
1 0 0 0 0 0 1
1 0 0 0 0 0 0
1 0 0 0 0 1 1
1 0 0 0 0 1 0
1 0 0 0 1 0 1
1 0 0 0 1 0 0
1 0 0 0 1 1 1
1 0 0 0 1 1 0
1 0 0 1 0 0 1
1 0 0 1 0 0 0
1 0 0 1 0 1 1
1 0 0 1 0 1 0
1 0 0 1 1 0 1
1 0 0 1 1 0 0
1 0 0 1 1 1 1
1 0 0 1 1 1 0
1 0 1 0 0 0 1
1.60000V
1.59375V
1.58750V
1.58125V
1.57500V
1.56875V
1.56250V
1.55625V
1.55000V
1.54375V
1.53750V
1.53125V
1.52500V
1.51875V
1.51250V
1.50625V
1.50000V
1.49375V
1.48750V
1.48125V
1.47500V
1.46875V
1.46250V
1.45625V
1.45000V
1.44375V
1.43750V
1.43125V
1.42500V
1.41875V
1.41250V
1.40625V
1.40000V
1.39375V
1.38750V
1.38125V
1.37500V
1.36875V
1.36250V
Pin Name
DS8803A-06 April 2011
To be continued
5
RT8803A
Table 1. Output Voltage Program (VRD10.x + VID6)
Nominal Output Voltage DACOUT
VID4 VID3 VID2 VID1 VID0 VID5 VID6
1 0 1 0 0 0 0
1 0 1 0 0 1 1
1 0 1 0 0 1 0
1 0 1 0 1 0 1
1 0 1 0 1 0 0
1 0 1 0 1 1 1
1 0 1 0 1 1 0
1 0 1 1 0 0 1
1 0 1 1 0 0 0
1 0 1 1 0 1 1
1 0 1 1 0 1 0
1 0 1 1 1 0 1
1 0 1 1 1 0 0
1 0 1 1 1 1 1
1 0 1 1 1 1 0
1 1 0 0 0 0 1
1 1 0 0 0 0 0
1 1 0 0 0 1 1
1 1 0 0 0 1 0
1 1 0 0 1 0 1
1 1 0 0 1 0 0
1 1 0 0 1 1 1
1 1 0 0 1 1 0
1 1 0 1 0 0 1
1 1 0 1 0 0 0
1 1 0 1 0 1 1
1 1 0 1 0 1 0
1 1 0 1 1 0 1
1 1 0 1 1 0 0
1 1 0 1 1 1 1
1 1 0 1 1 1 0
1 1 1 0 0 0 1
1 1 1 0 0 0 0
1 1 1 0 0 1 1
1 1 1 0 0 1 0
1 1 1 0 1 0 1
1 1 1 0 1 0 0
1 1 1 0 1 1 1
1 1 1 0 1 1 0
1.35625V
1.35000V
1.34375V
1.33750V
1.33125V
1.32500V
1.31875V
1.31250V
1.30625V
1.30000V
1.29375V
1.28750V
1.28125V
1.27500V
1.26875V
1.26250V
1.25625V
1.25000V
1.24375V
1.23750V
1.23125V
1.22500V
1.21875V
1.21250V
1.20625V
1.20000V
1.19375V
1.18750V
1.18125V
1.17500V
1.16875V
1.16250V
1,15625V
1.15000V
1.14375V
1.13750V
1.13125V
1.12500V
1.11875V
Pin Name
To be continued
6
DS8803A-06 April 2011
RT8803A
Table 1. Output Voltage Program (VRD10.x + VID6)
Nominal Output Voltage DACOUT
VID4 VID3 VID2 VID1 VID0 VID5 VID6
1 1 1 1 0 0 1
1 1 1 1 0 0 0
1 1 1 1 0 1 1
1 1 1 1 0 1 0
1 1 1 1 1 0 1
1 1 1 1 1 0 0
1 1 1 1 1 1 1
1 1 1 1 1 1 0
0 0 0 0 0 0 1
0 0 0 0 0 0 0
0 0 0 0 0 1 1
0 0 0 0 0 1 0
0 0 0 0 1 0 1
0 0 0 0 1 0 0
0 0 0 0 1 1 1
0 0 0 0 1 1 0
0 0 0 1 0 0 1
0 0 0 1 0 0 0
0 0 0 1 0 1 1
0 0 0 1 0 1 0
0 0 0 1 1 0 1
0 0 0 1 1 0 0
0 0 0 1 1 1 1
0 0 0 1 1 1 0
0 0 1 0 0 0 1
0 0 1 0 0 0 0
0 0 1 0 0 1 1
0 0 1 0 0 1 0
0 0 1 0 1 0 1
0 0 1 0 1 0 0
0 0 1 0 1 1 1
0 0 1 0 1 1 0
0 0 1 1 0 0 1
0 0 1 1 0 0 0
0 0 1 1 0 1 1
0 0 1 1 0 1 0
0 0 1 1 1 0 1
0 0 1 1 1 0 0
0 0 1 1 1 1 1
1.11250V
1.10625V
1.10000V
1.09375V
OFF
OFF
OFF
OFF
1.08750V
1.08125V
1.07500V
1.06875V
1.06250V
1.05625V
1.05000V
1.04375V
1.03750V
1.03125V
1.02500V
1.01875V
1.01250V
1.00625V
1.00000V
0.99375V
0.98750V
0.98125V
0.97500V
0.96875V
0.96250V
0.95625V
0.95000V
0.94375V
0.93750V
0.93125V
0.92500V
0.91875V
0.91250V
0.90625V
0.90000V
Pin Name
DS8803A-06 April 2011
To be continued
7
RT8803A
Table 1. Output Voltage Program (VRD10.x + VID6)
Nominal Output Voltage DACOUT
VID4 VID3 VID2 VID1 VID0 VID5 VID6
0 0 1 1 1 1 0
0 1 0 0 0 0 1
0 1 0 0 0 0 0
0 1 0 0 0 1 1
0 1 0 0 0 1 0
0 1 0 0 1 0 1
0 1 0 0 1 0 0
0 1 0 0 1 1 1
0 1 0 0 1 1 0
0 1 0 1 0 0 1
0 1 0 1 0 0 0
0.89375V
0.88750V
0.88125V
0.87500V
0.86875V
0.86250V
0.85625V
0.85000V
0.84375V
0.83750V
0.83125V
Pin Name
8
DS8803A-06 April 2011
RT8803A
Table 2. Output Voltage Program (VRD11)
Pin Name
Nominal Output Voltage DACOUT
Pin Name
HEX
00 OFF
01 OFF
02 1.60000V
03 1.59375V
04 1.58750V
05 1.58125V
06 1.57500V
07 1.56875V
08 1.56250V
09 1.55625V
0A 1.55000V
0B 1.54375V
0C 1.53750V
0D 1.53125V
0E 1.52500V
0F 1.51875V
10 1.51250V
11 1.50625V
12 1.50000V
13 1.49375V
14 1.48750V
15 1.48125V
16 1.47500V
17 1.46875V
18 1.46250V
19 1.45625V
1A 1.45000V
1B 1.44375V
1C 1.43750V
1D 1.43125V
1E 1.42500V
1F 1.41875V
20 1.41250V
21 1.40625V
22 1.40000V
23 1.39375V
24 1.38750V
25 1.38125V
26 1.37500V
HEX
27 1.36875V
28 1.36250V
29 1.35625V
2A 1.35000V
2B 1.34375V
2C 1.33750V
2D 1.33125V
2E 1.32500V
2F 1.31875V
30 1.31250V
31 1.30625V
32 1.30000V
33 1.29375V
34 1.28750V
35 1.28125V
36 1.27500V
37 1.26875V
38 1.26250V
39 1.25625V
3A 1.25000V
3B 1.24375V
3C 1.23750V
3D 1.23125V
3E 1.22500V
3F 1.21875V
40 1.21250V
41 1.20625V
42 1.20000V
43 1.19375V
44 1.18750V
45 1.18125V
46 1.17500V
47 1.16875V
48 1.16250V
49 1.15625V
4A 1.15000V
4B 1.14375V
4C 1.13750V
4D 1.13125V
Nominal Output Voltage DACOUT
DS8803A-06 April 2011
To be continued
9
RT8803A
Table 2. Output Voltage Program (VRD11)
Pin Name
Nominal Output Voltage DACOUT
Pin Name
Nominal Output Voltage DACOUT
HEX
4E 1.12500V
4F 1.11875V
50 1.11250V
51 1.10625V
52 1.10000V
53 1.09375V
54 1.08750V
55 1.08125V
56 1.07500V
57 1.06875V
58 1.06250V
59 1.05625V
5A 1.05000V
5B 1.04375V
5C 1.03750V
5D 1.03125V
5E 1.02500V
5F 1.01875V
60 1.01250V
61 1.00625V
62 1.00000V
63 0.99375V
64 0.98750V
65 0.98125V
66 0.97500V
67 0.96875V
68 0.96250V
69 0.95625V
6A 0.95000V
6B 0.94375V
6C 0.93750V
6D 0.93125V
6E 0.92500V
6F 0.91875V
70 0.91250V
71 0.90625V
72 0.90000V
73 0.89375V
74 0.88750V
HEX
75 0.88125V
76 0.87500V
77 0.86875V
78 0.86250V
79 0.85625V
7A 0.85000V
7B 0.84375V
7C 0.83750V
7D 0.83125V
7E 0.82500V
7F 0.81875V
80 0.81250V
81 0.80625V
82 0.80000V
83 0.79375V
84 0.78750V
85 0.78125V
86 0.77500V
87 0.76875V
88 0.76250V
89 0.75625V
8A 0.75000V
8B 0.74375V
8C 0.73750V
8D 0.73125V
8E 0.72500V
8F 0.71875V
90 0.71250V
91 0.70625V
92 0.70000V
93 0.69375V
94 0.68750V
95 0.68125V
96 0.67500V
97 0.66875V
98 0.66250V
99 0.65625V
9A 0.65000V
9B 0.64375V
10
To be continued
DS8803A-06 April 2011
RT8803A
Table 2. Output Voltage Program (VRD11)
Pin Name
Nominal Output Voltage DACOUT
Pin Name
Nominal Output Voltage DACOUT
HEX
9C 0.63750V
9D 0.63125V
9E 0.62500V
9F 0.61875V
A0 0.61250V
A1 0.60625V
A2 0.60000V
A3 0.59375V
A4 0.58750V
A5 0.58125V
A6 0.57500V
A7 0.56875V
A8 0.56250V
A9 0.55625V
AA 0.55000V
AB 0.54375V
AC 0.53750V
AD 0.53125V
AE 0.52500V
AF 0.51875V
B0 0.51250V
B1 0.50625V
B2 0.50000V
B3 X
B4 X
B5 X
B6 X
B7 X
B8 X
B9 X
BA X
BB X
BC X
BD X
BE X
BF X
C0 X
C1 X
C2 X
HEX
C3 X
C4 X
C5 X
C6 X
C7 X
C8 X
C9 X
CA X
CB X
CC X
CD X
CE X
CF X
D0 X
D1 X
D2 X
D3 X
D4 X
D5 X
D6 X
D7 X
D8 X
D9 X
DA X
DB X
DC X
DD X
DE X
DF X
E0 X
E1 X
E2 X
E3 X
E4 X
E5 X
E6 X
E7 X
E8 X
E9 X
DS8803A-06 April 2011
To be continued
11
RT8803A
Table 2. Output Voltage Program (VRD11)
Pin Name
Nominal Output Voltage DACOUT
HEX
EA X
EB X
EC X
ED X
EE X
EF X
F0 X
F1 X
F2 X
F3 X
F4 X
F5 X
F6 X
F7 X
F8 X
F9 X
FA X
FB X
FC X
FD X
FE OFF
FF OFF
Note: (1) 0 : Connected to GND
(2) 1 : Open
(3) X : Don
'
t Care
12
DS8803A-06 April 2011
RT8803A
Table 3. Output Voltage Program (K8)
VID4 VID3 VID2 VID1 VID0 Nominal Output Voltage DACOUT
0 0 0 0 0
0 0 0 0 1
0 0 0 1 0
0 0 0 1 1
0 0 1 0 0
0 0 1 0 1
0 0 1 1 0
0 0 1 1 1
0 1 0 0 0
0 1 0 0 1
0 1 0 1 0
0 1 0 1 1
0 1 1 0 0
0 1 1 0 1
0 1 1 1 0
0 1 1 1 1
1 0 0 0 0
1 0 0 0 1
1 0 0 1 0
1 0 0 1 1
1 0 1 0 0
1 0 1 0 1
1 0 1 1 0
1 0 1 1 1
1 1 0 0 0
1 1 0 0 1
1 1 0 1 0
1 1 0 1 1
1 1 1 0 0
1 1 1 0 1
1 1 1 1 0
1 1 1 1 1
Note: (1) 0 : Connected to GND
(2) 1 : Open
1.550
1.525
1.500
1.475
1.450
1.425
1.400
1.375
1.350
1.325
1.200
1.275
1.250
1.225
1.200
1.175
1.150
1.125
1.100
1.075
1.050
1.025
1.000
0.975
0.950
0.925
0.900
0.875
0.850
0.825
0.800
Shutdown
DS8803A-06 April
13
RT8803A
Table 4. Output Voltage Program (K8_M2)
Nominal Output Voltage DACOUT
VID5 VID4 VID3 VID2 VID1 VID0
0 0 0 0 0 0
0 0 0 0 0 1
0 0 0 0 1 0
0 0 0 0 1 1
0 0 0 1 0 0
0 0 0 1 0 1
0 0 0 1 1 0
0 0 0 1 1 1
0 0 1 0 0 0
0 0 1 0 0 1
0 0 1 0 1 0
0 0 1 0 1 1
0 0 1 1 0 0
0 0 1 1 0 1
0 0 1 1 1 0
0 0 1 1 1 1
0 1 0 0 0 0
0 1 0 0 0 1
0 1 0 0 1 0
0 1 0 0 1 1
0 1 0 1 0 0
0 1 0 1 0 1
0 1 0 1 1 0
0 1 0 1 1 1
0 1 1 0 0 0
0 1 1 0 0 1
0 1 1 0 1 0
0 1 1 0 1 1
0 1 1 1 0 0
0 1 1 1 0 1
0 1 1 1 1 0
0 1 1 1 1 1
1 0 0 0 0 0
1 0 0 0 0 1
1.5500
1.5250
1.5000
1.4750
1.4500
1.4250
1.4000
1.3750
1.3500
1.3250
1.3000
1.2750
1.2500
1.2250
1.2000
1.1750
1.1500
1.1250
1.1000
1.0750
1.0500
1.0250
1.0000
0.9750
0.9500
0.9250
0.9000
0.8750
0.8500
0.8250
0.8000
0.7750
0.7625
0.7500
Pin Name
To be continued
14
DS8803A-06 April 2011
RT8803A
Table 4. Output Voltage Program (K8_M2)
Nominal Output Voltage DACOUT
VID5 VID4 VID3 VID2 VID1 VID0
1 0 0 0 1 0
1 0 0 0 1 1
1 0 0 1 0 0
1 0 0 1 0 1
1 0 0 1 1 0
1 0 0 1 1 1
1 0 1 0 0 0
1 0 1 0 0 1
1 0 1 0 1 0
1 0 1 0 1 1
1 0 1 1 0 0
1 0 1 1 0 1
1 0 1 1 1 0
1 0 1 1 1 1
1 1 0 0 0 0
1 1 0 0 0 1
1 1 0 0 1 0
1 1 0 0 1 1
1 1 0 1 0 0
1 1 0 1 0 1
1 1 0 1 1 0
1 1 0 1 1 1
1 1 1 0 0 0
1 1 1 0 0 1
1 1 1 0 1 0
1 1 1 0 1 1
1 1 1 1 0 0
1 1 1 1 0 1
1 1 1 1 1 0
1 1 1 1 1 1
0.7375
0.7250
0.7125
0.7000
0.6875
0.6750
0.6625
0.6500
0.6375
0.6250
0.6125
0.6000
0.5875
0.5750
0.5625
0.5500
0.5375
0.5250
0.5125
0.5000
0.4875
0.4750
0.4625
0.4500
0.4375
0.4250
0.4125
0.4000
0.3875
0.3750
Pin Name
Note: (1) 0 : Connected to GND
(2) 1 : Open
(3) The voltage above are load independent for desktop and server platforms. For mobile platforms the voltage above
correspond to zero load current.
DS8803A-06 April
15
RT8803A
Absolute Maximum Ratings
(Note 1)
z
z
z
z
z
z
z
z
Supply Voltage, V
DD
------------------------------------------------------------------------------------------
Input, Output or I/O Voltage--------------------------------------------------------------------------------
Power Dissipation, P
D
@ T
A
= 25°C
VQFN−32L 5x5------------------------------------------------------------------------------------------------
Package Thermal Resistance (Note 2)
VQFN-32L 5x5, θ
JA
-------------------------------------------------------------------------------------------
Junction Temperature----------------------------------------------------------------------------------------
Lead Temperature (Soldering, 10 sec.)------------------------------------------------------------------
Storage Temperature Range--------------------------------------------------------------------------------
ESD Susceptibility (Note 3)
HBM (Human Body Mode)----------------------------------------------------------------------------------
MM (Machine Mode)-----------------------------------------------------------------------------------------
7V
GND-0.3V to V
DD
+0.3V
2.778W
36°C/W
150°C
260°C
−65°C to 150°C
2kV
200V
Recommended Operating Conditions
(Note 4)
z
z
z
Supply Voltage, V
DD
------------------------------------------------------------------------------------------5V ± 10%
Junction Temperature Range-------------------------------------------------------------------------------−40°C to 125°C
Ambient Temperature Range-------------------------------------------------------------------------------−40°C to 85°C
Electrical Characteristics
(V
DD
= 5V, T
A
= 25°C, unless otherwise specified)
Parameter Symbol Test Conditions Min Typ Max Unit
V
DD
Supply Current
Nominal Supply Current
Power-On Reset
POR Threshold V
DDRTH
Trip (Low to High)
V
DD
Rising 4.0 4.2 4.5 V
V
I
DD
PWM 1,2,3 Open -- 12 16 mA
Hysteresis V
DDHYS
V
DVD
Threshold
V
TT
Threshold
Oscillator
Free Running Frequency
Frequency Adjustable Range
Ramp Amplitude
Ramp Valley
Maximum On-Time of Each Channel
RT Pin Voltage
f
OSC
ΔV
OSC
V
RT
V
DVDTH
Enable
V
TTTH
Enable
Hysteresis V
DVDHYS
Trip (Low to High)
Hysteresis V
TTHYS
0.2 0.5 --
0.9 1.0 1.1 V
-- 60 -- mV
0.75 0.85 0.95
V
-- 0.1 --
R
RT
= 20kΩ 180 200 220 kHz
50 -- 400 kHz f
OSC_ADJ
R
RT
= 20kΩ -- 1.9 -- V
Three Phase Operation 62 67 72 %
V
RV
0.7 1.0 -- V
R
RT
= 20kΩ 0.9 1.0 1.1 V
To be continued
16
DS8803A-06 April 2011
RT8803A
Parameter Symbol Test Conditions Min Typ Max Unit
Reference and DAC
V
DAC
≥ 1V
DACOUT Voltage Accuracy
DAC (VID0-VID125) Input Low
DAC (VID0-VID125) Input High
V
ID
Pull-up Resistance
OFS Pin Voltage
Error Amplifier
DC Gain -- 65 -- dB
ΔV
DAC
V
ILDAC
V
IHDAC
V
OFS
1V ≥ V
DAC
≥ 0.8V
V
DAC
< 0.8V
R
OFS
= 100kΩ
−0.5 -- 0.5 %
−5 -- 5 mV
−8 -- 8 mV
-- -- V
1/2V
TT
− 0.2
1/2V
TT
+ 0.2
-- -- V
12 15 18
kΩ
0.9 1.0 1.1 V
Gain-Bandwidth Product GBW -- 10 -- MHz
Slew Rate
Current Sense GM Amplifier
CSN Full Scale Source Current
CSN Current for OCP
Protection
Over-Voltage Trip (FB-DACOUT) ΔOVT
IMAX Voltage
Power Good
Output Low Voltage V
PGOODL
I
PGOOD
= 4mA -- -- 0.2 V
V
IMAX
100 150 200 mV
0.9 1.0 1.1 V
I
ISPFSS
100 -- --
μA
150 -- --
μA
SR COMP = 10pF -- 8 -- V/μs
R
IMAX
= 20k
Note 1. Stresses listed as the above "Absolute Maximum Ratings" may cause permanent damage to the device. These are for
stress ratings. Functional operation of the device at these or any other conditions beyond those indicated in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended
periods may remain possibility to affect device reliability.
Note 2. θ
JA
is measured in the natural convection at T
A
= 25°C on a low effective thermal conductivity test board of
JEDEC 51-3 thermal measurement standard.
Note 3. Devices are ESD sensitive. Handling precaution recommended.
Note 4. The device is not guaranteed to function outside its operating conditions.
DS8803A-06 April
17
RT8803A
Typical Operating Characteristics
Frequency vs. R
RT
700
600
GM
450
400
350
P
o
s
i
t
i
v
e
D
u
t
y
(
n
s
)
F
r
e
q
u
e
n
c
y
(
k
H
z
)
500
400
300
200
100
0
300
250
200
150
100
50
0
5150175200
PHASE 3
PHASE 1
PHASE 2
(k
ٛ
Ω
)R
RT
(k
ISN (uA)
Output Voltage vs. Temperature
1.264
1.262
322
320
318
Frequency vs. Temperature
O
u
t
p
u
t
V
o
l
t
a
g
e
(
V
)
1.26
F
r
e
q
u
e
n
c
y
(
k
H
z
)
-20
1.258
1.256
1.254
1.252
1.25
1.248
316
314
312
310
308
306
304
-20
Temperature
(°C)
Temperature
(°C)
Power On from DVD
Power Off from DVD
DVD
(1V/Div)
SS
(1V/Div)
V
OUT
(1V/Div)
PHASE 3
(10V/Div)
Time (1ms/Div)
DVD
(1V/Div)
SS
(1V/Div)
V
OUT
(1V/Div)
PHASE 3
(10V/Div)
Time (1μs/Div)
18
DS8803A-06 April 2011
RT8803A
Power On from VCC12Power Off from VCC12
VCC12
(10V/Div)
SS
(1V/Div)
V
OUT
(1V/Div)
PHASE 3
(10V/Div)
Time (1ms/Div)
VCC12
(10V/Div)
SS
(1V/Div)
V
OUT
(1V/Div)
PHASE 3
(10V/Div)
Time (1ms/Div)
Power On from VCC5Power Off from VCC5
VCC5
(5V/Div)
SS
(1V/Div)
V
OUT
(1V/Div)
PHASE 3
(10V/Div)
Time (1ms/Div)
VCC5
(5V/Div)
SS
(1V/Div)
V
OUT
(1V/Div)
PHASE 3
(10V/Div)
Time (25ms/Div)
Power On with OCP
VR_Ready
(1V/Div)
SS
(2V/Div)
V
OUT
1V/Div)
PWM
(5V/Div)
Time (500μs/Div)
VR_Ready
(1V/Div)
SS
(2V/Div)
V
OUT
(1V/Div)
PWM
(5V/Div)
Output Short Circuit
Time (1ms/Div)
DS8803A-06 April
19
RT8803A
V
OUT
Droop
V
OUT
Overshoot
V
OUT
(20mV/Div)
V
OUT
(20mV/Div)
I
OUT
(40A/Div)
Time (2μs/Div)
I
OUT
(40A/Div)
Time (2μs/Div)
Dynamic VID
V
OUT
(200mV/Div)
Dynamic VID
V
OUT
(200mV/Div)
VID0
(500mV/Div)
Time (50μs/Div)
VID0
(500mV/Div)
Time (50μs/Div)
OVP
VR_Ready
(1V/Div)
SS
(2V/Div)
FB
(1V/Div)
PWM
(5V/Div)
Time (10μs/Div)
20
DS8803A-06 April 2011
RT8803A
Applications Information
RT8803A is a multi-phase DC/DC controller specifically
designed to deliver high quality power for next generation
CPU. RT8803A controls a special power-on sequence &
monitors the thermal condition of VR module to meet the
VRD11 requirement. Phase currents are sensed by
innovative time-sharing DCR current sensing technique
for channel current balance, droop tuning, and over current
protection. Using one common GM amplifier for current
sensing eliminates offset errors and linearity variation
between GMs. As sub-milli-ohm-grade inductors are
widely used in modern mother boards, slight mismatch
of GM amplifiers offset and linearity results in considerable
current shift between phases. The time-sharing DCR
current sensing technique is extremely important to
guarantee phase current balance in mass production.
Converter Initialization, Phase Selection, and
Power Good Function
The RT8803A initiates only after 3 pins are ready: VDD
pin power on reset (POR), VTT/EN pin enabled, and DVD
pin is higher than 1V. VDD POR is to make sure RT8803A
is powered by a voltage for normal work. The rising
threshold voltage of VDD POR is 4.2V typically. At VDD
POR, RT8803A checks PWM3, PWM4 and PWM5 status
to determine phase number of operation. Pull high PWM3
for two-phase operation; pull high PWM4 for three-phase
operation; pull high PWM5 for four-phase operation. The
unused current sense pins should be connected to GND
or left floating.
VTT/EN acts as a chip enable pin and receives signal from
FSB or other power management IC.
DVD is to make sure that ATX12V is ready for drivers to
work normally. Connect a voltage divider from ATX12V to
DVD pin as shown in the Typical Application Circuit. Make
sure that DVD pin voltage is below its threshold voltage
before drivers are ready and above its threshold voltage
for minimum ATX12V during normal operation.
If any one of VDD, VTT/EN, and DVD is not ready, RT8803A
keeps its PWM outputs high impedance and the
companion drivers turn off both upper and lower
MOSFETs. After VDD, VTT/EN, and DVD are ready,
RT8803A initiates its soft start cycle that is compliant
with Intel
®
VRD11 specification as shown in Figure 1. A
time-variant internal current source charges the capacitor
connected to SS pin. SS voltage ramps up piecewise
linearly and locks VID_DAC output with a specified voltage
drop. Consequently, V
CORE
is built up according to
VID_DAC output and meet Intel
®
VRD11 requirement.
VR_READY output is pulled high by external resistor when
V
CORE
reaches VID_DAC output with 1~2ms delay. An
SS capacitor about 47nF is recommend for VRD11
compliance.
VDD POR, DVD, and VTT/EN ready
SS
V
CORE
1.1V
VR_Ready
VID on the fly
1~2ms1~2ms1~2ms
1~2ms
1~2ms
Figure 1. Timming Diagram During Soft Start Interval
Voltage Control
CPU V
CORE
voltage is Kelvin sensed by FB and FBRTN
pins and precisely regulated to VID_DAC output by internal
high gain Error Amplifier (EA). The sensed signal is also
used for power good and over voltage function. The typical
OVP trip point is 170mV above VID_DAC output. RT8803A
pulls PWM outputs low and latches up upon OVP trip to
prevent damaging the CPU. It can only restart by resetting
one of VDD, DVD, or VTT/EN pin.
RT8803A supports Intel VRD10.x, VRD11, AMD K8 and
AMD K8_M2 VID specification.
The change of VID_DAC output at VID on the fly is also
smoothed by capacitor connected to SS pin.
Consequently, Vcore shifts to its new position smoothly
as shown in Figure 2.
DS8803A-06 April
21
RT8803A
PWM3
V
CORE
Consequently, the sensing current I
X
is proportional to
inductor current I
LX
and is expressed as :
I×DCRx
I
X
=
LX
R
CSNX
The sensed current I
X
is used for current balance and droop
tuning as described as followed. Since all phases share
one common GM, GM offset and linearity variation effect
is eliminated in practical applications. As sub-milli-ohm-
grade inductors are widely used in modern mother boards,
slight mismatch of GM amplifiers offset and linearity results
in considerable current shift between phases. The time-
sharing DCR current sensing technical is extremely
important to guarantee phase current balance in mass
production.
Phase Current Balance
The sampled and held phase current I
X
are summed and
averaged to get the averaged current . Each phase
I
X
current I
X
then is compared with the averaged current.
The difference between I
X
and is injected to
I
X
corresponding PWM comparator. If phase current I
X
is
smaller than the averaged current , RT8803A increases
the duty cycle of corresponding phase to increase the
phase current accordingly and vice versa.
VID7
Figure 2. Vcore Response at VID on the Fly
DCR Current Sensing
RT8803A adopts an innovative time-sharing DCR current
sensing technique to sense the phase currents for phase
current balance (phase thermal balance) and load line
regulation as shown in Figure 3. Current sensing amplifier
GM samples and holds voltages VCx across the current
sensing capacitor Cx by turns in a switching cycle.
According to the Basic Circuit Theory, if
Lx
=Rx×Cx then VCx=I×DCRx
LX
DCRx
T1
T2
T3
I
X
= I
LX
x DCR
X
/R
CSNX
I
X
S/H CKT
+
CSA
-
L1
DCR1
R1
C1
+ VC1 -
L3
DCR3
ISP1
T1
T1
ISP3
T3
T3
ISN23
R
CSN3
L2
DCR2
ISN1
R
CSN1
R3
C3
+ VC3 -
CSA: Current Sense Amplifier
R2
ISP2
T2
T2
ISN23
C2
+ VC2 -
R
CSN2
Figure 3
22
DS8803A-06 April 2011
RT8803A
I
OFS
4
If
L
X
=(R
X
//R
PX
)×Cx then
DCRx
VCx=
R
PX
×I
LX
×DCRx
Rx+R
PX
V
CORE
R
FB1
-
+
EACOMP
V
ADJ
DAC
+
-
4I
X
R
ADJ
Figure 4. Load Line and Offset Function
Output Voltage Offset Function
To meet Intel
®
requirement of initial offset of load line,
RT8803A provides programmable initial offset function.
External resistor R
OFS
and voltage source at OFS pin
V
generate offset current
I
OFS
=
OFS
R
OFS
, where V
OFS
is 1V typical. One quarter of I
OFS
flows
through R
FB1
as shown in Figure 4. Error amplifier would
hold the inverting pin equal to V
DAC
- V
ADJ
. Thus output
voltage is subtracted from V
DAC
- V
ADJ
for a constant offset
voltage.
R
FB1
V
CORE
= V
DAC
− V
ADJ
−
4×R
OFS
A positive output voltage offset is possible by connecting
R
OFS
to VDD instead of to GND. Please note that when
R
OFS
is connected to VDD, V
OFS
is V
DD
− 2V typically and
half of I
OFS
flows through R
FB1
. V
CORE
is rewritten as :
V
CORE
= V
DAC
− V
ADJ
+
R
FB1
R
OFS
With other phase kept unchanged, this phase would share
(R
PX
+Rx)/R
PX
times current than other phases. Figure 6
and 7 show different current ratio setting for the power
stage when Phase 3 is programmed 2 times current than
other phases. Figure 8 and 9 compare the above current
ratio setting results.
L
X
DCRx
+
VCx
-
I
LX
Rx
Cx
R
PX
V
OUT
+
T
Figure 5
Current Ratio Setting
Current ratio adjustment is possible as described below.
It is important for achieving thermal balance in practical
application where thermal conditions between phases are
not identical. Figure 5 shows the application circuit of GM
for current ratio requirement. According to Basic Circuit
Theory
R
PX
Rx+R
PX
VCx = ×I
LX
×DCRx
SRx×R
PX
×Cx
+1
Rx+R
PX
Figure 6. GM3 Setting for current ratio function
Figure 7. GM1~2 Setting for current ratio function
DS8803A-06 April
23
RT8803A
Current Ratio Function
35
30
25
Load Line without dead zone at light loads
1.31
I
L3
1.3
1.29
w/o Dead Zone Compensation
R
CSN
open
I
L
(
A
)
20
15
10
I
L2
I
L1
V
C
O
R
E
(
V
)
1.28
1.27
1.26
1.25
R
CSN2
= 82k
w/i Dead Zone Compensation
5
0
0
1.24
1.23
I
OUT
(A)
I
OUT
(A)
Figure 8
Figure 10
Lx
Rx
DCRx
Cx
+
VCx
-
V
OUT
Current Balance Function
35
30
25
I
LX
I
L
(
A
)
20
15
10
5
0
02040
I
L3
GMx
+
-
R
CSN
R
CSN2
I
L2
I
L1
Ix
Figure 11. Application circuit of GM
6080100120
I
OUT
(A)
Referring to Figure 11, I
X
is expressed as :
I
X
=
I
LX_66%
×DCRxI
LX_66%
×DCRx
V
OUT
++
R
CSN2
R
CSN2
R
CSN
Figure 9
Dead Zone Elimination
RT8803A samples and holds inductor current at 50%
period by time-sharing sourcing a current I
X
to R
CSN
. At
light load condition when inductor current is not balance,
voltage VCx
across the sensing capacitor would be
negative. It needs a negative I
X
to sense the voltage.
However, RT8803A CANNOT provide a negative I
X
and
consequently cannot sense negative inductor current. This
results in dead zone of load line performance as shown in
Figure 10. Therefore a technique as shown in Figure 11 is
required to eliminate the dead zone of load line at light
load condition.
(1)
where I
LX_50%
is the of inductor current at 50% period. To
make sure RT8803A could sense the inductor current,
right hand side of Equation (1) should always be positive:
I
LX_66%
×DCRxI
LX_66%
×DCRx
V
OUT
++≥0
R
CSN2
R
CSN2
R
CSN
(2)
Since R
CSN
>> DCRx in practical application, Equation (2)
could be simplified as :
I
LX_66%
×DCRx
V
OUT
≥
R
CSN2
R
CSN
24
DS8803A-06 April 2011
RT8803A
For example, assuming the negative inductor current is
I
LX_50%
= −5A at no load, then for
R
CSN
330Ω, R
ADJ
= 160Ω, V
OUT
= 1.300V
If R
ADJ
is connected as in Figure 14, R
ADJ
= R1 + (R2//
R
NTC
), which is a negative temperature correlated
resistance. By properly selecting R1 and R2, the positive
temperature coefficient of DCR can be canceled by the
negative temperature coefficient of R
ADJ
. Thus the load
line will be thermally compensated.
ADJ
1.3V
≥
−5A×1mΩ
R
CSN2
330Ω
R
CSN2
≤ 85.8kΩ
Choose R
CSN2
= 82kΩ
Figure 10 shows that dead zone of load line at light load
is eliminated by applying this technique.
VR_HOT & VR_FAN Setting
V
CC
5V
R1
R
ADJ
R
NTC
R2
Figure 14. R
ADJ
Connection for Thernal Compensation
R1
V
TSEN
R
NTC
0.28 x V
CC
TSEN
0.39 x V
CC
0.33 x V
CC
+
CMP
-
+
CMP
-
+
CMP
-
Q1
Over Current Protection
Phase current OCP
RT8803A uses an external resistor R
IMAX
connected to
IMAX pin to generate a reference current I
IMAX
for over
current protection :
V
I
IMAX
=
IMAX
R
IMAX
where V
IMAX
is typical 1.0V . OCP comparator compares
each sensed phase current I
X
with this reference current
as shown in Figure 15. Equivalently, the maximum phase
current I
LX(MAX)
is calculated as below:
1
1
I
X(MAX)
=
I
IMAX
2
3
V
I
X(MAX)
=
3
I
IMAX
=
3
×
IMAX
2
R
IMAX
2
R
R
V
I
LX(MAX)
=
I
X
×
CSNX
=
3
×
IMAX
×
CSNX
R
LX
2
R
IMAX
DCR
X
OCP Comparator
Q2
Q3
Figure 12
V
TSEN
V
TSEN
is inversely proportional
to Temperature.
0.39 x V
CC
0.33 x V
CC
0.28 x V
CC
VR_FAN
VR_HOT
Temperature
Figure 13. VR_HOT and VR_FAN Signal vs TSEN Voltage
Load Line Setting and Thermal Compensation
V
ADJ
= Sum(I
X
) x R
ADJ
= (DCR x R
ADJ
/ R
CSN
) x I
OUT
= LL x I
OUT
V
OUT
= V
DAC
− V
ADJ
= V
DAC
− LL x I
OUT
LL = DCR(PTC) x R
ADJ
(NTC) / R
CSN
DCR is the inductor DCR which is a PTC resistance.
+
-
1/3 I
X
1/2 I
IMAX
Figure 15. Over Current Comparator
DS8803A-06 April
25
RT8803A
Error Amplifier Characteristic
For fast response of converter to meet stringent output
current transient response, RT8803A provides large slew
rate capability and high gain-bandwidth performance.
B
4.7k
4.7k
-
EA
+
V
REF
A
EA Falling Slew Rate
Figure 18. Gain-Bandwidth Measurement by signal A
divided by signal B
Design Procedure Suggestion
V
FB
a. Output filter pole and zero (Inductor, output capacitor
value & ESR).
b. Error amplifier compensation & saw-tooth wave
amplitude (compensation network).
V
COMP
CH1:(500mV/Div)
CH2:(2V/Div)
c. Kelvin sense for V
CORE
.
Current Loop Setting
a. GM amplifier S/H current (current sense component
DCR, ISP
X
and ISN
X
pin external resistor value).
b. Over-current protection trip point (R
IMAX
resistor).
VRM Load Line Setting
a. Droop amplitude (ADJ pin resistor).
Time (250ns/Div)
Figure 16. EA Rising Transient with 10pF Loading ;
Slew Rate = 10V/μs
EA Rising Slew Rate
V
FB
b. No load offset (R
CSN
)
c. DAC offset voltage setting (OFS pin & compensation
network resistor).
d. Temperature coefficient compensation(TSEN external
resister & thermistor, resistor between ADJ and GND.)
Power Sequence & SS
V
COMP
CH1:(500mV/Div)
CH2:(2V/Div)
DVD pin external resistor and SS pin capacitor.
PCB Layout
sense for current sense GM amplifier input.
to layout guide for other items.
Time (250ns/Div)
Figure 17. EA Falling Transient with 10pF Loading ;
Slew Rate = 8V/μs
26
DS8803A-06 April 2011
RT8803A
Outline Dimension
D
D2
SEE DETAIL A
L
1
E
E2
e
b
1
2
1
2
A
A3
A1
DETAIL A
Pin #1 ID and Tie Bar Mark Options
Note : The configuration of the Pin #1 identifier is optional,
but must be located within the zone indicated.
Symbol
Dimensions In Millimeters Dimensions In Inches
Min Max Min Max
A 0.800 1.000 0.031 0.039
A1 0.000 0.050 0.000 0.002
A3 0.175 0.250 0.007 0.010
b 0.180 0.300 0.007 0.012
D 4.950 5.050 0.195 0.199
D2 3.400 3.750 0.134 0.148
E 4.950 5.050 0.195 0.199
E2 3.400 3.750 0.134 0.148
e 0.500 0.020
L 0.350 0.450
0.014 0.018
V-Type 32L QFN 5x5 Package
Richtek Technology Corporation
Headquarter
5F, No. 20, Taiyuen Street, Chupei City
Hsinchu, Taiwan, R.O.C.
Tel: (8863)5526789 Fax: (8863)5526611
Richtek Technology Corporation
Taipei Office (Marketing)
5F, No. 95, Minchiuan Road, Hsintien City
Taipei County, Taiwan, R.O.C.
Tel: (8862)86672399 Fax: (8862)86672377
Email:*********************
Information that is provided by Richtek Technology Corporation is believed to be accurate and reliable. Richtek reserves the right to make any change in circuit
design, specification or other related things if necessary without notice at any time. No third party intellectual property infringement of the applications should be
guaranteed by users when integrating Richtek products into any application. No legal responsibility for any said applications is assumed by Richtek.
DS8803A-06 April
27