2024年3月18日发(作者：姓海阳)
元器件交易网
74AUP1G08
Low-power 2-input AND gate
Rev. 02 — 29 June 2006Product data sheet
l description
The 74AUP1G08 is a high-performance, low-power, low-voltage, Si-gate CMOS device,
superior to most advanced CMOS compatible TTL families.
Schmitt-trigger action at all inputs makes the circuit tolerant to slower input riseand fall
times across the entire V
CC
range from 0.8 V to 3.6 V.
This device ensures a very low static and dynamic power consumption across the entire
V
CC
range from 0.8 V to 3.6 V.
This device is fully specified for partial Power-down applications usingI
OFF
.
TheI
OFF
circuitry disables the output, preventing the damaging backflow current through
the device when it is powered down.
The 74AUP1G08 provides the single 2-input AND function.
es
sWide supply voltage range from 0.8 Vto3.6V
sHigh noise immunity
sComplies with JEDEC standards:
xJESD8-12 (0.8 Vto1.3 V)
xJESD8-11 (0.9 Vto1.65V)
xJESD8-7 (1.2 Vto1.95V)
xJESD8-5 (1.8 Vto2.7V)
xJESD8-B (2.7 Vto3.6V)
sESD protection:
xHBM JESD22-A114-C Class 3A. Exceeds 5000V
xMM JESD22-A115-A exceeds 200V
xCDM JESD22-C101-C exceeds 1000V
sLow static power consumption; I
CC
= 0.9µA (maximum)
sLatch-up performance exceeds 100mA per JESD 78 Class II
sInputs accept voltages up to 3.6V
sLow noise overshoot and undershoot < 10 % of V
CC
sI
OFF
circuitry provides partial Power-down mode operation
sMultiple package options
sSpecified from−40°Cto+85°C and−40°Cto+125°C
元器件交易网
Philips Semiconductors
74AUP1G08
Low-power 2-input AND gate
ng information
Table ng information
Package
Temperature rangeName
74AUP1G08GW
74AUP1G08GM
74AUP1G08GF
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
TSSOP5
XSON6
XSON6
Description
plastic thin shrink small outline package; 5 leads;
body width 1.25 mm
Version
SOT353-1
Type number
plasticextremelythinsmalloutlinepackage;noleads;SOT886
6 terminals; body 1×1.45×0.5mm
plasticextremelythinsmalloutlinepackage;noleads;SOT891
6 terminals; body 1×1×0.5mm
g
Table g
Marking code
pE
pE
pE
Type number
74AUP1G08GW
74AUP1G08GM
74AUP1G08GF
onal diagram
A
1
2
B
A
Y
4
1
2
B
mna113
mna114
&
4
Y
mna221
Fig symbolFig logic symbolFig diagram
74AUP1G08_2© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheetRev. 02 — 29 June 20062 of 17
2024年3月18日发(作者：姓海阳)
元器件交易网
74AUP1G08
Low-power 2-input AND gate
Rev. 02 — 29 June 2006Product data sheet
l description
The 74AUP1G08 is a high-performance, low-power, low-voltage, Si-gate CMOS device,
superior to most advanced CMOS compatible TTL families.
Schmitt-trigger action at all inputs makes the circuit tolerant to slower input riseand fall
times across the entire V
CC
range from 0.8 V to 3.6 V.
This device ensures a very low static and dynamic power consumption across the entire
V
CC
range from 0.8 V to 3.6 V.
This device is fully specified for partial Power-down applications usingI
OFF
.
TheI
OFF
circuitry disables the output, preventing the damaging backflow current through
the device when it is powered down.
The 74AUP1G08 provides the single 2-input AND function.
es
sWide supply voltage range from 0.8 Vto3.6V
sHigh noise immunity
sComplies with JEDEC standards:
xJESD8-12 (0.8 Vto1.3 V)
xJESD8-11 (0.9 Vto1.65V)
xJESD8-7 (1.2 Vto1.95V)
xJESD8-5 (1.8 Vto2.7V)
xJESD8-B (2.7 Vto3.6V)
sESD protection:
xHBM JESD22-A114-C Class 3A. Exceeds 5000V
xMM JESD22-A115-A exceeds 200V
xCDM JESD22-C101-C exceeds 1000V
sLow static power consumption; I
CC
= 0.9µA (maximum)
sLatch-up performance exceeds 100mA per JESD 78 Class II
sInputs accept voltages up to 3.6V
sLow noise overshoot and undershoot < 10 % of V
CC
sI
OFF
circuitry provides partial Power-down mode operation
sMultiple package options
sSpecified from−40°Cto+85°C and−40°Cto+125°C
元器件交易网
Philips Semiconductors
74AUP1G08
Low-power 2-input AND gate
ng information
Table ng information
Package
Temperature rangeName
74AUP1G08GW
74AUP1G08GM
74AUP1G08GF
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
TSSOP5
XSON6
XSON6
Description
plastic thin shrink small outline package; 5 leads;
body width 1.25 mm
Version
SOT353-1
Type number
plasticextremelythinsmalloutlinepackage;noleads;SOT886
6 terminals; body 1×1.45×0.5mm
plasticextremelythinsmalloutlinepackage;noleads;SOT891
6 terminals; body 1×1×0.5mm
g
Table g
Marking code
pE
pE
pE
Type number
74AUP1G08GW
74AUP1G08GM
74AUP1G08GF
onal diagram
A
1
2
B
A
Y
4
1
2
B
mna113
mna114
&
4
Y
mna221
Fig symbolFig logic symbolFig diagram
74AUP1G08_2© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheetRev. 02 — 29 June 20062 of 17