2024年11月3日发(作者：殷宜民)
元器件交易网
74F538 1-of-8 Decoder with 3-STATE Outputs
April 1988
Revised August 1999
74F538
1-of-8 Decoder with 3-STATE Outputs
General Description
The 74F538 decoder/demultiplexer accepts three Address
(A
0
–A
2
) input signals and decodes them to select one of
eight mutually exclusive outputs. A polarity control input (P)
determines whether the outputs are active LOW or active
HIGH. A HIGH Signal on either of the active LOW Output
Enable (OE) inputs forces all outputs to the high imped-
ance state. Two active HIGH and two active LOW input
enables are available for easy expansion to 1-of 32 decod-
ing with four packages, or for data demultiplexing to 1-of-8
or 1-of-16 destinations.
Features
sOutput polarity control
sData demultiplexing capability
sMultiple enables for expansion
s3-STATE outputs
Ordering Code:
Order Number
74F538SC
74F538SJ
74F538PC
Package Number
M20B
M20D
N20A
Package Description
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic SymbolsConnection Diagram
IEEE/IEC
© 1999 Fairchild Semiconductor
元器件交易网
7
4
F
5
3
8
Unit Loading/Fan Out
Pin Names
A
0
–A
2
E
1
, E
2
E
3
, E
4
P
OE
1
, OE
2
O
0
–O
7
Description
Address Inputs
Enable Inputs (Active LOW)
Enable Inputs (Active HIGH)
Polarity Control Input
Output Enable Inputs (Active LOW)
3-STATE Outputs
U.L.
HIGH/LOW
1.0/1.0
1.0/1.0
1.0/1.0
1.0/1.0
1.0/1.0
150/40 (33.3)
Input I
IH
/I
IL
Output I
OH
/I
OL
20 µA/−0.6 mA
20 µA/−0.6 mA
20 µA/−0.6 mA
20 µA/−0.6 mA
20 µA/−0.6 mA
−3 mA/24 mA (20 mA)
Truth Table
Function
High
Impedance
Disable
Inputs
OE
1
H
X
L
L
L
L
ActiveHIGH
Output
(P=L)
L
L
L
L
L
L
L
L
ActiveLOW
Output
(P =H)
L
L
L
L
L
L
L
L
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance
Outputs
E
4
X
X
X
X
X
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
A
2
X
X
X
X
X
X
L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H
A
1
X
X
X
X
X
X
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
A
0
X
X
X
X
X
X
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
H
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
L
H
L
L
L
L
L
L
H
L
H
H
H
H
H
H
L
L
H
L
L
L
L
L
H
H
L
H
H
H
H
H
L
L
L
H
L
L
L
L
H
H
H
L
H
H
H
H
L
L
L
L
H
L
L
L
H
H
H
H
L
H
H
H
L
L
L
L
L
H
L
L
H
H
H
H
H
L
H
H
L
L
L
L
L
L
H
L
H
H
H
H
H
H
L
H
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
L
OutputsEqualPInput
O
0
Z
Z
O
1
Z
Z
O
2
Z
O
3
O
4
O
5
Z
Z
O
6
Z
Z
O
7
Z
Z
OE
2
X
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
E
1
X
X
H
X
X
X
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
E
2
X
X
X
H
X
X
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
E
3
X
X
X
X
L
X
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
ZZ
Z
Z
Z
2
元器件交易网
74F538
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
元器件交易网
7
4
F
5
3
8
Absolute Maximum Ratings
(Note 1)
Storage Temperature
Ambient Temperature under Bias
Junction Temperature under Bias
V
CC
Pin Potential to Ground Pin
Input Voltage (Note 2)
Input Current (Note 2)
Voltage Applied to Output
in HIGH State (with V
CC
= 0V)
Standard Output
3-STATE Output
Current Applied to Output
in LOW State (Max)twice the rated I
OL
(mA)
−0.5V to V
CC
−0.5V to +5.5V
−65°C to +150°C
−55°C to +125°C
−55°C to +150°C
−0.5V to +7.0V
−0.5V to +7.0V
−30 mA to +5.0 mA
Recommended Operating
Conditions
Free Air Ambient Temperature
Supply Voltage
0°C to +70°C
+4.5V to +5.5V
Note 1: Absolute maximum ratings are values beyond which the device
may be damaged or have its useful life impaired. Functional operation
under these conditions is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
DC Electrical Characteristics
Symbol
V
IH
V
IL
V
CD
V
OH
Parameter
Input HIGH Voltage
Input LOW Voltage
Input Clamp Diode Voltage
Output HIGH
Voltage
10% V
CC
10% V
CC
5% V
CC
5% V
CC
V
OL
I
IH
I
BVI
I
CEX
V
ID
I
OD
I
IL
I
OZH
I
OZL
I
OS
I
ZZ
I
CCH
I
CCL
I
CCZ
Output LOW
Voltage
Input HIGH Current
Input HIGH Current
Breakdown Test
Output HIGH
Leakage Current
Input Leakage
Test
Output Leakage
Circuit Current
Input LOW Current
Output Leakage Current
Output Leakage Current
Output Short-Circuit Current
Bus Drainage Test
Power Supply Current
Power Supply Current
Power Supply Current
31
37
37
−60
4.75
3.75
−0.6
50
−50
−150
500
45
56
56
10% V
CC
2.5
2.4
2.7
2.7
0.5
5.0
7.0
50
V
µA
µA
µA
V
µA
mA
µA
µA
mA
µA
mA
mA
mA
Min
Max
Max
Max
0.0
0.0
Max
Max
Max
Max
0.0V
Max
Max
Max
VMin
Min
2.0
0.8
−1.2
TypMaxUnits
V
V
VMin
V
CC
Conditions
Recognized as a HIGH Signal
Recognized as a LOW Signal
I
IN
= −18 mA
I
OH
= −1 mA
I
OH
= −3 mA
I
OH
= −1 mA
I
OH
= −3 mA
I
OL
= 20 mA
V
IN
= 2.7V
V
IN
= 7.0V
V
OUT
= V
CC
I
ID
= 1.9 µA
All Other Pins Grounded
V
IOD
= 150 mV
All Other Pins Grounded
V
IN
= 0.5V
V
OUT
= 2.7V
V
OUT
= 0.5V
V
OUT
= 0V
V
OUT
= 5.25V
V
O
= HIGH
V
O
= LOW
V
O
= HIGH Z
4
元器件交易网
74F538
AC Electrical Characteristics
T
A
= +25°C
SymbolParameter
Min
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
Propagation Delay
A
n
to O
n
Propagation Delay
E
1
or E
2
to O
n
Propagation Delay
E
3
or E
4
to O
n
Propagation Delay
P to O
n
Output Enable Time
OE
1
or OE
2
to O
n
Output Disable Time
OE
1
or OE
2
to O
n
6.0
4.0
5.0
4.0
6.0
5.0
6.0
6.0
3.0
5.0
2.0
3.0
V
CC
= +5.0V
C
L
= 50 pF
Typ
11.0
7.5
8.5
6.5
11.0
10.0
11.5
11.0
5.5
9.0
4.0
5.0
Max
16.0
11.0
15.0
9.0
16.0
14.0
18.0
16.0
10.0
13.0
6.0
8.0
T
A
= 0°C to +70°C
V
CC
= +5.0V
C
L
= 50 pF
Min
6.0
4.0
5.0
4.0
6.0
5.0
6.0
6.0
3.0
5.0
2.0
3.0
Max
17.0
12.0
16.0
10.0
17.0
15.0
20.0
17.0
11.0
14.0
7.0
9.0
ns
ns
ns
Units
元器件交易网
7
4
F
5
3
8
Physical Dimensions
inches (millimeters) unless otherwise noted
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
Package Number M20B
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M20D
6
元器件交易网
74F538 1-of-8 Decoder with 3-STATE Outputs
Physical Dimensions
inches (millimeters) unless otherwise noted (Continued)
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Package Number N20A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
7
2.A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
2024年11月3日发(作者：殷宜民)
元器件交易网
74F538 1-of-8 Decoder with 3-STATE Outputs
April 1988
Revised August 1999
74F538
1-of-8 Decoder with 3-STATE Outputs
General Description
The 74F538 decoder/demultiplexer accepts three Address
(A
0
–A
2
) input signals and decodes them to select one of
eight mutually exclusive outputs. A polarity control input (P)
determines whether the outputs are active LOW or active
HIGH. A HIGH Signal on either of the active LOW Output
Enable (OE) inputs forces all outputs to the high imped-
ance state. Two active HIGH and two active LOW input
enables are available for easy expansion to 1-of 32 decod-
ing with four packages, or for data demultiplexing to 1-of-8
or 1-of-16 destinations.
Features
sOutput polarity control
sData demultiplexing capability
sMultiple enables for expansion
s3-STATE outputs
Ordering Code:
Order Number
74F538SC
74F538SJ
74F538PC
Package Number
M20B
M20D
N20A
Package Description
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic SymbolsConnection Diagram
IEEE/IEC
© 1999 Fairchild Semiconductor
元器件交易网
7
4
F
5
3
8
Unit Loading/Fan Out
Pin Names
A
0
–A
2
E
1
, E
2
E
3
, E
4
P
OE
1
, OE
2
O
0
–O
7
Description
Address Inputs
Enable Inputs (Active LOW)
Enable Inputs (Active HIGH)
Polarity Control Input
Output Enable Inputs (Active LOW)
3-STATE Outputs
U.L.
HIGH/LOW
1.0/1.0
1.0/1.0
1.0/1.0
1.0/1.0
1.0/1.0
150/40 (33.3)
Input I
IH
/I
IL
Output I
OH
/I
OL
20 µA/−0.6 mA
20 µA/−0.6 mA
20 µA/−0.6 mA
20 µA/−0.6 mA
20 µA/−0.6 mA
−3 mA/24 mA (20 mA)
Truth Table
Function
High
Impedance
Disable
Inputs
OE
1
H
X
L
L
L
L
ActiveHIGH
Output
(P=L)
L
L
L
L
L
L
L
L
ActiveLOW
Output
(P =H)
L
L
L
L
L
L
L
L
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance
Outputs
E
4
X
X
X
X
X
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
A
2
X
X
X
X
X
X
L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H
A
1
X
X
X
X
X
X
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
A
0
X
X
X
X
X
X
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
H
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
L
H
L
L
L
L
L
L
H
L
H
H
H
H
H
H
L
L
H
L
L
L
L
L
H
H
L
H
H
H
H
H
L
L
L
H
L
L
L
L
H
H
H
L
H
H
H
H
L
L
L
L
H
L
L
L
H
H
H
H
L
H
H
H
L
L
L
L
L
H
L
L
H
H
H
H
H
L
H
H
L
L
L
L
L
L
H
L
H
H
H
H
H
H
L
H
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
L
OutputsEqualPInput
O
0
Z
Z
O
1
Z
Z
O
2
Z
O
3
O
4
O
5
Z
Z
O
6
Z
Z
O
7
Z
Z
OE
2
X
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
E
1
X
X
H
X
X
X
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
E
2
X
X
X
H
X
X
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
E
3
X
X
X
X
L
X
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
ZZ
Z
Z
Z
2
元器件交易网
74F538
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
元器件交易网
7
4
F
5
3
8
Absolute Maximum Ratings
(Note 1)
Storage Temperature
Ambient Temperature under Bias
Junction Temperature under Bias
V
CC
Pin Potential to Ground Pin
Input Voltage (Note 2)
Input Current (Note 2)
Voltage Applied to Output
in HIGH State (with V
CC
= 0V)
Standard Output
3-STATE Output
Current Applied to Output
in LOW State (Max)twice the rated I
OL
(mA)
−0.5V to V
CC
−0.5V to +5.5V
−65°C to +150°C
−55°C to +125°C
−55°C to +150°C
−0.5V to +7.0V
−0.5V to +7.0V
−30 mA to +5.0 mA
Recommended Operating
Conditions
Free Air Ambient Temperature
Supply Voltage
0°C to +70°C
+4.5V to +5.5V
Note 1: Absolute maximum ratings are values beyond which the device
may be damaged or have its useful life impaired. Functional operation
under these conditions is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
DC Electrical Characteristics
Symbol
V
IH
V
IL
V
CD
V
OH
Parameter
Input HIGH Voltage
Input LOW Voltage
Input Clamp Diode Voltage
Output HIGH
Voltage
10% V
CC
10% V
CC
5% V
CC
5% V
CC
V
OL
I
IH
I
BVI
I
CEX
V
ID
I
OD
I
IL
I
OZH
I
OZL
I
OS
I
ZZ
I
CCH
I
CCL
I
CCZ
Output LOW
Voltage
Input HIGH Current
Input HIGH Current
Breakdown Test
Output HIGH
Leakage Current
Input Leakage
Test
Output Leakage
Circuit Current
Input LOW Current
Output Leakage Current
Output Leakage Current
Output Short-Circuit Current
Bus Drainage Test
Power Supply Current
Power Supply Current
Power Supply Current
31
37
37
−60
4.75
3.75
−0.6
50
−50
−150
500
45
56
56
10% V
CC
2.5
2.4
2.7
2.7
0.5
5.0
7.0
50
V
µA
µA
µA
V
µA
mA
µA
µA
mA
µA
mA
mA
mA
Min
Max
Max
Max
0.0
0.0
Max
Max
Max
Max
0.0V
Max
Max
Max
VMin
Min
2.0
0.8
−1.2
TypMaxUnits
V
V
VMin
V
CC
Conditions
Recognized as a HIGH Signal
Recognized as a LOW Signal
I
IN
= −18 mA
I
OH
= −1 mA
I
OH
= −3 mA
I
OH
= −1 mA
I
OH
= −3 mA
I
OL
= 20 mA
V
IN
= 2.7V
V
IN
= 7.0V
V
OUT
= V
CC
I
ID
= 1.9 µA
All Other Pins Grounded
V
IOD
= 150 mV
All Other Pins Grounded
V
IN
= 0.5V
V
OUT
= 2.7V
V
OUT
= 0.5V
V
OUT
= 0V
V
OUT
= 5.25V
V
O
= HIGH
V
O
= LOW
V
O
= HIGH Z
4
元器件交易网
74F538
AC Electrical Characteristics
T
A
= +25°C
SymbolParameter
Min
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
Propagation Delay
A
n
to O
n
Propagation Delay
E
1
or E
2
to O
n
Propagation Delay
E
3
or E
4
to O
n
Propagation Delay
P to O
n
Output Enable Time
OE
1
or OE
2
to O
n
Output Disable Time
OE
1
or OE
2
to O
n
6.0
4.0
5.0
4.0
6.0
5.0
6.0
6.0
3.0
5.0
2.0
3.0
V
CC
= +5.0V
C
L
= 50 pF
Typ
11.0
7.5
8.5
6.5
11.0
10.0
11.5
11.0
5.5
9.0
4.0
5.0
Max
16.0
11.0
15.0
9.0
16.0
14.0
18.0
16.0
10.0
13.0
6.0
8.0
T
A
= 0°C to +70°C
V
CC
= +5.0V
C
L
= 50 pF
Min
6.0
4.0
5.0
4.0
6.0
5.0
6.0
6.0
3.0
5.0
2.0
3.0
Max
17.0
12.0
16.0
10.0
17.0
15.0
20.0
17.0
11.0
14.0
7.0
9.0
ns
ns
ns
Units
元器件交易网
7
4
F
5
3
8
Physical Dimensions
inches (millimeters) unless otherwise noted
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
Package Number M20B
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M20D
6
元器件交易网
74F538 1-of-8 Decoder with 3-STATE Outputs
Physical Dimensions
inches (millimeters) unless otherwise noted (Continued)
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Package Number N20A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
7
2.A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.