2024年10月25日发(作者：李又香)

元器件交易网

ADVANCE INFORMATION Data Sheet No. PD60164A

IR1110

SOFT START CONTROLLER IC

Features

•

Self-contained soft charging of DC bus capacitor

•

DC bus voltage regulation

•

3-phase or 1-phase AC input

•

Applicable to 115/230/380/460/575V AC input

•

Drives SCR phase controlled half bridge

•

Programmable ramp rate

•

Protection against DC bus short circuit

•

Fast power dip ride through with automatic ramp back

•

Selectable shutdown on single phase loss

•

1-phase and 3-phase loss fault output

•

Insensitive to phase rotation

•

High line or low line fault output

•

Low power consumption

•

Integrated watchdog function for each phase

•

64-pin MQFP package

Product Summary

V

DDS

/V

SS

DC bus registration

response time

+/- 5V

I

SS

/I

DD

+/- 5mA

100msec (typ.)

Min. DC bus regulation 35% of V

DCMAX

voltage with capacitive load

Programmable

DC bus ramp time

100msec to

330msec (typ.)

Description

The IR1110 is a high performance analog IC designed

to control ramp rate and voltage of the DC bus from

either single or three phase AC line voltage input. It con-

trols a SCR half bridge and provides robust ride through

capability in event of transient loss of line, and DC bus

regulation with eternal reference input. Comprehensive

line status fault output including 1/3 phase loss and high

or low line fault provides versatile line diagnostic capa-

bility to the system. The IR1110 is based on advanced

low power design so it can utilize the SCR snubber

derived power supply.

Package

64 Lead MQFP

System Block Diagram

Snubber and

Snubber derived

power supply

IR1110

and

Peripheral

Components

(Optional)

+

AC

3-Phase

Input

(Optional)

-

元器件交易网

IR1110

Absolute Maximum Ratings

Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage param-

eters are absolute voltages referenced to AGND and DGND, all currents are defined positive into any lead. The thermal

resistance and power dissipation ratings are measured under board mounted and still air conditions.

Symbol Definition

V

DD

V

SS

V

IN

V

BIN

V

LED

V

LNSET

I

LED

Rth

JA

T

A

T

J

T

S

T

L

Positive supply voltage

Negative supply voltage

Operating input voltage range on UIN,VIN & WIN pins

Operating input voltage on VBOS and VBNEG

Operating input voltage on 1PHLED, LNLED, and LNLSLED pins

Operating input voltage on LNSET

Sinking current on 1PHLED, LNLED, and LNLSLED pins

Thermal resistance, junction to ambient

Operating ambient temperature

Junction temperature

Storage temperature

Lead temperature (soldering, 10 seconds)

Min.

—

—

(V

SS

+ 0.4)

- 4.5

—

—

—

—

-40

—

-55

—

Max.

6.0

-6.0

(V

DD

- 0.4)

3.0

V

DD

(V

DD

- 0.4)

3

60

85

150

150

300

Units

V

mA

°C/W

°C

Recommended Component Values

All capacitors are rated 6.3V unless otherwise specified. All resistors are rated 1/16W unless otherwise specified. The

typical connection diagram is shown in figure 3. For proper operation the device should be used with the recommended

components specified below.

Symbol Definition

Q

U

Q

V

Q

W

R

U1

R

V1

R

W1

R

B

R

U2

R

V2

R

W2

R

ERR

R

CLAMP1

R

CLAMP2

R

RAMP

DC bus regulation error resistor

Ramp clamp resistor 1

Ramp clamp resistor 2

Ramp resistor

Bias resistor

Resistor divider for input voltage

Resistor divider for input voltage

Phase U/V/W complementary MOSFET

Typ.

IRF7509

ToleranceUnitsComments

Complementary

NMOS/PMOS

Driver

3.4 X

VACrms

max

249k

9.09k

1%

.25W

1%

1%

kΩNote 1

Ω

2M

430k

100k

82k

5%

5%

5%

5%

2

元器件交易网

IR1110

Symbol Definition

R

PKLL1

R

PKLL2

R

DIP1

R

DIP2

R

DFIL

R

PKD

R

PKFIL

R

POS1

R

NEG1

R

POS2

R

NEG2

R

WDU

R

WDV

R

WDW

R

LS1

R

LS2

R

SG1

R

SG2

R

INTU

R

INTV

R

INTW

R

INTRU

R

INTRV

R

INTRW

R

LED1

R

LED2

R

U,

R

V,

R

W

R

GU

R

GV

R

GW

R

DU

R

DV

R

DW

Phase U/V/W SCR driver filter resistor

LNLSLED pin resistor for opto interface

LNLED pin resistor for opto interface

Phase U/V/W SCR driver pull-up resistor

Phase U/V/W SCR driver output resistor

Phase U/V/W integrator reset resistor

Line fault output reference divider resistor 1

Line fault output reference divider resistor 2

SCR firing anode voltage reference resistor 1

SCR firing anode voltage reference resistor 2

Phase U/V/W integrator resistor

Line voltage peak holding resistor 1

Line voltage peak holding resistor 2

Voltage dip resistor 1

Voltage dip resistor 2

Voltage dip filter resistor

Timing wave peak voltage discharge resistor

Timing wave peak voltage filter resistor

Resistor divider for DC bus voltage input

Feedback resistor for DC bus voltage Amp

Resistor divider for DC bus voltage

Phase U/V/W watchdog resistor

Typ.

2.2M

6.8M

332k

1.0M

15k

1M

56k

3.2 X

9.09k

9.09k

845k

ToleranceUnits

5%

5%

1%

1%

5%

5%

5%

1%

.5W

1%

1%

1%

kΩ

Ω

Comments

Note 1,2

VACrmsmax

Note 3

357k

78.7k

0.82k X

10k

1M

1%

1%

1%

1%

1%

Note 4

VACrmsmax

Ω

33.2k

1%

6.2k

6.2k

5.6k

33

5%

5%

5%

5%

.25W

470

5%

.

3

元器件交易网

IR1110

Recommended Operating Conditions cont.

All capacitors are rated 6.3V unless otherwise specified. All resistors are rated 1/16W unless otherwise specified. The

typical connection diagram is shown in figure 3. For proper operation the device should be used with the recommended

componens specified below.

Symbol Definition

C

UVLO

C

1PH

C

3PH

C

ERR

C

RAMP

C

PKLL

C

BDIP1

C

BDIP2

C

HOLD

C

PK

C

WDU

C

WDV

C

WDW

C

INTU

C

INTV

C

INTW

C

U,

C

V,

C

W

D

RAMP

Capacitor between CINTU/V/W and

INTNU/V/W

Capacitor on UVLOCAP pin

Capacitor on 1PHCAP pin

Capacitor on 3PHCAP pin

Capacitor on DCREGC pin

Capacitor on CRAMP pin

Capacitor on VPKLL pin

Capacitor on BDIP1

Capacitor on BDIP2

Capacitor on BDIPHLD

Capacitor on VPK

Capacitor on WDCAPU, WDCAPV, and

WDCAPW

Typ.

.1

.001

.022

.22

1.0

.1

3300

1000

.33

.33

.027

ToleranceUnits

5%

5%

5%

10%

10%

10%

5%

5%

10%

10%

2%

µF

PF

µF

Comments

.00822%

Capacitor in SCR driver circuit .0047/25V

Diode in series with RRAMPIN4148

10%

Opto1,Opto2Fault output opto couplers HCPL0701

Note 1) Power rating is based on 550VAC rms maximum. For lower AC line voltage, power can be reduced proportionally. Vac

rms max = Maximum operating RMS value of AC line voltage. Use the nearest standard 1% value to calculated value. Resistor

must be rated for peak line voltage.

Note 2) R

POS2

is not required if no series inductor(s) in place on positive DC bus. Resistor must be rated for peak line voltage.

Note 3) V

DD

= 5.0V

±

2.5%. If 5.1V

±

2% zener diode sets V

DD

, use 866k 1%.

Note 4) With these values LNLED is used for low line detection and is low at line voltage greater than approximately 57% of

Vacrms maximum voltage.

Note 5) Use the nearest standard 1% value to calculated value.

Note 6) C

RAMP

and R

RAMP

sets the bus voltage ranp-up time. Minimum value of C

RAMP

is 0.68µF, maximum value is

3.3µF. See Operation Description - Ramp Circuit.

Special Mode of Operation

1. Dedicated single phase operation

For operation with a one-phase bridge, connect 1PHSEL (pin12) to V

SS

. Use the U and V inputs. Connect WIN (pin3) to

ground. Use the SCRU (pin47) and SCRV (pin46) outputs. Use R

PKD

= 3.0MΩ, R

WDU,

R

WDV = 1.0

MΩ , CINTU,CINTV =

0.0068υF 2%.

The following components can be omitted: R

W1

, R

W2

, R

WDW

, C

WDW

, R

INTW

, R

INTRW

, C

INTW

.

2. Operation without DC bus voltage regulation

For operation without bus voltage, ie. maximum DC bus voltage only, connect VBREF (pin8) to VSS. RERR and CERR can

be omitted. Connect DCREGC (pin10) to ground.

4

元器件交易网

IR1110

DC Electrical Characteristics

R

BIAS

= 249K/1%, V

DD

= 5.1V, V

SS

= 5.1V and T

A

= 25°C unless otherwise specified.

Symbol

V

DD

V

SS

I

DD

I

SS

V

IN

V

BREF

V

IL1

V

IH1

V

PCINT

V

PCR+

V

PCR-

I

1PHCAP+

I

1PHCAP-

I

3PHCAP+

I

3PHCAP-

VOL

LED

VOH

LED

UVLO

I

UVLO+

VH

SCR

VL

SCR

V

RAMPBUF

R

VBREF

I

BDIPCAP

V

t

LNLED+

V

t

LNLED-

V

t

LNLS

V

t

1PH

Definition

Positive Supply Voltage

Negative Supply Voltage

V

DD

Supply Current

V

SS

Supply Current

Input Voltage Range for UIN, VIN, and WIN

Input Voltage Range for VBREF

Input logic low voltage on 1PHEN, LNLSSL

Input logic high voltage on 1PHEN, LNLSSL

Positive Output Voltage Swing at CINTU, CINTV,

and CINTW Pins

Positive Output Voltage Swing at CRAMP Pin

Negative Output Voltage Swing at CRAMP Pin

Sourcing Current at 1PHCAP pin

Sinking Current at 1PHCAP pin

Sourcing Current at 3PHCAP pin

Sinking Current at 3PHCAP pin

Output Low Voltage at 1PHLED, LNLSLED, and

LNLED pins

Output High Voltage at 1PHLED, LNLSLED,

and LNLSLED pin

Undervoltage lockout between VDD-GND

Sinking Current at UVLOCAP pin

Output Voltage at High level at SCRU, SCRV,

and SCRW pins

Output Voltage at Low level at SCRU, SCRV,

and SCRW pins

Output Voltage at VRAMP pin

Input Resistance On VBREF pin

Sourcing Current of BDIPCAP pin

Peak threshold voltage on UIN/VIN/WIN pins

for LNLED to switch low

Peak threshold voltage on UIN/VIN/WIN pins

for LNLED to switch high

Peak threshold voltage on UIN/VIN/WIN pins

for LNLSLED to stay low

Peak threshold voltage on UIN/VIN/WIN pins

for 1PHLED to stay low

est Conditions

4.8

-4.8

—-

—-

1.5

0

—-

2.2

—-

—-

0

—-

—-

—-

—-

0

V

DD

0.4

4.1

60

—-

—-

—-

—-

—-

2.2

2.0

—-

—-

4.4

86

4.5

0.1

4.0

400

5

2.3

2.1

.5

.5

4.6

110

—-

0.31

—-

—-

—-

2.4

2.2

—-

V

—-

k

Ω

uABDIPCAP=VSS

VLNSET = 1.0V

Note 2

All input voltages

present

All input voltages

present

V

uAVUVLOCAP=VDD

I

O

= 1mA

I

O

= -1mA

5.1

-5.1

3.0

-3.0

—-

—-

—-

—-

4.0

4.0

—-

2.0

5.0

3.0

15.0

0.12

—-

5.6

-5.6

6.0

-5.0

4.0

5.0

-2.0

—-

4.5

4.5

—-

—-

—-

—-

—-

.4

V

DD

V

µA

1PHCAP=VSS

1PHCAP=GND

3PHCAP=VSS

3PHCAP=GND

Output sinking

current = 3.0mA

Output sourcing

current = 3mA

V

Peak voltage of Vin

= 4.0V

Note 1

mA

V

Note 3

Note 3

Note 4

Note 4

See notes on page 6

5

元器件交易网

IR1110

Notes for DC Electrical Characteristics

Note 1) VBREF=5.0V will assure full SCR firing on to produce the maximum amount of DC bus voltage and faster conver-

gence to the maximum DC bus voltage. Although VBREF=4.0V corresponds to the maximum voltage, it will take longer time

to converge to the maximum DC bus voltage.

Note 2) These voltage values are linearly proportional to VLNSET. For example, if VLNSET = 2.0V, then all values are twice

of those values listed in the table.

Note 3) VDD must be regulated within ±2.5%. VSS must be regulated within ±5%.

Symbol

t

r

t

f

t

WSCR

t

DLL

Definition

Turn-on rise time on SCRU, SCRV, and SCRW

Turn-off fall time on SCRU, SCRV, and SCRW

Output pulse width of SCRU,SCRV, and SCRW

LNLSLED propagation delay

est Conditions

—-

—-

—-

—-

500

500

15

30

—-

—-

—-

—-

ns

µs

LNLSSL=VDD,

C3PH =.022uF,

(note 1)

t

D1PH

t

LN

t

S1PH

1PHLED propagation delay

LNLED propagation delay

Shutdown time after loss of single phase

—-

—-

—-

8.3

150

15

—-

—-

20

ms

ms

C1PH = .001uF

(note 2)

1PHEN = VDD,

CUVLO = .1

m

F,

C1PH = .001

m

F,

(note 3)

t

f

FO

t

W1PH

t

UVLCK

t

RAMP

V

ENSCR

P

PUBAL

Fall time from high to low on LNLSLED,

1PHLED, LNLED

1PHLED pulse width

Power up UVLOCK delay

DC bus ramp time

Minimum input voltage on UIN, VIN, and WIN

for enabling SCR firing

Phase-to-phase unbalance between

pulses on SCRU, SCRV, and SCRW

—-

—-

50

2

60

150

—-

—-

ns

Pull-up resistor

= 6.2k

W

C1PH =.001

m

F,

(note 4)

msec

CUVLCK=.1uF,

(note 5)

C

RAMP

=1uF,

R

RAMP

=82k,(note 6)

—-

—-

—-

R

U2

/R

U1

—-

X 12

±

1.5

±

3

—-

V

(note 7)

Firing angle = 90

°

o

Notes 8 and 9

Firing angle = 140

°

Note 9

—-

°

6

元器件交易网

IR1110

Notes for AC Electrical Characteristics

Note 1) Delay is proportional to the capacitor values with minimum allowed value of C

3PH

= .01µF

Note 2) Depends on C

PKLL

charge condition

Note 3) C

UVLO

= .1µF, C

1PH

= .001µF. Increasing C

UVLO

increases the delay/response time of the 1phase lockout.

Note 4) Pulse width is proportional to C1PH. Maximum allowed values of C

1PH

is .001µF.

Note 5) Power up delay is set by C

UVLO

or by V

DD

rise time whichever takes longer. In this condition, V

DD

rise time must

not be less than 100msec, and 1-phase shutdown must be enabled. If this is less than 100msec or 1-phase shut

down is disabled, C

UVLO

must be increased to 0.22µF in order to increase the undervoltage lockout time to greater

than 100msec. See Note 3) above on additional effect of increasing C

UVLO

.

Note 6) Ramp time is proportional to the capacitor value.

Note 7) This value corresponds approximately to 15V minimum SCR firing voltage. For 15V minimum SCR firing voltage,

(R

SG2

/R

SG1

) X V

DD

= (

R

U2

/R

U1

) X 15.

Note 8) PPUBAL applies to steady operation, is deviation of any firing point to closest balanced set of firing points.

Note 9) Firing angle is defined with respect to zero delay (ie. max output voltage.

System Operating Characteristics and Specifications

All peripheral component values are those listed in the recommended operating condition unless otherwise specified.

Symbol

V

AC

Definition

Line-to-line AC voltage range (1%)

est Conditions

80

161

322

120

230

460

50/60

—-

2

100

150

140

276

552

63

99.8

—-

—-

—-

V

RMS

R

u1

,R

v1

,R

w1

=475K

R

POS1

,R

NEG1

=453K

R

u1

,R

v1

,R

w1

9537K

R

POS1

,R

NEG1

=887K

R

u1

,R

v1

,R

w1

=2X953K

R

POS1

,R

NEG1

=887K

f

LINE

V

BRANGE

V

BREG

V

BRES

t

RAMP1

Input line frequency

DC bus voltage controllable range

DC bus voltage regulation

DC bus voltage step response time

DC bus voltage ramp up time at power up

47

35

—-

—-

—

t

RAMP2

DC bus voltage ramp up time at power dip

ride through

Power up delay time before ramp up

—-75—-

t

d

PWR

—-190—-

t

d

DIP1

Delay time to start ramp-up after recovery from

a transient loss of line voltage

Firing angle range

Delay time to shutdown SCR firing pulses after

loss of one phase input

Delay time to start ramp-up after recovery from a

loss of one phase input

1.5

15

—-

15

a

FIRE

t

d

1PHS

t

d

1PHE

—-

—-

30

160

30

—-

Hz

%V

BREF

=1.4V to 4V

%

msec V

BUS

=35% to 100%

Note 6

msec C

RAMP

= 1

µ

F

R

RAMP

= 82k

(Note 7)

msecC

RAMP

= 1

µ

F

R

RAMP

= 82k

(Note 7)

msecC

RAMP

= 1

µ

F

C

UVLO

= 0.1

µ

F

Note 9)

msec Voltage drop below

the reference voltage

at B

DIP2

pin

°

Figure 2, Note 14

msec1PHEN = V

DD

msec1PHEN = V

DD

7

元器件交易网

IR1110

System Operating Characteristics and Specifications

All peripheral component values are those listed in the recommended operating condition unless otherwise specified.

t

d

1FIRE

First SCR firing angle at ramp-up—20CRAMP=1

µ

F,

R

RAMP

= 82k

(Note 10)

°

25CRAMP=2.2

µ

F,

R

RAMP

= 47k

(Note 10)

°

22CRAMP=3.3

µ

F,

R

RAMP

= 30k

(Notes10,12, 13)

20

°

CRAMP = 1

µ

F,

R

RAMP

= 82k

14CRAMP=3.3

µ

F,

R

RAMP

= 30k

(Notes 11 and 13)

32

°

16

14

RLIM

FIRE

Rate of advance of firing angle from last max firing

angle during ramp-up

—-10

7

Notes for System Operating Characteristics

Note 6) Step change of V

BREF

may result in excessive bus capacitor charging current. Rate of change of V

BREF

should

be decreased in order to limit bus capacitor charging current for practical application.

Note 7) Time to ramp up to 99.8% DC bus level at a power up. It does not include the power up delay time. The practical

limitation of the minimum time (50msec) depends on the inrush current to the DC bus capacitor. Ramp time is

proportional to C

RAMP

.

Note 8) Time to ramp back to 99.8% DC bus level from 50% DC bus level at a momentary power dip. This does not

include the delay time to start ramp-up (t

DDIP

)

Note 9) The value depends on C

UVLCK

Note 10) The value depends on C

RAMP

, R

PK

, R

RAMP

Note 11)The value depends on C

RAMP

Note 12)See operation description - Ramp Circuit

Note 13)Firing angle defined with respect to fully off (zero output voltage) firing angle.

Note 14)Firing angle defined with respect to zero delay.

8

元器件交易网

uld

IR1110

Note 1) LNLSLED may toggle high once for 2msec after event of phase loss.

Note 2) 1PHLED and LNLSLED are completely synchronized and complementary.

9

ctical

e is

元器件交易网

IR1110

3

Firing

voltage

reference

COMP

LINE

VOLTAGE

3

Line Voltage

Processing

3

Line Sync

&

Timing wave

generator

Timing wave

Watchdog

3

3

COMP

SCR

FIRING

PULSES

Single Phase

Phase Loss

Detect

High/Low

Line Fault

+

-

Line Loss

Ramp

Clamp

Amp

ENABLE

Ramp

Generator

Timing wave

Reference

Generator

VBUS

Vbus Dip

Detector

RESET

VBUS

REF

+

-

Error

Amp

1

1 + s

τ

Figure 1

Firing Angle,

2024年10月25日发(作者：李又香)

元器件交易网

ADVANCE INFORMATION Data Sheet No. PD60164A

IR1110

SOFT START CONTROLLER IC

Features

•

Self-contained soft charging of DC bus capacitor

•

DC bus voltage regulation

•

3-phase or 1-phase AC input

•

Applicable to 115/230/380/460/575V AC input

•

Drives SCR phase controlled half bridge

•

Programmable ramp rate

•

Protection against DC bus short circuit

•

Fast power dip ride through with automatic ramp back

•

Selectable shutdown on single phase loss

•

1-phase and 3-phase loss fault output

•

Insensitive to phase rotation

•

High line or low line fault output

•

Low power consumption

•

Integrated watchdog function for each phase

•

64-pin MQFP package

Product Summary

V

DDS

/V

SS

DC bus registration

response time

+/- 5V

I

SS

/I

DD

+/- 5mA

100msec (typ.)

Min. DC bus regulation 35% of V

DCMAX

voltage with capacitive load

Programmable

DC bus ramp time

100msec to

330msec (typ.)

Description

The IR1110 is a high performance analog IC designed

to control ramp rate and voltage of the DC bus from

either single or three phase AC line voltage input. It con-

trols a SCR half bridge and provides robust ride through

capability in event of transient loss of line, and DC bus

regulation with eternal reference input. Comprehensive

line status fault output including 1/3 phase loss and high

or low line fault provides versatile line diagnostic capa-

bility to the system. The IR1110 is based on advanced

low power design so it can utilize the SCR snubber

derived power supply.

Package

64 Lead MQFP

System Block Diagram

Snubber and

Snubber derived

power supply

IR1110

and

Peripheral

Components

(Optional)

+

AC

3-Phase

Input

(Optional)

-

元器件交易网

IR1110

Absolute Maximum Ratings

Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage param-

eters are absolute voltages referenced to AGND and DGND, all currents are defined positive into any lead. The thermal

resistance and power dissipation ratings are measured under board mounted and still air conditions.

Symbol Definition

V

DD

V

SS

V

IN

V

BIN

V

LED

V

LNSET

I

LED

Rth

JA

T

A

T

J

T

S

T

L

Positive supply voltage

Negative supply voltage

Operating input voltage range on UIN,VIN & WIN pins

Operating input voltage on VBOS and VBNEG

Operating input voltage on 1PHLED, LNLED, and LNLSLED pins

Operating input voltage on LNSET

Sinking current on 1PHLED, LNLED, and LNLSLED pins

Thermal resistance, junction to ambient

Operating ambient temperature

Junction temperature

Storage temperature

Lead temperature (soldering, 10 seconds)

Min.

—

—

(V

SS

+ 0.4)

- 4.5

—

—

—

—

-40

—

-55

—

Max.

6.0

-6.0

(V

DD

- 0.4)

3.0

V

DD

(V

DD

- 0.4)

3

60

85

150

150

300

Units

V

mA

°C/W

°C

Recommended Component Values

All capacitors are rated 6.3V unless otherwise specified. All resistors are rated 1/16W unless otherwise specified. The

typical connection diagram is shown in figure 3. For proper operation the device should be used with the recommended

components specified below.

Symbol Definition

Q

U

Q

V

Q

W

R

U1

R

V1

R

W1

R

B

R

U2

R

V2

R

W2

R

ERR

R

CLAMP1

R

CLAMP2

R

RAMP

DC bus regulation error resistor

Ramp clamp resistor 1

Ramp clamp resistor 2

Ramp resistor

Bias resistor

Resistor divider for input voltage

Resistor divider for input voltage

Phase U/V/W complementary MOSFET

Typ.

IRF7509

ToleranceUnitsComments

Complementary

NMOS/PMOS

Driver

3.4 X

VACrms

max

249k

9.09k

1%

.25W

1%

1%

kΩNote 1

Ω

2M

430k

100k

82k

5%

5%

5%

5%

2

元器件交易网

IR1110

Symbol Definition

R

PKLL1

R

PKLL2

R

DIP1

R

DIP2

R

DFIL

R

PKD

R

PKFIL

R

POS1

R

NEG1

R

POS2

R

NEG2

R

WDU

R

WDV

R

WDW

R

LS1

R

LS2

R

SG1

R

SG2

R

INTU

R

INTV

R

INTW

R

INTRU

R

INTRV

R

INTRW

R

LED1

R

LED2

R

U,

R

V,

R

W

R

GU

R

GV

R

GW

R

DU

R

DV

R

DW

Phase U/V/W SCR driver filter resistor

LNLSLED pin resistor for opto interface

LNLED pin resistor for opto interface

Phase U/V/W SCR driver pull-up resistor

Phase U/V/W SCR driver output resistor

Phase U/V/W integrator reset resistor

Line fault output reference divider resistor 1

Line fault output reference divider resistor 2

SCR firing anode voltage reference resistor 1

SCR firing anode voltage reference resistor 2

Phase U/V/W integrator resistor

Line voltage peak holding resistor 1

Line voltage peak holding resistor 2

Voltage dip resistor 1

Voltage dip resistor 2

Voltage dip filter resistor

Timing wave peak voltage discharge resistor

Timing wave peak voltage filter resistor

Resistor divider for DC bus voltage input

Feedback resistor for DC bus voltage Amp

Resistor divider for DC bus voltage

Phase U/V/W watchdog resistor

Typ.

2.2M

6.8M

332k

1.0M

15k

1M

56k

3.2 X

9.09k

9.09k

845k

ToleranceUnits

5%

5%

1%

1%

5%

5%

5%

1%

.5W

1%

1%

1%

kΩ

Ω

Comments

Note 1,2

VACrmsmax

Note 3

357k

78.7k

0.82k X

10k

1M

1%

1%

1%

1%

1%

Note 4

VACrmsmax

Ω

33.2k

1%

6.2k

6.2k

5.6k

33

5%

5%

5%

5%

.25W

470

5%

.

3

元器件交易网

IR1110

Recommended Operating Conditions cont.

All capacitors are rated 6.3V unless otherwise specified. All resistors are rated 1/16W unless otherwise specified. The

typical connection diagram is shown in figure 3. For proper operation the device should be used with the recommended

componens specified below.

Symbol Definition

C

UVLO

C

1PH

C

3PH

C

ERR

C

RAMP

C

PKLL

C

BDIP1

C

BDIP2

C

HOLD

C

PK

C

WDU

C

WDV

C

WDW

C

INTU

C

INTV

C

INTW

C

U,

C

V,

C

W

D

RAMP

Capacitor between CINTU/V/W and

INTNU/V/W

Capacitor on UVLOCAP pin

Capacitor on 1PHCAP pin

Capacitor on 3PHCAP pin

Capacitor on DCREGC pin

Capacitor on CRAMP pin

Capacitor on VPKLL pin

Capacitor on BDIP1

Capacitor on BDIP2

Capacitor on BDIPHLD

Capacitor on VPK

Capacitor on WDCAPU, WDCAPV, and

WDCAPW

Typ.

.1

.001

.022

.22

1.0

.1

3300

1000

.33

.33

.027

ToleranceUnits

5%

5%

5%

10%

10%

10%

5%

5%

10%

10%

2%

µF

PF

µF

Comments

.00822%

Capacitor in SCR driver circuit .0047/25V

Diode in series with RRAMPIN4148

10%

Opto1,Opto2Fault output opto couplers HCPL0701

Note 1) Power rating is based on 550VAC rms maximum. For lower AC line voltage, power can be reduced proportionally. Vac

rms max = Maximum operating RMS value of AC line voltage. Use the nearest standard 1% value to calculated value. Resistor

must be rated for peak line voltage.

Note 2) R

POS2

is not required if no series inductor(s) in place on positive DC bus. Resistor must be rated for peak line voltage.

Note 3) V

DD

= 5.0V

±

2.5%. If 5.1V

±

2% zener diode sets V

DD

, use 866k 1%.

Note 4) With these values LNLED is used for low line detection and is low at line voltage greater than approximately 57% of

Vacrms maximum voltage.

Note 5) Use the nearest standard 1% value to calculated value.

Note 6) C

RAMP

and R

RAMP

sets the bus voltage ranp-up time. Minimum value of C

RAMP

is 0.68µF, maximum value is

3.3µF. See Operation Description - Ramp Circuit.

Special Mode of Operation

1. Dedicated single phase operation

For operation with a one-phase bridge, connect 1PHSEL (pin12) to V

SS

. Use the U and V inputs. Connect WIN (pin3) to

ground. Use the SCRU (pin47) and SCRV (pin46) outputs. Use R

PKD

= 3.0MΩ, R

WDU,

R

WDV = 1.0

MΩ , CINTU,CINTV =

0.0068υF 2%.

The following components can be omitted: R

W1

, R

W2

, R

WDW

, C

WDW

, R

INTW

, R

INTRW

, C

INTW

.

2. Operation without DC bus voltage regulation

For operation without bus voltage, ie. maximum DC bus voltage only, connect VBREF (pin8) to VSS. RERR and CERR can

be omitted. Connect DCREGC (pin10) to ground.

4

元器件交易网

IR1110

DC Electrical Characteristics

R

BIAS

= 249K/1%, V

DD

= 5.1V, V

SS

= 5.1V and T

A

= 25°C unless otherwise specified.

Symbol

V

DD

V

SS

I

DD

I

SS

V

IN

V

BREF

V

IL1

V

IH1

V

PCINT

V

PCR+

V

PCR-

I

1PHCAP+

I

1PHCAP-

I

3PHCAP+

I

3PHCAP-

VOL

LED

VOH

LED

UVLO

I

UVLO+

VH

SCR

VL

SCR

V

RAMPBUF

R

VBREF

I

BDIPCAP

V

t

LNLED+

V

t

LNLED-

V

t

LNLS

V

t

1PH

Definition

Positive Supply Voltage

Negative Supply Voltage

V

DD

Supply Current

V

SS

Supply Current

Input Voltage Range for UIN, VIN, and WIN

Input Voltage Range for VBREF

Input logic low voltage on 1PHEN, LNLSSL

Input logic high voltage on 1PHEN, LNLSSL

Positive Output Voltage Swing at CINTU, CINTV,

and CINTW Pins

Positive Output Voltage Swing at CRAMP Pin

Negative Output Voltage Swing at CRAMP Pin

Sourcing Current at 1PHCAP pin

Sinking Current at 1PHCAP pin

Sourcing Current at 3PHCAP pin

Sinking Current at 3PHCAP pin

Output Low Voltage at 1PHLED, LNLSLED, and

LNLED pins

Output High Voltage at 1PHLED, LNLSLED,

and LNLSLED pin

Undervoltage lockout between VDD-GND

Sinking Current at UVLOCAP pin

Output Voltage at High level at SCRU, SCRV,

and SCRW pins

Output Voltage at Low level at SCRU, SCRV,

and SCRW pins

Output Voltage at VRAMP pin

Input Resistance On VBREF pin

Sourcing Current of BDIPCAP pin

Peak threshold voltage on UIN/VIN/WIN pins

for LNLED to switch low

Peak threshold voltage on UIN/VIN/WIN pins

for LNLED to switch high

Peak threshold voltage on UIN/VIN/WIN pins

for LNLSLED to stay low

Peak threshold voltage on UIN/VIN/WIN pins

for 1PHLED to stay low

est Conditions

4.8

-4.8

—-

—-

1.5

0

—-

2.2

—-

—-

0

—-

—-

—-

—-

0

V

DD

0.4

4.1

60

—-

—-

—-

—-

—-

2.2

2.0

—-

—-

4.4

86

4.5

0.1

4.0

400

5

2.3

2.1

.5

.5

4.6

110

—-

0.31

—-

—-

—-

2.4

2.2

—-

V

—-

k

Ω

uABDIPCAP=VSS

VLNSET = 1.0V

Note 2

All input voltages

present

All input voltages

present

V

uAVUVLOCAP=VDD

I

O

= 1mA

I

O

= -1mA

5.1

-5.1

3.0

-3.0

—-

—-

—-

—-

4.0

4.0

—-

2.0

5.0

3.0

15.0

0.12

—-

5.6

-5.6

6.0

-5.0

4.0

5.0

-2.0

—-

4.5

4.5

—-

—-

—-

—-

—-

.4

V

DD

V

µA

1PHCAP=VSS

1PHCAP=GND

3PHCAP=VSS

3PHCAP=GND

Output sinking

current = 3.0mA

Output sourcing

current = 3mA

V

Peak voltage of Vin

= 4.0V

Note 1

mA

V

Note 3

Note 3

Note 4

Note 4

See notes on page 6

5

元器件交易网

IR1110

Notes for DC Electrical Characteristics

Note 1) VBREF=5.0V will assure full SCR firing on to produce the maximum amount of DC bus voltage and faster conver-

gence to the maximum DC bus voltage. Although VBREF=4.0V corresponds to the maximum voltage, it will take longer time

to converge to the maximum DC bus voltage.

Note 2) These voltage values are linearly proportional to VLNSET. For example, if VLNSET = 2.0V, then all values are twice

of those values listed in the table.

Note 3) VDD must be regulated within ±2.5%. VSS must be regulated within ±5%.

Symbol

t

r

t

f

t

WSCR

t

DLL

Definition

Turn-on rise time on SCRU, SCRV, and SCRW

Turn-off fall time on SCRU, SCRV, and SCRW

Output pulse width of SCRU,SCRV, and SCRW

LNLSLED propagation delay

est Conditions

—-

—-

—-

—-

500

500

15

30

—-

—-

—-

—-

ns

µs

LNLSSL=VDD,

C3PH =.022uF,

(note 1)

t

D1PH

t

LN

t

S1PH

1PHLED propagation delay

LNLED propagation delay

Shutdown time after loss of single phase

—-

—-

—-

8.3

150

15

—-

—-

20

ms

ms

C1PH = .001uF

(note 2)

1PHEN = VDD,

CUVLO = .1

m

F,

C1PH = .001

m

F,

(note 3)

t

f

FO

t

W1PH

t

UVLCK

t

RAMP

V

ENSCR

P

PUBAL

Fall time from high to low on LNLSLED,

1PHLED, LNLED

1PHLED pulse width

Power up UVLOCK delay

DC bus ramp time

Minimum input voltage on UIN, VIN, and WIN

for enabling SCR firing

Phase-to-phase unbalance between

pulses on SCRU, SCRV, and SCRW

—-

—-

50

2

60

150

—-

—-

ns

Pull-up resistor

= 6.2k

W

C1PH =.001

m

F,

(note 4)

msec

CUVLCK=.1uF,

(note 5)

C

RAMP

=1uF,

R

RAMP

=82k,(note 6)

—-

—-

—-

R

U2

/R

U1

—-

X 12

±

1.5

±

3

—-

V

(note 7)

Firing angle = 90

°

o

Notes 8 and 9

Firing angle = 140

°

Note 9

—-

°

6

元器件交易网

IR1110

Notes for AC Electrical Characteristics

Note 1) Delay is proportional to the capacitor values with minimum allowed value of C

3PH

= .01µF

Note 2) Depends on C

PKLL

charge condition

Note 3) C

UVLO

= .1µF, C

1PH

= .001µF. Increasing C

UVLO

increases the delay/response time of the 1phase lockout.

Note 4) Pulse width is proportional to C1PH. Maximum allowed values of C

1PH

is .001µF.

Note 5) Power up delay is set by C

UVLO

or by V

DD

rise time whichever takes longer. In this condition, V

DD

rise time must

not be less than 100msec, and 1-phase shutdown must be enabled. If this is less than 100msec or 1-phase shut

down is disabled, C

UVLO

must be increased to 0.22µF in order to increase the undervoltage lockout time to greater

than 100msec. See Note 3) above on additional effect of increasing C

UVLO

.

Note 6) Ramp time is proportional to the capacitor value.

Note 7) This value corresponds approximately to 15V minimum SCR firing voltage. For 15V minimum SCR firing voltage,

(R

SG2

/R

SG1

) X V

DD

= (

R

U2

/R

U1

) X 15.

Note 8) PPUBAL applies to steady operation, is deviation of any firing point to closest balanced set of firing points.

Note 9) Firing angle is defined with respect to zero delay (ie. max output voltage.

System Operating Characteristics and Specifications

All peripheral component values are those listed in the recommended operating condition unless otherwise specified.

Symbol

V

AC

Definition

Line-to-line AC voltage range (1%)

est Conditions

80

161

322

120

230

460

50/60

—-

2

100

150

140

276

552

63

99.8

—-

—-

—-

V

RMS

R

u1

,R

v1

,R

w1

=475K

R

POS1

,R

NEG1

=453K

R

u1

,R

v1

,R

w1

9537K

R

POS1

,R

NEG1

=887K

R

u1

,R

v1

,R

w1

=2X953K

R

POS1

,R

NEG1

=887K

f

LINE

V

BRANGE

V

BREG

V

BRES

t

RAMP1

Input line frequency

DC bus voltage controllable range

DC bus voltage regulation

DC bus voltage step response time

DC bus voltage ramp up time at power up

47

35

—-

—-

—

t

RAMP2

DC bus voltage ramp up time at power dip

ride through

Power up delay time before ramp up

—-75—-

t

d

PWR

—-190—-

t

d

DIP1

Delay time to start ramp-up after recovery from

a transient loss of line voltage

Firing angle range

Delay time to shutdown SCR firing pulses after

loss of one phase input

Delay time to start ramp-up after recovery from a

loss of one phase input

1.5

15

—-

15

a

FIRE

t

d

1PHS

t

d

1PHE

—-

—-

30

160

30

—-

Hz

%V

BREF

=1.4V to 4V

%

msec V

BUS

=35% to 100%

Note 6

msec C

RAMP

= 1

µ

F

R

RAMP

= 82k

(Note 7)

msecC

RAMP

= 1

µ

F

R

RAMP

= 82k

(Note 7)

msecC

RAMP

= 1

µ

F

C

UVLO

= 0.1

µ

F

Note 9)

msec Voltage drop below

the reference voltage

at B

DIP2

pin

°

Figure 2, Note 14

msec1PHEN = V

DD

msec1PHEN = V

DD

7

元器件交易网

IR1110

System Operating Characteristics and Specifications

All peripheral component values are those listed in the recommended operating condition unless otherwise specified.

t

d

1FIRE

First SCR firing angle at ramp-up—20CRAMP=1

µ

F,

R

RAMP

= 82k

(Note 10)

°

25CRAMP=2.2

µ

F,

R

RAMP

= 47k

(Note 10)

°

22CRAMP=3.3

µ

F,

R

RAMP

= 30k

(Notes10,12, 13)

20

°

CRAMP = 1

µ

F,

R

RAMP

= 82k

14CRAMP=3.3

µ

F,

R

RAMP

= 30k

(Notes 11 and 13)

32

°

16

14

RLIM

FIRE

Rate of advance of firing angle from last max firing

angle during ramp-up

—-10

7

Notes for System Operating Characteristics

Note 6) Step change of V

BREF

may result in excessive bus capacitor charging current. Rate of change of V

BREF

should

be decreased in order to limit bus capacitor charging current for practical application.

Note 7) Time to ramp up to 99.8% DC bus level at a power up. It does not include the power up delay time. The practical

limitation of the minimum time (50msec) depends on the inrush current to the DC bus capacitor. Ramp time is

proportional to C

RAMP

.

Note 8) Time to ramp back to 99.8% DC bus level from 50% DC bus level at a momentary power dip. This does not

include the delay time to start ramp-up (t

DDIP

)

Note 9) The value depends on C

UVLCK

Note 10) The value depends on C

RAMP

, R

PK

, R

RAMP

Note 11)The value depends on C

RAMP

Note 12)See operation description - Ramp Circuit

Note 13)Firing angle defined with respect to fully off (zero output voltage) firing angle.

Note 14)Firing angle defined with respect to zero delay.

8

元器件交易网

uld

IR1110

Note 1) LNLSLED may toggle high once for 2msec after event of phase loss.

Note 2) 1PHLED and LNLSLED are completely synchronized and complementary.

9

ctical

e is

元器件交易网

IR1110

3

Firing

voltage

reference

COMP

LINE

VOLTAGE

3

Line Voltage

Processing

3

Line Sync

&

Timing wave

generator

Timing wave

Watchdog

3

3

COMP

SCR

FIRING

PULSES

Single Phase

Phase Loss

Detect

High/Low

Line Fault

+

-

Line Loss

Ramp

Clamp

Amp

ENABLE

Ramp

Generator

Timing wave

Reference

Generator

VBUS

Vbus Dip

Detector

RESET

VBUS

REF

+

-

Error

Amp

1

1 + s

τ

Figure 1

Firing Angle,