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2024年10月26日发(作者：钭梦竹)

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MX25L1005

1M-BIT [x 1] CMOS SERIAL FLASH

FEATURES

GENERAL

• Serial Peripheral Interface (SPI) compatible -- Mode 0 and Mode 3

• 1,048,576 x 1 bit structure

• 32 Equal Sectors with 4K byte each

- Any Sector can be erased individually

•2 Equal Blocks with 64K byte each

- Any Block can be erased individually

• Single Power Supply Operation

- 2.7 to 3.6 volt for read, erase, and program operations

• Latch-up protected to 100mA from -1V to Vcc +1V

• Low Vcc write inhibit is from 1.5V to 2.5V

PERFORMANCE

• High Performance

- Fast access time: 85MHz serial clock (15pF + 1TTL Load) and 66MHz serial clock (30pF + 1TTL Load)

- Fast program time: 1.4ms(typ.) and 5ms(max.)/page (256-byte per page)

- Fast erase time: 60ms(typ.) and 120ms(max.)/sector (4K-byte per sector) ; 1s(typ.) and 2s(max.)/block (64K-byte per

block)

• Low Power Consumption

- Low active read current: 12mA(max.) at 85MHz, 8mA(max.) at 66MHz and 4mA(max.) at 33MHz

- Low active programming current: 15mA (max.)

- Low active erase current: 15mA (max.)

- Low standby current: 10uA (max.)

- Deep power-down mode 1uA (typical)

• Minimum 100,000 erase/program cycles

SOFTWARE FEATURES

• Input Data Format

- 1-byte Command code

•Block Lock protection

- The BP0~BP1 status bit defines the size of the area to be software protected against Program and Erase instructions.

• Auto Erase and Auto Program Algorithm

Automatically erases and verifies data at selected sector

Automatically programs and verifies data at selected page by an internal algorithm that automatically times the

program pulse widths (Any page to be programed should have page in the erased state first)

• Status Register Feature

• Electronic Identification

JEDEC 2-byte Device ID

- RES command, 1-byte Device ID

P/N: PM1238

REV. 1.9, AUG. 14, 2008

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MX25L1005

HARDWARE FEATURES

• SCLK Input

Serial clock input

• SI Input

Serial Data Input

• SO Output

Serial Data Output

• WP# pin

Hardware write protection

• HOLD# pin

pause the chip without diselecting the chip

• PACKAGE

8-pin SOP (150mil)

- 8-land USON (2x3x0.6mm)

- All Pb-free devices are RoHS Compliant

GENERAL DESCRIPTION

MX25L1005 is a CMOS 1,048,576 bit serial Flash memory, which is configured as 131,072 x 8 MX25L1005

feature a serial peripheral interface and software protocol allowing operation on a simple 3-wire bus. The three bus signals

are a clock input (SCLK), a serial data input (SI), and a serial data output (SO). SPI access to the device is enabled by

CS# input.

The MX25L1005 provide sequential read operation on whole chip.

After program/erase command is issued, auto program/ erase algorithms which program/ erase and verify the specified

page or sector/block locations will be executed. Program command is executed on page (256 bytes) basis, and erase

command is executes on chip or sector(4K-bytes) or block(64K-bytes).

To provide user with ease of interface, a status register is included to indicate the status of the chip. The status read

command can be issued to detect completion status of a program or erase operation via WIP bit.

When the device is not in operation and CS# is high, it is put in standby mode and draws less than 10uA DC current.

The MX25L1005 utilize MXIC's proprietary memory cell, which reliably stores memory contents even after 100,000 program

and erase cycles.

Advanced Information

P/N: PM1238

REV. 1.9, AUG. 14, 2008

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MX25L1005

PIN CONFIGURATIONS

8-PIN SOP (150mil)

CS#

WP#

GND

VCC

HOLD#

SCLK

8-LAND USON (2x3mm)

CS#

WP#

GND

VCC

HOLD#

SCLK

PIN DESCRIPTION

SYMBOL

CS#

SCLK

HOLD#

VCC

GND

DESCRIPTION

Chip Select

Serial Data Input

Serial Data Output

Clock Input

Hold, to pause the device without

deselecting the device

+ 3.3V Power Supply

Ground

P/N: PM1238

REV. 1.9, AUG. 14, 2008

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MX25L1005

BLOCK DIAGRAM

Address

Generator

X-Decoder

Memory Array

Page Buffer

Data

Y-Decoder

SRAM

Buffer

Sense

Amplifier

Generator

CS#

Mode

Logic

State

Machine

Output

Buffer

SCLKClock Generator

P/N: PM1238

REV. 1.9, AUG. 14, 2008

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MX25L1005

DATA PROTECTION

The MX25L1005 is designed to offer protection against accidental erasure or programming caused by spurious system level

signals that may exist during power transition. During power up the device automatically resets the state machine in the

Read mode. In addition, with its control register architecture, alteration of the memory contents only occurs after successful

completion of specific command sequences. The device also incorporates several features to prevent inadvertent write

cycles resulting from VCC power-up and power-down transition or system noise.

•Power-on reset and tPUW: to avoid sudden power switch by system power supply transition, the power-on reset and

tPUW (internal timer) may protect the Flash.

• Valid command length checking: The command length will be checked whether it is at byte base and completed on byte

boundary.

• Write Enable (WREN) command: WREN command is required to set the Write Enable Latch bit (WEL) before other

command to change data. The WEL bit will return to reset stage under following situation:

- Power-up

- Write Disable (WRDI) command completion

- Write Status Register (WRSR) command completion

- Page Program (PP) command completion

- Sector Erase (SE) command completion

- Block Erase (BE) command completion

- Chip Erase (CE) command completion

•

Software Protection Mode (SPM): by using BP0-BP1 bits to set the part of Flash protected from data change.

Hardware Protection Mode (HPM): by using WP# going low to protect the BP0-BP1 bits and SRWD bit from data change.

Deep Power Down Mode: By entering deep power down mode, the flash device also is under protected from writing all

commands except Release from deep power down mode command (RDP) and Read Electronic Signature command

(RES).

P/N: PM1238

REV. 1.9, AUG. 14, 2008

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MX25L1005

Table 1. Protected Area Sizes

Status bit

BP1BP0

Protect level

0 (none)

1 (1 block)

2 (2 blocks)

3 (All)

1Mb

None

Block 1

All

HOLD FEATURE

HOLD# pin signal goes low to hold any serial communications with the device. The HOLD feature will not stop the operation

of write status register, programming, or erasing in progress.

The operation of HOLD requires Chip Select(CS#) keeping low and starts on falling edge of HOLD# pin signal while Serial

Clock (SCLK) signal is being low (if Serial Clock signal is not being low, HOLD operation will not start until Serial Clock

signal being low). The HOLD condition ends on the rising edge of HOLD# pin signal while Serial Clock(SCLK) signal is

being low( if Serial Clock signal is not being low, HOLD operation will not end until Serial Clock being low), see Figure 1.

Figure 1. Hold Condition Operation

CS#

SCLK

HOLD#

Hold

Condition

(standard)

Hold

Condition

(non-standard)

The Serial Data Output (SO) is high impedance, both Serial Data Input (SI) and Serial Clock (SCLK) are don't care during

the HOLD operation. If Chip Select (CS#) drives high during HOLD operation, it will reset the internal logic of the device.

To re-start communication with chip, the HOLD# must be at high and CS# must be at low.

P/N: PM1238

REV. 1.9, AUG. 14, 2008

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MX25L1005

Table 2. COMMAND DEFINITION

COMMANDWREN

(byte)(write

Enable)

1st06 Hex

2nd

3rd

4th

5th

Actionsets the

(WEL)

write

enable

latch bit

COMMANDSE

(byte)(Sector

Erase)

1st

2nd

3rd

4th

5th

Action

20 Hex

AD1

AD2

AD3

WRDI

(write

disable)

04 Hex

RDID

(read ident-

ification)

9F Hex

RDSR

(read status

05 Hex

WRSR

(write status

01 Hex

READ

(read data)

03 Hex

AD1

AD2

AD3

Fast Read

(fast read

data)

0B Hex

AD1

AD2

AD3

reset the

(WEL)

write

enable

latch bit

(Block

Erase)

D8 Hex

AD1

AD2

AD3

output theto read out

manufacturerthe status

ID and 2-byteregister

device ID

to write newn bytes

values to theread out

status registeruntil

CS# goes

high

RDP

(Release

from Deep

Power-down)

AB Hex

RES

(Read

Electronic

ID)

AB Hex

REMS (Read

Electronic

Manufacturer

& Device ID)

90 Hex

ADD(1)

Output the

manufacturer

ID and device

(Chip

Erase)

60 or

C7 Hex

(Page

Program)

02 Hex

AD1

AD2

AD3

(Deep

Power

Down)

B9 Hex

(1) ADD=00H will output the manufacturer's ID first and ADD=01H will output device ID first.

(2) It is not allowed to adopt any other code which is not in the above command definition table.

P/N: PM1238

REV. 1.9, AUG. 14, 2008

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MX25L1005

Table 3. Memory Organization

Bolck

Sector

Address Range

01F000h

010000h

00F000h

003000h

002000h

001000h

000000h

01FFFFh

010FFFh

00FFFFh

003FFFh

002FFFh

001FFFh

000FFFh

P/N: PM1238

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MX25L1005

DEVICE OPERATION

a command is issued, status register should be checked to ensure device is ready for the intended operation.

incorrect command is inputted to this LSI, this LSI becomes standby mode and keeps the standby mode until

next CS# falling edge. In standby mode, SO pin of this LSI should be High-Z.

correct command is inputted to this LSI, this LSI becomes active mode and keeps the active mode until next

CS# rising edge.

data is latched on the rising edge of Serial Clock(SCLK) and data shifts out on the falling edge of SCLK. The

difference of SPI mode 0 and mode 3 is shown as Figure 2.

the following instructions: RDID, RDSR, READ, FAST_READ, RES and REMS the shifted-in instruction sequence

is followed by a data-out sequence. After any bit of data being shifted out, the CS# can be high. For the following

instructions: WREN, WRDI, WRSR, SE, BE, CE, PP, RDP and DP the CS# must go high exactly at the byte boundary;

otherwise, the instruction will be rejected and not executed.

the progress of Write Status Register, Program, Erase operation, to access the memory array is neglected and

not affect the current operation of Write Status Register, Program, Erase.

Figure 2.

SPI Modes Supported

CPOLCPHA

SCLK

shift inshift out

(SPI mode 0)00

(SPI mode 3)

SCLK

SIMSB

MSB

Note:

CPOL indicates clock polarity of SPI master, CPOL=1 for SCLK high while idle, CPOL=0 for SCLK low while not

transmitting. CPHA indicates clock phase. The combination of CPOL bit and CPHA bit decides which SPI mode is

supported.

P/N: PM1238

REV. 1.9, AUG. 14, 2008

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MX25L1005

COMMAND DESCRIPTION

(1) Write Enable (WREN)

The Write Enable (WREN) instruction is for setting Write Enable Latch (WEL) bit. For those instructions like PP, SE, BE,

CE, and WRSR, which are intended to change the device content, should be set every time after the WREN instruction

setting the WEL bit.

The sequence of issuing WREN instruction is: CS# goes low-> sending WREN instruction code-> CS# goes high. (see

Figure 11)

(2) Write Disable (WRDI)

The Write Disable (WRDI) instruction is for resetting Write Enable Latch (WEL) bit.

The sequence of issuing WRDI instruction is: CS# goes low-> sending WRDI instruction code-> CS# goes high. (see Figure

12)

The WEL bit is reset by following situations:

- Power-up

- Write Disable (WRDI) instruction completion

- Write Status Register (WRSR) instruction completion

- Page Program (PP) instruction completion

- Sector Erase (SE) instruction completion

- Block Erase (BE) instruction completion

- Chip Erase (CE) instruction completion

(3) Read Identification (RDID)

The RDID instruction is for reading the manufacturer ID of 1-byte and followed by Device ID of 2-byte. The MXIC

Manufacturer ID is C2(hex), the memory type ID is 20(hex) as the first-byte device ID, and the individual device ID of

second-byte ID is as followings: 11(hex) for MX25L1005.

The sequence of issuing RDID instruction is: CS# goes low-> sending RDID instruction code -> 24-bits ID data out on SO

-> to end RDID operation can use CS# to high at any time during data out. (see Figure. 13)

While Program/Erase operation is in progress, it will not decode the RDID instruction, so there's no effect on the cycle of

program/erase operation which is currently in progress. When CS# goes high, the device is at standby stage.

P/N: PM1238

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MX25L1005

(4) Read Status Register (RDSR)

The RDSR instruction is for reading Status Register Bits. The Read Status Register can be read at any time (even in

program/erase/write status register condition) and continuously. It is recommended to check the Write in Progress (WIP)

bit before sending a new instruction when a program, erase, or write status register operation is in progress.

The sequence of issuing RDSR instruction is: CS# goes low-> sending RDSR instruction code-> Status Register data out

on SO (see Figure. 14)

The definition of the status register bits is as below:

WIP bit. The Write in Progress (WIP) bit, a volatile bit, indicates whether the device is busy in program/erase/write status

register progress. When WIP bit sets to 1, which means the device is busy in program/erase/write status register progress.

When WIP bit sets to 0, which means the device is not in progress of program/erase/write status register cycle.

WEL bit. The Write Enable Latch (WEL) bit, a volatile bit, indicates whether the device is set to internal write enable latch.

When WEL bit sets to 1, which means the internal write enable latch is set, the device can accept program/erase/write

status register instruction. When WEL bit sets to 0, which means no internal write enable latch; the device will not accept

program/erase/write status register instruction.

BP1, BP0 bits. The Block Protect (BP1, BP0) bits, non-volatile bits, indicate the protected area(as defined in table 1) of

the device to against the program/erase instruction without hardware protection mode being set. To write the Block Protect

(BP1, BP0) bits requires the Write Status Register (WRSR) instruction to be executed. Those bits define the protected

area of the memory to against Page Program (PP), Sector Erase (SE), Block Erase (BE) and Chip Erase(CE) instructions

(only if all Block Protect bits set to 0, the CE instruction can be executed)

SRWD bit. The Status Register Write Disable (SRWD) bit, non-volatile bit, is operated together with Write Protection (WP#)

pin for providing hardware protection mode. The hardware protection mode requires SRWD sets to 1 and WP# pin signal

is low stage. In the hardware protection mode, the Write Status Register (WRSR) instruction is no longer accepted for

execution and the SRWD bit and Block Protect bits (BP1, BP0) are read only.

bit 7

SRWD

Status

Protect

1= status

disable

bit 6

bit 5

bit 4

bit 3bit 2

BP1BP0

the level ofthe level of

protectedprotected

blockblock

(note 1)(note 1)

bit 1

WEL

(write enable

latch)

bit 0

WIP

(write in progress

bit)

1=write enable1=write operation

0=not write0=not in write

enableoperation

Note:1. See the table "Protected Area Sizes".

2. The endurance cycles of protect bits are 100,000 cycles; however, the tW time out spec of protect bits is relaxed

as tW = N x 15ms (N is a multiple of 10,000 cycles, ex. N = 2 for 20,000 cycles) after 10,000 cycles on those bits.

P/N: PM1238

REV. 1.9, AUG. 14, 2008

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MX25L1005

(5) Write Status Register (WRSR)

The WRSR instruction is for changing the values of Status Register Bits. Before sending WRSR instruction, the Write

Enable (WREN) instruction must be decoded and executed to set the Write Enable Latch (WEL) bit in advance. The WRSR

instruction can change the value of Block Protect (BP1, BP0) bits to define the protected area of memory (as shown in

table 1). The WRSR also can set or reset the Status Register Write Disable (SRWD) bit in accordance with Write Protection

(WP#) pin signal. The WRSR instruction cannot be executed once the Hardware Protected Mode (HPM) is entered.

The sequence of issuing WRSR instruction is: CS# goes low-> sending WRSR instruction code-> Status Register data

on SI-> CS# goes high. (see Figure 15)

The WRSR instruction has no effect on b6, b5, b4, b1, b0 of the status register.

The CS# must go high exactly at the byte boundary; otherwise, the instruction will be rejected and not executed. The self-

timed Write Status Register cycle time (tW) is initiated as soon as Chip Select (CS#) goes high. The Write in Progress

(WIP) bit still can be check out during the Write Status Register cycle is in progress. The WIP sets 1 during the tW timing,

and sets 0 when Write Status Register Cycle is completed, and the Write Enable Latch (WEL) bit is reset.

Table 4. Protection Modes

Mode

Software protection

mode(SPM)

Status register condition

Status register can be written

in (WEL bit is set to "1") and

the SRWD, BP0-BP1

bits can be changed

WP# and SRWD bit status

WP#=1 and SRWD bit=0, or

WP#=0 and SRWD bit=0, or

WP#=1 and SRWD=1

Memory

The protected area cannot

be programmed or erased.

Hardware protection

mode (HPM)

The SRWD, BP0-BP1 of

status register bits cannot be

changed

WP#=0, SRWD bit=1

The protected area cannot

be programmed or erased.

Note:

1. As defined by the values in the Block Protect (BP1, BP0) bits of the Status Register, as shown in Table 1.

As the above table showing, the summary of the Software Protected Mode (SPM) and Hardware Protected Mode (HPM).

Software Protected Mode (SPM):

-When SRWD bit=0, no matter WP# is low or high, the WREN instruction may set the WEL bit and can change the values

of SRWD, BP1, BP0. The protected area, which is defined by BP1, BP0, is at software protected mode (SPM).

-When SRWD bit=1 and WP# is high, the WREN instruction may set the WEL bit can change the values of SRWD, BP1,

BP0. The protected area, which is defined by BP1, BP0, is at software protected mode (SPM)

Note: If SRWD bit=1 but WP# is low, it is impossible to write the Status Register even if the WEL bit has previously been

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MX25L1005

set. It is rejected to write the Status Register and not be executed.

Hardware Protected Mode (HPM):

-When SRWD bit=1, and then WP# is low (or WP# is low before SRWD bit=1), it enters the hardware protected mode

(HPM). The data of the protected area is protected by software protected mode by BP1, BP0 and hardware protected

mode by the WP# to against data modification.

Note: to exit the hardware protected mode requires WP# driving high once the hardware protected mode is entered. If the

WP# pin is permanently connected to high, the hardware protected mode can never be entered; only can use software

protected mode via BP1, BP0.

(6) Read Data Bytes (READ)

The read instruction is for reading data out. The address is latched on rising edge of SCLK, and data shifts out on the falling

edge of SCLK at a maximum frequency fR. The first address byte can be at any location. The address is automatically

increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single

READ instruction. The address counter rolls over to 0 when the highest address has been reached.

The sequence of issuing READ instruction is: CS# goes low-> sending READ instruction code-> 3-byte address on SI

-> data out on SO-> to end READ operation can use CS# to high at any time during data out. (see Figure. 16)

(7) Read Data Bytes at Higher Speed (FAST_READ)

The FAST_READ instruction is for quickly reading data out. The address is latched on rising edge of SCLK, and data of

each bit shifts out on the falling edge of SCLK at a maximum frequency fC. The first address byte can be at any location.

The address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory

can be read out at a single FAST_READ instruction. The address counter rolls over to 0 when the highest address has

been reached.

The sequence of issuing FAST_READ instruction is: CS# goes low-> sending FAST_READ instruction code-> 3-byte

address on SI-> 1-dummy byte address on SI->data out on SO-> to end FAST_READ operation can use CS# to high at

any time during data out. (see Figure. 17)

While Program/Erase/Write Status Register cycle is in progress, FAST_READ instruction is rejected without any impact

on the Program/Erase/Write Status Register current cycle.

(8) Sector Erase (SE)

The Sector Erase (SE) instruction is for erasing the data of the chosen sector to be "1". A Write Enable (WREN) instruction

must execute to set the Write Enable Latch (WEL) bit before sending the Sector Erase (SE). Any address of the sector

(see table 3) is a valid address for Sector Erase (SE) instruction. The CS# must go high exactly at the byte boundary (the

latest eighth of address byte been latched-in); otherwise, the instruction will be rejected and not executed.

Address bits [Am-A12] (Am is the most significant address) select the sector address.

The sequence of issuing SE instruction is: CS# goes low -> sending SE instruction code-> 3-byte address on SI -> CS#

goes high. (see Figure 19)

P/N: PM1238

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MX25L1005

The self-timed Sector Erase Cycle time (tSE) is initiated as soon as Chip Select (CS#) goes high. The Write in Progress

(WIP) bit still can be check out during the Sector Erase cycle is in progress. The WIP sets 1 during the tSE timing, and

sets 0 when Sector Erase Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If the page is protected by

BP1, BP0 bits, the Sector Erase (SE) instruction will not be executed on the page.

(9) Block Erase (BE)

The Block Erase (BE) instruction is for erasing the data of the chosen block to be "1". A Write Enable (WREN) instruction

must execute to set the Write Enable Latch (WEL) bit before sending the Block Erase (BE). Any address of the block

(see table 3) is a valid address for Block Erase (BE) instruction. The CS# must go high exactly at the byte boundary (the

latest eighth of address byte been latched-in); otherwise, the instruction will be rejected and not executed.

The sequence of issuing BE instruction is: CS# goes low -> sending BE instruction code-> 3-byte address on SI -> CS#

goes high. (see Figure 20)

The self-timed Block Erase Cycle time (tBE) is initiated as soon as Chip Select (CS#) goes high. The Write in Progress

(WIP) bit still can be check out during the Sector Erase cycle is in progress. The WIP sets 1 during the tBE timing, and

sets 0 when Sector Erase Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If the page is protected by

BP1, BP0 bits, the Block Erase (BE) instruction will not be executed on the page.

(10) Chip Erase (CE)

The Chip Erase (CE) instruction is for erasing the data of the whole chip to be "1". A Write Enable (WREN) instruction must

execute to set the Write Enable Latch (WEL) bit before sending the Chip Erase (CE). Any address of the sector (see table

3) is a valid address for Chip Erase (CE) instruction. The CS# must go high exactly at the byte boundary( the latest eighth

of address byte been latched-in); otherwise, the instruction will be rejected and not executed.

The sequence of issuing CE instruction is: CS# goes low-> sending CE instruction code-> CS# goes high. (see Figure

20)

The self-timed Chip Erase Cycle time (tCE) is initiated as soon as Chip Select (CS#) goes high. The Write in Progress

(WIP) bit still can be check out during the Chip Erase cycle is in progress. The WIP sets 1 during the tCE timing, and

sets 0 when Chip Erase Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If the chip is protected by BP1,

BP0 bits, the Chip Erase (CE) instruction will not be executed. It will be only executed when BP1, BP0 all set to "0".

(11) Page Program (PP)

The Page Program (PP) instruction is for programming the memory to be "0". A Write Enable (WREN) instruction must

execute to set the Write Enable Latch (WEL) bit before sending the Page Program (PP). If the eight least significant

address bits (A7-A0) are not all 0, all transmitted data which goes beyond the end of the current page are programmed

from the start address if the same page (from the address whose 8 least significant address bits (A7-A0) are all 0). The

CS# must keep during the whole Page Program cycle. The CS# must go high exactly at the byte boundary( the latest

eighth of address byte been latched-in); otherwise, the instruction will be rejected and not executed. If more than 256 bytes

are sent to the device, the data of the last 256-byte is programmed at the request page and previous data will be

disregarded. If less than 256 bytes are sent to the device, the data is programmed at the request address of the page

without effect on other address of the same page.

The sequence of issuing PP instruction is: CS# goes low-> sending PP instruction code-> 3-byte address on SI-> at least

1-byte on data on SI-> CS# goes high. (see Figure 18)

The self-timed Page Program Cycle time (tPP) is initiated as soon as Chip Select (CS#) goes high. The Write in Progress

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MX25L1005

(WIP) bit still can be check out during the Page Program cycle is in progress. The WIP sets 1 during the tPP timing, and

sets 0 when Page Program Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If the page is protected by

BP1, BP0 bits, the Page Program (PP) instruction will not be executed.

(12) Deep Power-down (DP)

The Deep Power-down (DP) instruction is for setting the device on the minimizing the power consumption (to entering the

Deep Power-down mode), the standby current is reduced from ISB1 to ISB2). The Deep Power-down mode requires the

Deep Power-down (DP) instruction to enter, during the Deep Power-down mode, the device is not active and all Write/

Program/Erase instruction are ignored. When CS# goes high, it's only in standby mode not deep power-down mode. It's

different from Standby mode.

The sequence of issuing DP instruction is: CS# goes low-> sending DP instruction code-> CS# goes high. (see Figure 22)

Once the DP instruction is set, all instruction will be ignored except the Release from Deep Power-down mode (RDP) and

Read Electronic Signature (RES) instruction. (RES instruction to allow the ID been read out). When Power-down, the deep

power-down mode automatically stops, and when power-up, the device automatically is in standby mode. For RDP

instruction the CS# must go high exactly at the byte boundary (the latest eighth bit of instruction code been latched-in);

otherwise, the instruction will not executed. As soon as Chip Select (CS#) goes high, a delay of tDP is required before

entering the Deep Power-down mode and reducing the current to ISB2.

(13) Release from Deep Power-down (RDP), Read Electronic Signature (RES)

The Release from Deep Power-down (RDP) instruction is terminated by driving Chip Select (CS#) High. When Chip Select

(CS#) is driven High, the device is put in the Stand-by Power mode. If the device was not previously in the Deep Power-

down mode, the transition to the Stand-by Power mode is immediate. If the device was previously in the Deep Power-down

mode, though, the transition to the Stand-by Power mode is delayed by tRES2, and Chip Select (CS#) must remain High

for at least tRES2(max), as specified in Table 6. Once in the Stand-by Power mode, the device waits to be selected, so

that it can receive, decode and execute instructions.

RES instruction is for reading out the old style of 8-bit Electronic Signature, whose values are shown as table of ID

Definitions. This is not the same as RDID instruction. It is not recommended to use for new design. For new deisng, please

use RDID instruction. Even in Deep power-down mode, the RDP and RES are also allowed to be executed, only except

the device is in progress of program/erase/write cycle; there's no effect on the current program/erase/write cycle in

progress.

The sequence is shown as Figure 23,24.

The RES instruction is ended by CS# goes high after the ID been read out at least once. The ID outputs repeatedly if

continuously send the additional clock cycles on SCLK while CS# is at low. If the device was not previously in Deep Power-

down mode, the device transition to standby mode is immediate. If the device was previously in Deep Power-down mode,

there's a delay of tRES2 to transit to standby mode, and CS# must remain to high at least tRES2(max). Once in the standby

mode, the device waits to be selected, so it can be receive, decode, and execute instruction.

The RDP instruction is for releasing from Deep Power Down Mode.

P/N: PM1238

REV. 1.9, AUG. 14, 2008

元器件交易网

MX25L1005

(14) Read Electronic Manufacturer ID & Device ID (REMS)

The REMS instruction is an alternative to the Release from Power-down/Device ID instruction that provides both the JEDEC

assigned manufacturer ID and the specific device ID.

The REMS instruction is very similar to the Release from Power-down/Device ID instruction. The instruction is initiated

by driving the CS# pin low and shift the instruction code "90h" followed by two dummy bytes and one bytes address (A7~A0).

After which, the Manufacturer ID for MXIC (C2h) and the Device ID are shifted out on the falling edge of SCLK with most

significant bit (MSB) first as shown in figure 25. The Device ID values are listed in Table of ID Definitions on page 16. If

the one-byte address is initially set to 01h, then the device ID will be read first and then followed by the Manufacturer ID.

The Manufacturer and Device IDs can be read continuously, alternating from one to the other. The instruction is completed

by driving CS# high.

Table of ID Definitions:

RDID Command

RES Command

REMS Commandmanufacturer ID

manufacturer ID

memory type

electronic ID

device ID

memory density

P/N: PM1238

REV. 1.9, AUG. 14, 2008

元器件交易网

MX25L1005

POWER-ON STATE

The device is at below states when power-up:

- Standby mode ( please note it is not deep power-down mode)

- Write Enable Latch (WEL) bit is reset

The device must not be selected during power-up and power-down stage unless the VCC achieves below correct level:

- VCC minimum at power-up stage and then after a delay of tVSL

- GND at power-down

Please note that a pull-up resistor on CS# may ensure a safe and proper power-up/down level.

An internal power-on reset (POR) circuit may protect the device from data corruption and inadvertent data change during

power up state. When VCC is lower than VWI (POR threshold voltage value), the internal logic is reset and the flash device

has no response to any command.

For further protection on the device, after VCC reaching the VWI level, a tPUW time delay is required before the device

is fully accessible for commands like write enable(WREN), page program (PP), sector erase(SE), chip erase(CE) and write

status register(WRSR). If the VCC does not reach the VCC minimum level, the correct operation is not guaranteed. The

write, erase, and program command should be sent after the below time delay:

- tPUW after VCC reached VWI level

- tVSL after VCC reached VCC minimum level

The device can accept read command after VCC reached VCC minimum and a time delay of tVSL, even time of tPUW

has not passed.

Please refer to the figure of "power-up timing".

Note:

- To stabilize the VCC level, the VCC rail decoupled by a suitable capacitor close to package pins is

recommended.(generally around 0.1uF)

- At power-down stage, the VCC drops below VWI level, all operations are disable and device has no response to any

command. The data corruption might occur during the stage while a write, program, erase cycle is in progress.

P/N: PM1238

REV. 1.9, AUG. 14, 2008

元器件交易网

MX25L1005

ELECTRICAL SPECIFICATIONS

ABSOLUTE MAXIMUM RATINGS

RATINGVALUE

Industrial grade

0°C to 70°C for

Commercial grade

Storage Temperature

Applied Input Voltage

Applied Output Voltage

VCC to Ground Potential

-55°C to 125°C

-0.5V to 4.6V

Ambient Operating Temperature-40°C to 85°C for

NOTICE:

es greater than those listed under ABSOLUTE

MAXIMUM RATINGS may cause permanent damage

to the device. This is stress rating only and functional

operational sections of this specification is not implied.

Exposure to absolute maximum rating conditions for

extended period may affect reliability.

ications contained within the following tables are

subject to change.

voltage transitions, all pins may overshoot to

4.6V or -0.5V for period up to 20ns.

input and output pins may overshoot to VCC+0.5V

while VCC+0.5V is smaller than or equal to 4.6V.

Figure m Negative Overshoot Waveform

20ns

Figure 4. Maximum Positive Overshoot Waveform

-0.5V

4.6V

3.6V

20ns

CAPACITANCE TA = 25

C, f = 1.0 MHz

SYMBOL

CIN

COUT

PARAMETER

Input Capacitance

Output Capacitance

UNIT

CONDITIONS

VIN = 0V

VOUT = 0V

P/N: PM1238

REV. 1.9, AUG. 14, 2008

元器件交易网

MX25L1005

Figure 5. INPUT TEST WAVEFORMS AND MEASUREMENT LEVEL

Input timing referance level

0.8VCC

0.7VCC

0.3VCC

Measurement

Level

Output timing referance level

0.5VCC

0.2VCC

Note: Input pulse rise and fall time are <5ns

Figure 6. OUTPUT LOADING

DEVICE UNDER

TEST

2.7K ohm

+3.3V

6.2K ohmDIODES=IN3064

OR EQUIVALENT

CL=30pF Including jig capacitance

(CL=15pF Including jig capacitance for 85MHz)

P/N: PM1238

REV. 1.9, AUG. 14, 2008

元器件交易网

MX25L1005

Table 5. DC CHARACTERISTICS (Temperature = -40

C to 85

C for Industrial grade, Temperature =

C to 70

C for Commercial grade, VCC = 2.7V ~ 3.6V)

SYMBOLPARAMETER

ILI

ILO

ISB1

ISB2

ICC1

Input Load

Current

Output Leakage

Current

VCC Standby

Current

Deep Power-down

Current

VCC Read112

ICC2

ICC3

VCC Program

Current (PP)

VCC Write Status

Current

ICC4

ICC5

VIL

VIH

VOL

VOH

VCC Sector Erase

Current (SE)

VCC Chip Erase

Current (CE)

Input Low Voltage

Input High Voltage

Output Low Voltage

Output High VoltageVCC-0.2

-0.5

0.7VCC

0.3VCC

VCC+0.4

0.4

IOL = 1.6mA

IOH = -100uA

115mA

115mAErase in Progress

CS#=VCC

Erase in Progress

CS#=VCC

15mA

115

15uA

110uA

1± 2uA

NOTES

± 2uA

TEST CONDITIONS

VCC = VCC Max

VIN = VCC or GND

VCC = VCC Max

VIN = VCC or GND

CS# = VCC

VIN = VCC or GND

CS# = VCC

f=85MHz

SCLK=0.1VCC/0.9VCC, SO=Open

f=66MHz

SCLK=0.1VCC/0.9VCC, SO=Open

f=33MHz

SCLK=0.1VCC/0.9VCC, SO=Open

Program in Progress

CS# = VCC

Program status register in progress

CS#=VCC

Notes :

l values at VCC = 3.3V, T = 25°C. These currents are valid for all product versions (package and speeds).

l value is calculated by simulation.

P/N: PM1238

REV. 1.9, AUG. 14, 2008

元器件交易网

MX25L1005

Table 6. AC CHARACTERISTICS (Temperature = -40

C to 85

C for Industrial grade, Temperature =

C to 70

C for Commercial grade, VCC = 2.7V ~ 3.6V)

Symbol

fSCLK

Alt.

Parameter

Clock Frequency for the following instructions:

FAST_READ, PP, SE, BE, CE, DP, RES,RDP

WREN, WRDI, RDID, RDSR, WRSR

Min.

1KHz

85MHz

(Condition:15pF)

66MHz

(Condition:30pF)

33MHz

V/ns

6ns

8ns

6ns

3us

1.8us

515ms

1.45ms

60120ms

12s

fRSCLK

tCH(1)

tCL(1)

tCLCH(2)

tCHCL(2)

tSLCH

tCHSL

tDVCH

tCHDX

tCHSH

tSHCH

tSHSL

tSHQZ(2)

tCLQV

tCLQX

tHLCH

tCHHH

tHHCH

tCHHL

tHHQX(2)

tHLQZ(2)

tWHSL(4)

tSHWL(4)

tDP(2)

tRES1(2)

tRES2(2)

tPP

tSE

tBE

tCE

fRClock Frequency for READ instructions

tCLHClock High Time

tCLLClock Low Time

Clock Rise Time (3) (peak to peak)

Clock Fall Time (3) (peak to peak)

tCSSCS# Active Setup Time (relative to SCLK)

CS# Not Active Hold Time (relative to SCLK)

tDSUData In Setup Time

tDHData In Hold Time

CS# Active Hold Time (relative to SCLK)

CS# Not Active Setup Time (relative to SCLK)

tCSHCS# Deselect Time

tDISOutput Disable Time

tVClock Low to Output Valid 30pF

15pF

tHOOutput Hold Time

HOLD# Setup Time (relative to SCLK)

HOLD# Hold Time (relative to SCLK)

HOLD Setup Time (relative to SCLK)

HOLD Hold Time (relative to SCLK)

tLZHOLD to Output Low-Z

tHZHOLD# to Output High-Z

Write Protect Setup Time

Write Protect Hold Time

CS# High to Deep Power-down Mode

CS# High to Standby Mode without Electronic Signature Read

CS# High to Standby Mode with Electronic Signature Read

Write Status Register Cycle Time

Page Program Cycle Time

Sector Erase Cycle Time

Block Erase Cycle Time

Chip Erase Cycle Time

1KHz

0.1

100

Note:

1. tCH + tCL must be greater than or equal to 1/ fC

2. Value guaranteed by characterization, not 100% tested in production.

3. Expressed as a slew-rate.

4. Only applicable as a constraint for a WRSR instruction when SRWD is set at 1.

5. Test condition is shown as Figure 3.

P/N: PM1238

REV. 1.9, AUG. 14, 2008

元器件交易网

MX25L1005

Table 7. Power-Up Timing and VWI Threshold

Symbol

tVSL(1)

tPUW(1)

VWI(1)

Parameter

VCC(min) to CS# low

Time delay to Write instruction

Write Inhibit Voltage

Min.

1.5

Max.

2.5

Unit

Note: 1. These parameters are characterized only.

INITIAL DELIVERY STATE

The device is delivered with the memory array erased: all bits are set to 1 (each byte contains FFh). The Status Register

contains 00h (all Status Register bits are 0).

P/N: PM1238

REV. 1.9, AUG. 14, 2008

元器件交易网

MX25L1005

Figure 7. Serial Input Timing

tSHSL

CS#

tCHSL

SCLK

tDVCH

tCHDX

MSB

tCLCH

LSB

tCHCL

tSLCHtCHSHtSHCH

High-Z

Figure 8. Output Timing

CS#

tCH

SCLK

tCLQV

tCLQX

tQLQH

tQHQL

tCLQV

tCLQX

tCLtSHQZ

LSB

P/N: PM1238

REV. 1.9, AUG. 14, 2008

元器件交易网

MX25L1005

Figure 9. Hold Timing

CS#

tHLCH

tCHHL

SCLK

tCHHH

tHLQZ

tHHQX

tHHCH

HOLD#

* SI is "don't care" during HOLD operation.

Figure 10. WP# Disable Setup and Hold Timing during WRSR when SRWD=1

WP#

tWHSL

CS#

SCLK

11121314

tSHWL

High-Z

P/N: PM1238

REV. 1.9, AUG. 14, 2008

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MX25L1005

Figure 11. Write Enable (WREN) Sequence (Command 06)

CS#

SCLK

Command

High-Z

1234567

Figure 12. Write Disable (WRDI) Sequence (Command 04)

CS#

SCLK

Command

High-Z

1234567

Figure 13. Read Identification (RDID) Sequence (Command 9F)

CS#

SCLK

Command

Manufacturer Identification

High-Z

MSB

65321

Device Identification

3210

1234567891

1617 1828293031

0151413

MSB

P/N: PM1238

REV. 1.9, AUG. 14, 2008

元器件交易网

MX25L1005

Figure 14. Read Status Register (RDSR) Sequence (Command 05)

CS#

SCLK

command

High-Z

MSB

6543210

MSB

6543210

Status Register Out

1234567891

Figure 15. Write Status Register (WRSR) Sequence (Command 01)

CS#

SCLK

command

Status

MSB

65432

1234567891

High-Z

Figure 16. Read Data Bytes (READ) Sequence (Command 03)

CS#

SCLK

command

24-Bit Address

3435

363738

232221

MSB

3210

Data Out 1

76543

Data Out 2

High-Z

MSB

P/N: PM1238

REV. 1.9, AUG. 14, 2008

元器件交易网

MX25L1005

Figure 17. Read at Higher Speed (FAST_READ) Sequence (Command 0B)

CS#

SCLK

Command

24 BIT ADDRESS

28293031

High-Z

2322213210

CS#

323334

3637383946

SCLK

Dummy Byte

765432

DATA OUT 1

DATA OUT 2

MSB

6543210

MSB

65432

P/N: PM1238

REV. 1.9, AUG. 14, 2008

元器件交易网

MX25L1005

Figure 18. Page Program (PP) Sequence (Command 02)

CS#

SCLK

Command

24-Bit AddressData Byte 1

3435

363738

232221

MSB

3210

765432

MSB

CS#

464748495

SCLK

Data Byte 2Data Byte 3Data Byte 256

765432

MSB

65432

765432

MSBMSB

P/N: PM1238

REV. 1.9, AUG. 14, 2008

元器件交易网

MX25L1005

Figure 19. Sector Erase (SE) Sequence (Command 20)

CS#

SCLK

Command

24 Bit Address

3031

MSB

6210

Note: SE command is 20(hex).

Figure 20. Block Erase (BE) Sequence (Command 52 or D8)

CS#

SCLK

Command

24 Bit Address

3031

52 or D8

2322

MSB

Note: BE command is 52 or D8(hex).

P/N: PM1238

REV. 1.9, AUG. 14, 2008

元器件交易网

MX25L1005

Figure 21. Chip Erase (CE) Sequence (Command 60 or C7)

CS#

SCLK

Command

60 or C7

1234567

Note: CE command is 60(hex) or C7(hex).

Figure 22. Deep Power-down (DP) Sequence (Command B9)

CS#

SCLK

Command

1234567

Stand-by Mode

Deep Power-down Mode

Figure 23. Release from Deep Power-down and Read Electronic Signature (RES) Sequence

(Command AB)

CS#

SCLK

Command

3 Dummy Bytes

RES2

3435

363738

High-Z

232221

MSB

3210

Electronic Signature Out

MSB

Deep Power-down Mode

Stand-by Mode

65432

P/N: PM1238

REV. 1.9, AUG. 14, 2008

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MX25L1005

Figure 24. Release from Deep Power-down (RDP) Sequence (Command AB)

CS#

SCLK

Command

High-Z

1234567

RES1

Deep Power-down Mode

Stand-by Mode

Figure 25. Read Electronic Manufacturer & Device ID (REMS) Sequence (Command 90)

CS#

SCLK

Command

2 Dummy Bytes

High-Z

1514133210

CS#

28293031

323334

3637383946

SCLK

ADD (1)

765432

Manufacturer ID

Device ID

MSB

6543210

MSB

65432

Notes:

(1) ADD=00H will output the manufacturer's ID first and ADD=01H will output device ID first

P/N: PM1238

REV. 1.9, AUG. 14, 2008

元器件交易网

MX25L1005

Figure 26. Power-up Timing

(max)

Program, Erase and Write Commands are Ignored

Chip Selection is Not Allowed

(min)

Reset State

of the

Flash

tPUW

tVSL

Read Command is

allowed

Device is fully

accessible

time

P/N: PM1238

REV. 1.9, AUG. 14, 2008

元器件交易网

MX25L1005

RECOMMENDED OPERATING CONDITIONS

At Device Power-Up

AC timing illustrated in Figure A is recommended for the supply voltages and the control signals at device power-up. If

the timing in the figure is ignored, the device may not operate correctly.

VCC(min)

VCC

GND

tVR

tSHSL

CS#

tCHSLtSLCHtCHSHtSHCH

SCLK

tDVCH

tCHDXtCLCH

LSB IN

tCHCL

MSB IN

High Impedance

Figure A. AC Timing at Device Power-Up

Symbol

tVR

Parameter

VCC Rise Time

Notes

Min.

0.5

Max.

500000

Unit

us/V

Notes :

d, not 100% tested.

AC spec tCHSL, tSLCH, tDVCH, tCHDX, tSHSL, tCHSH, tSHCH, tCHCL, tCLCH in the figure, please refer to "AC

CHARACTERISTICS" table.

P/N: PM1238

REV. 1.9, AUG. 14, 2008

元器件交易网

MX25L1005

ERASE AND PROGRAMMING PERFORMANCE

PARAMETER

Write Status Register Cycle Time

Sector erase Time

Block erase Time

Chip Erase Time

Page Program Time

Erase/Program Cycle100,000

. (1)

1.4

Max. (2)

120

UNIT

cycles

Note:

l program and erase time assumes the following conditions: 25°C, 3.3V, and checker board pattern.

worst conditions of 70°C and 3.0V.

-level overhead is the time required to execute the first-bus-cycle sequence for the programming command.

maximum chip programming time is evaluated under the worst conditions of 0C, VCC=3.0V, and 100K cycle with

90% confidence level.

LATCH-UP CHARACTERISTICS

MIN.

Input Voltage with respect to GND on ACC

Input Voltage with respect to GND on all power pins, SI, CS#

Input Voltage with respect to GND on SO

Current

Includes all pins except VCC. Test conditions: VCC = 3.0V, one pin at a time.

-1.0V

-100mA

MAX.

12.5V

2 VCCmax

VCC + 1.0V

+100mA

P/N: PM1238

REV. 1.9, AUG. 14, 2008

元器件交易网

MX25L1005

ORDERING INFORMATION

PART

(MHz)

MX25L1005MC-12G

MX25L1005MI-12G

MX25L1005ZUI-12G

OPERATING

(mA)

STANDBY

(uA)

0~70°C

-40~85°C

8-SOP

(150mil)

8-SOP

(150mil)

8-USON

(2x3x0.6mm)

Pb-free

TemperaturePACKAGERemark

CURRENT T MAX.

P/N: PM1238

REV. 1.9, AUG. 14, 2008

元器件交易网

MX25L1005

PART NAME DESCRIPTION

MX25L1005MC12G

OPTION:

G: Pb-free

SPEED:

12: 85MHz

TEMPERATURE RANGE:

C: Commercial (0˚C to 70˚C)

I: Industrial (-40˚C to 85˚C)

PACKAGE:

M: 150mil 8-SOP

ZU: 8-USON (2x3x0.6mm)

DENSITY & MODE:

1005: 1Mb

TYPE:

L: 3V

DEVICE:

25: Serial Flash

P/N: PM1238

REV. 1.9, AUG. 14, 2008

元器件交易网

MX25L1005

PACKAGE INFORMATION

P/N: PM1238

REV. 1.9, AUG. 14, 2008

元器件交易网

MX25L1005

P/N: PM1238

REV. 1.9, AUG. 14, 2008

元器件交易网

MX25L1005

REVISION HISTORY

Revision ption

1.01. Modified read current:6mA@85MHz/4mA@66MHz/2mA@33MHz

--> 12mA@85MHz/8mA@66MHz/4mA@33MHz

2. Modified tSE:90ms(typ)/270ms(max)-->60ms(typ)/120ms(max) ;

tBE:3s(max)-->2s(max); tCE:2.5s(typ)/6s(max)-->1s(typ)/2s(max)

3. Added description about Pb-free device is RoHS compliant

4. Removed "Advanced Information" title

1.11. Format change

2. Supplemented the footnote for tW of protect/unprotect bits

1.21. Added statement

1.31. Defined min. clock frequency of fSCLK & fRSCLK as 1KHz

1.41. Added 8-land USON package

1.51. Removed 8-land SON package and order information

1.61. Removed 8-USON(4x4mm) package and order information

1.71. Added 8-land USON(2x3mm) package and order information

1.81. Added 8-land USON (2x3mm) package as "advanced information"

2. Removed tCLQV frequency condition

1.91. Removed wrong Block Protect Bit, BP2

Page

P1,19,34

P1,20,33

All

P10

P39

P21

P2,3,35,36,39

P2,3,35,36

P2,3,35,36,38

P2,3,35,36

P21

P5,11

Date

SEP/28/2005

JUN/08/2006

NOV/06/2006

NOV/30/2006

JAN/22/2008

MAR/24/2008

APR/07/2008

MAY/27/2008

JUL/04/2008

AUG/14/2008

P/N: PM1238

REV. 1.9, AUG. 14, 2008

元器件交易网

MX25L1005

Macronix's products are not designed, manufactured, or intended for use for any high risk applications in which the failure

of a single component could cause death, personal injury, severe physical damage, or other substantial harm to persons

or property, such as life-support systems, high temperature automotive, medical, aircraft and military application. Macronix

and its suppliers will not be liable to you and/or any third party for any claims, injuries or damages that may be incurred due

to use of Macronix's products in the prohibited applications.

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NTERNATIONAL

O.,

TD.

Headquarters

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Tel: +886-3-5786688

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