2024年4月14日发(作者：笃德庸)
Chapter1
Packaging Overview
About this Guide
Xilinx® 7 series FPGAs include four FPGA families that are all designed for lowest power to
enable a common design to scale across families for optimal power, performance, and cost.
The Spartan®-7 family is the lowest density with the lowest cost entry point into the
7 series portfolio. The Artix®-7 family is optimized for highest performance-per-watt and
bandwidth-per-watt for cost-sensitive, high-volume applications. The Kintex®-7 family is
an innovative class of FPGAs optimized for the best price-performance. The Virtex®-7
family is optimized for highest system performance and capacity.
This 7 series packaging and pinout product specification, part of an overall set of
documentation on the 7 series FPGAs, is available on the Xilinx.
Introduction
This section describes the pinouts for the 7 series FPGAs in various fine pitch and flip-chip
1.0 mm pitch BGA packages, 0.8 mm and 0.5 mm pitch chip-scale packages, and 0.5 mm
pitch wire-bond lead frame packages.
Spartan-7, Artix-7, and Kintex-7 devices are offered in low-cost, space-saving packages that
are optimally designed for the maximum number of user I/Os.
Virtex-7 T and Virtex-7 XT devices are offered exclusively in high performance flip-chip BGA
packages that are optimally designed for improved signal integrity and jitter.
For pinout and packaging information on the Virtex-7 HT devices.
Package inductance is minimized as a result of optimal placement and even distribution
as well as an increased number of Power and GND pins.
The FFG, FLG, FHG, FBG, SBG, and RFG flip-chip packages marked with the Pb-free Character
on the upper right of the device are RoHS 6 of 6 compliant. The FFG, FLG, FHG, FBG, SBG, and
RFG flip-chip packages not marked with the Pb-free character are RoHS 6 of 6 compliant,
7 Series FPGAs Packaging
UG475 (v1.18) July 16, 2019
Chapter 1:Packaging Overview
7 Series FPGAs Packaging
UG475 (v1.18) July 16, 2019
Chapter 1:Packaging Overview
Table1-6 lists the quantity of GTX and GTH serial transceiver channels for the Virtex-7XT
FPGAs. In all devices, a serial transceiver channel is one set of MGTRXP, MGTRXN, MGTTXP,
and MGTTXN pins.
Table 1-6:
Device
XC7VX330T
XC7VX415T
XC7VX485T
XC7VX550T
XC7VX690T
XC7VX980T
XC7VX1140T
XQ7VX330T
XQ7VX485T
XQ7VX690T
XQ7VX980T
0
–
Serial Transceiver Channels (GTX/GTH) by Device/Package (Virtex-7XTFPGAs)
FFG1157FFG1158FFG1761
FFG1927FFG1930
FFV1157FFV1158FFV1761FFG1926
FFV1927
FFG1928
RF1930
FLG1926FLG1928FLG1930
RF1157RF1158RF1761
GTXGTHGTXGTHGTXGTHGTXGTHGTXGTHGTXGTHGTXGTHGTXGTHGTXGTHGTXGTH
0
0
20
–
20
20
0
20
–
–
–
0
48
0
48
480
–
–
–
28
0
–
–
–
–
–
–––
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
0
48
0
0
–
–
0
56
0
64
64
0
–
–
–
–
–
–
48
0
80
80
0
–
–
–
–
2824
–
0
24
24
–
–
–
–
–
–
0360
0
–
0
720
–
–
–
–
–
0
–
64
–
–
–
0
–
–
–
–
960
–
–
–
–
24
0
–
20
200
–
–
0
28
480
–
28
0
36
–
–
–
–
24
0
0
0
24
24
–
7 Series FPGAs Packaging
UG475 (v1.18) July 16, 2019
Chapter 1:Packaging Overview
Spartan-7 User I/O
DevicesPins
XC7S6
XA7S6
XC7S15
XA7S15
XC7S25
XA7S25
XC7S50
XA7S50
XC7S75
XA7S75
XC7S100
XA7S100
User I/O
Differential
User I/O
Differential
User I/O
Differential
User I/O
Differential
User I/O
Differential
User I/O
Differential
Spartan-7 FPGA Packages: HR I/O Banks Only
CPGA196
100
96
100
96
–
–
–
–
–
–
–
–
CSGA225
100
96
100
96
150
144
–
–
–
–
–
–
CSGA324
–
–
–
–
150
144
210
202
–
–
–
–
FTGB196
100
96
100
96
100
96
100
96
–
–
–
–
FGGA484
–
–
–
–
–
–
250
240
338
324
338
324
FGGA676
–
–
–
–
–
–
–
–
400
384
400
384
7 Series FPGAs Packaging
UG475 (v1.18) July 16, 2019
Chapter 1:Packaging Overview
Table 1-12:7Series FPGAs Pin Definitions (Cont’d)
Type
Dedicated
Dedicated
Dedicated
Dedicated
Dedicated
Dedicated
Dedicated
Pin Name
Power/Ground Pins
GND
RSVDGND
VCCAUX
VCCAUX_IO_G#
(2)
VCCINT
VCCO_#
(3)
VCCBRAM
Direction
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Ground
Description
Reserved pins, tie to GND
1.8V power-supply pins for auxiliary circuits
1.8V/2.0V power-supply pins for auxiliary I/O circuits
0.9V/1.0V power-supply pins for the internal core logic
Power-supply pins for the output drivers (per bank)
1.0V power-supply pins for the FPGA logic block RAM
Decryptor key memory backup supply; this pin should be
tied to the appropriate V
CC
or GND when not used
(4)
.
Specific Spartan-7 devices (XC7S6 and XC7S15) do not
support AES encryption. In these devices, connect
VCCBATT_0 to VCCAUX or GND.
These are input threshold voltage pins. They become user
I/Os when an external threshold voltage is not needed
(per bank).
VCCBATT_0DedicatedN/A
VREFMulti-functionN/A
Analog to Digital Converter (XADC) Pins
For more information, see the XADC Package Pins table in UG480, 7Series FPGAs and Zynq-7000 All
Programmable SoC XADC Dual 12-Bit 1 MSPS Analog-to-Digital Converter User Guide
XADC analog positive supply voltage
VCCADC_0
(5)(6)
DedicatedN/A
The XC7S6 and XC7S15 Spartan-7 devices do not support
the XADC. In these devices, connect the VCCADC_0 pin to
VCCAUX.
XADC analog ground reference
GNDADC_0
(5)(6)
VP_0
(5)
VN_0
(5)
VREFP_0
(5)
VREFN_ 0
(5)
AD0P through AD15P
AD0N through AD15N
DedicatedN/A
The XC7S6 and XC7S15 Spartan-7 devices do not support
the XADC. In these devices, connect the GNDADC_0 pin to
GND.
XADC dedicated differential analog input (positive side)
XADC dedicated differential analog input (negative side)
1.25V reference input
1.25V reference GND reference
XADC (analog-to-digital converter) differential auxiliary
analog inputs 0–15.
Auxiliary channels 6, 7, 13, 14, and 15 are not supported
on Kintex-7 devices.
Dedicated
Dedicated
Dedicated
Dedicated
Input
Input
N/A
N/A
Multi-functionInput
7 Series FPGAs Packaging
UG475 (v1.18) July 16, 2019
2024年4月14日发(作者：笃德庸)
Chapter1
Packaging Overview
About this Guide
Xilinx® 7 series FPGAs include four FPGA families that are all designed for lowest power to
enable a common design to scale across families for optimal power, performance, and cost.
The Spartan®-7 family is the lowest density with the lowest cost entry point into the
7 series portfolio. The Artix®-7 family is optimized for highest performance-per-watt and
bandwidth-per-watt for cost-sensitive, high-volume applications. The Kintex®-7 family is
an innovative class of FPGAs optimized for the best price-performance. The Virtex®-7
family is optimized for highest system performance and capacity.
This 7 series packaging and pinout product specification, part of an overall set of
documentation on the 7 series FPGAs, is available on the Xilinx.
Introduction
This section describes the pinouts for the 7 series FPGAs in various fine pitch and flip-chip
1.0 mm pitch BGA packages, 0.8 mm and 0.5 mm pitch chip-scale packages, and 0.5 mm
pitch wire-bond lead frame packages.
Spartan-7, Artix-7, and Kintex-7 devices are offered in low-cost, space-saving packages that
are optimally designed for the maximum number of user I/Os.
Virtex-7 T and Virtex-7 XT devices are offered exclusively in high performance flip-chip BGA
packages that are optimally designed for improved signal integrity and jitter.
For pinout and packaging information on the Virtex-7 HT devices.
Package inductance is minimized as a result of optimal placement and even distribution
as well as an increased number of Power and GND pins.
The FFG, FLG, FHG, FBG, SBG, and RFG flip-chip packages marked with the Pb-free Character
on the upper right of the device are RoHS 6 of 6 compliant. The FFG, FLG, FHG, FBG, SBG, and
RFG flip-chip packages not marked with the Pb-free character are RoHS 6 of 6 compliant,
7 Series FPGAs Packaging
UG475 (v1.18) July 16, 2019
Chapter 1:Packaging Overview
7 Series FPGAs Packaging
UG475 (v1.18) July 16, 2019
Chapter 1:Packaging Overview
Table1-6 lists the quantity of GTX and GTH serial transceiver channels for the Virtex-7XT
FPGAs. In all devices, a serial transceiver channel is one set of MGTRXP, MGTRXN, MGTTXP,
and MGTTXN pins.
Table 1-6:
Device
XC7VX330T
XC7VX415T
XC7VX485T
XC7VX550T
XC7VX690T
XC7VX980T
XC7VX1140T
XQ7VX330T
XQ7VX485T
XQ7VX690T
XQ7VX980T
0
–
Serial Transceiver Channels (GTX/GTH) by Device/Package (Virtex-7XTFPGAs)
FFG1157FFG1158FFG1761
FFG1927FFG1930
FFV1157FFV1158FFV1761FFG1926
FFV1927
FFG1928
RF1930
FLG1926FLG1928FLG1930
RF1157RF1158RF1761
GTXGTHGTXGTHGTXGTHGTXGTHGTXGTHGTXGTHGTXGTHGTXGTHGTXGTHGTXGTH
0
0
20
–
20
20
0
20
–
–
–
0
48
0
48
480
–
–
–
28
0
–
–
–
–
–
–––
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
0
48
0
0
–
–
0
56
0
64
64
0
–
–
–
–
–
–
48
0
80
80
0
–
–
–
–
2824
–
0
24
24
–
–
–
–
–
–
0360
0
–
0
720
–
–
–
–
–
0
–
64
–
–
–
0
–
–
–
–
960
–
–
–
–
24
0
–
20
200
–
–
0
28
480
–
28
0
36
–
–
–
–
24
0
0
0
24
24
–
7 Series FPGAs Packaging
UG475 (v1.18) July 16, 2019
Chapter 1:Packaging Overview
Spartan-7 User I/O
DevicesPins
XC7S6
XA7S6
XC7S15
XA7S15
XC7S25
XA7S25
XC7S50
XA7S50
XC7S75
XA7S75
XC7S100
XA7S100
User I/O
Differential
User I/O
Differential
User I/O
Differential
User I/O
Differential
User I/O
Differential
User I/O
Differential
Spartan-7 FPGA Packages: HR I/O Banks Only
CPGA196
100
96
100
96
–
–
–
–
–
–
–
–
CSGA225
100
96
100
96
150
144
–
–
–
–
–
–
CSGA324
–
–
–
–
150
144
210
202
–
–
–
–
FTGB196
100
96
100
96
100
96
100
96
–
–
–
–
FGGA484
–
–
–
–
–
–
250
240
338
324
338
324
FGGA676
–
–
–
–
–
–
–
–
400
384
400
384
7 Series FPGAs Packaging
UG475 (v1.18) July 16, 2019
Chapter 1:Packaging Overview
Table 1-12:7Series FPGAs Pin Definitions (Cont’d)
Type
Dedicated
Dedicated
Dedicated
Dedicated
Dedicated
Dedicated
Dedicated
Pin Name
Power/Ground Pins
GND
RSVDGND
VCCAUX
VCCAUX_IO_G#
(2)
VCCINT
VCCO_#
(3)
VCCBRAM
Direction
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Ground
Description
Reserved pins, tie to GND
1.8V power-supply pins for auxiliary circuits
1.8V/2.0V power-supply pins for auxiliary I/O circuits
0.9V/1.0V power-supply pins for the internal core logic
Power-supply pins for the output drivers (per bank)
1.0V power-supply pins for the FPGA logic block RAM
Decryptor key memory backup supply; this pin should be
tied to the appropriate V
CC
or GND when not used
(4)
.
Specific Spartan-7 devices (XC7S6 and XC7S15) do not
support AES encryption. In these devices, connect
VCCBATT_0 to VCCAUX or GND.
These are input threshold voltage pins. They become user
I/Os when an external threshold voltage is not needed
(per bank).
VCCBATT_0DedicatedN/A
VREFMulti-functionN/A
Analog to Digital Converter (XADC) Pins
For more information, see the XADC Package Pins table in UG480, 7Series FPGAs and Zynq-7000 All
Programmable SoC XADC Dual 12-Bit 1 MSPS Analog-to-Digital Converter User Guide
XADC analog positive supply voltage
VCCADC_0
(5)(6)
DedicatedN/A
The XC7S6 and XC7S15 Spartan-7 devices do not support
the XADC. In these devices, connect the VCCADC_0 pin to
VCCAUX.
XADC analog ground reference
GNDADC_0
(5)(6)
VP_0
(5)
VN_0
(5)
VREFP_0
(5)
VREFN_ 0
(5)
AD0P through AD15P
AD0N through AD15N
DedicatedN/A
The XC7S6 and XC7S15 Spartan-7 devices do not support
the XADC. In these devices, connect the GNDADC_0 pin to
GND.
XADC dedicated differential analog input (positive side)
XADC dedicated differential analog input (negative side)
1.25V reference input
1.25V reference GND reference
XADC (analog-to-digital converter) differential auxiliary
analog inputs 0–15.
Auxiliary channels 6, 7, 13, 14, and 15 are not supported
on Kintex-7 devices.
Dedicated
Dedicated
Dedicated
Dedicated
Input
Input
N/A
N/A
Multi-functionInput
7 Series FPGAs Packaging
UG475 (v1.18) July 16, 2019