2024年4月24日发(作者：南门虹颖)
CAT28LV256
256K-Bit CMOS PARALLEL EEPROM
FEATURES
s
3.0V to 3.6V Supply
s
Read Access Times: 200/250/300 ns
s
Low Power CMOS Dissipation:
s
CMOS and TTL Compatible I/O
s
Automatic Page Write Operation:
– Active: 15 mA Max.
– Standby: 150
µ
A Max.
s
Simple Write Operation:
– 1 to 64 Bytes in 10ms
– Page Load Timer
s
End of Write Detection:
– On-Chip Address and Data Latches
– Self-Timed Write Cycle with Auto-Clear
s
Fast Write Cycle Time:
– Toggle Bit
–
DATA
Polling
s
Hardware and Software Write Protection
s
100,000 Program/Erase Cycles
s
100 Year Data Retention
– 10ms Max.
s
Commercial, Industrial and Automotive
Temperature Ranges
DESCRIPTION
The CAT28LV256 is a fast, low power, low voltage
CMOS Parallel E
2
PROM organized as 32K x 8-bits. It
requires a simple interface for in-system programming.
On-chip address and data latches, self-timed write cycle
with auto-clear and V
CC
power up/down write protection
eliminate additional timing and protection hardware.
DATA Polling and Toggle status bits signal the start and
end of the self-timed write cycle. Additionally, the
CAT28LV256 features hardware and software write
protection.
The CAT28LV256 is manufactured using Catalyst’s
advanced CMOS floating gate technology. It is designed
to endure 100,000 program/erase cycles and has a data
retention of 100 years. The device is available in JEDEC–
approved 28-pin DIP, 28-pin TSOP or 32-pin PLCC
packages.
BLOCK DIAGRAM
A
6
–A
14
ADDR. BUFFER
& LATCHES
INADVERTENT
WRITE
PROTECTION
ROW
DECODER
32,768 x 8
E
2
PROM
ARRAY
64 BYTE PAGE
REGISTER
V
CC
HIGH VOLTAGE
GENERATOR
CE
OE
WE
CONTROL
LOGIC
I/O BUFFERS
TIMER
ADDR. BUFFER
& LATCHES
DATA POLLING
AND
TOGGLE BIT
COLUMN
DECODER
28LV256 F01
I/O
0
–I/O
7
A
0
–A
5
© 2009 SCILLC. All rights reserved.
Characteristics subject to change without notice
1
Doc. No. MD-1071, Rev. E
/
CAT28LV256
PIN CONFIGURATION
DIP Package (P, L)
PLCC Package (N, G)
N
C
V
C
C
W
E
A
7
A
1
2
A
1
4
A
1
3
A
14
A
12
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
I/O
0
I/O
1
I/O
2
V
SS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
CC
WE
A
13
A
8
A
9
A
11
OE
A
10
CE
I/O
7
I/O
6
I/O
5
I/O
4
I/O
3
4321323130
A
6
A
5
A
4
A
3
A
2
A
1
A
0
NC
I/O
0
5
6
7
8
9
TOP VIEW
29
28
27
26
25
A
8
A
9
A
11
NC
OE
A
10
CE
I/O
7
I/O
6
1024
1123
1222
1321
920
I
/
O
1
I
/
O
2
V
S
S
N
C
I
/
O
3
I
/
O
4
I
/
O
5
28
27
26
25
24
23
22
21
20
19
18
17
16
15
TSOP Top View (8mm X 13.4mm) (H)
OE
A
11
A
9
A
8
A
13
WE
V
CC
A
14
A
12
A
7
A
6
A
5
A
4
A
3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
A
10
CE
I/O
7
I/O
6
I/O
5
I/O
4
I/O
3
GND
I/O
2
I/O
1
I/O
0
A
0
A
1
A
2
PIN FUNCTIONS
Pin Name
A
0
–A
14
I/O
0
–I/O
7
CE
OE
Function
Address Inputs
Data Inputs/Outputs
Chip Enable
Output Enable
Pin Name
WE
V
CC
V
SS
NC
Function
Write Enable
3.0 to 3.6 V Supply
Ground
No Connect
Doc. No. MD-1071, Rev. E
2
© 2009 SCILLC. All rights reserved.
Characteristics subject to change without notice
/
2024年4月24日发(作者：南门虹颖)
CAT28LV256
256K-Bit CMOS PARALLEL EEPROM
FEATURES
s
3.0V to 3.6V Supply
s
Read Access Times: 200/250/300 ns
s
Low Power CMOS Dissipation:
s
CMOS and TTL Compatible I/O
s
Automatic Page Write Operation:
– Active: 15 mA Max.
– Standby: 150
µ
A Max.
s
Simple Write Operation:
– 1 to 64 Bytes in 10ms
– Page Load Timer
s
End of Write Detection:
– On-Chip Address and Data Latches
– Self-Timed Write Cycle with Auto-Clear
s
Fast Write Cycle Time:
– Toggle Bit
–
DATA
Polling
s
Hardware and Software Write Protection
s
100,000 Program/Erase Cycles
s
100 Year Data Retention
– 10ms Max.
s
Commercial, Industrial and Automotive
Temperature Ranges
DESCRIPTION
The CAT28LV256 is a fast, low power, low voltage
CMOS Parallel E
2
PROM organized as 32K x 8-bits. It
requires a simple interface for in-system programming.
On-chip address and data latches, self-timed write cycle
with auto-clear and V
CC
power up/down write protection
eliminate additional timing and protection hardware.
DATA Polling and Toggle status bits signal the start and
end of the self-timed write cycle. Additionally, the
CAT28LV256 features hardware and software write
protection.
The CAT28LV256 is manufactured using Catalyst’s
advanced CMOS floating gate technology. It is designed
to endure 100,000 program/erase cycles and has a data
retention of 100 years. The device is available in JEDEC–
approved 28-pin DIP, 28-pin TSOP or 32-pin PLCC
packages.
BLOCK DIAGRAM
A
6
–A
14
ADDR. BUFFER
& LATCHES
INADVERTENT
WRITE
PROTECTION
ROW
DECODER
32,768 x 8
E
2
PROM
ARRAY
64 BYTE PAGE
REGISTER
V
CC
HIGH VOLTAGE
GENERATOR
CE
OE
WE
CONTROL
LOGIC
I/O BUFFERS
TIMER
ADDR. BUFFER
& LATCHES
DATA POLLING
AND
TOGGLE BIT
COLUMN
DECODER
28LV256 F01
I/O
0
–I/O
7
A
0
–A
5
© 2009 SCILLC. All rights reserved.
Characteristics subject to change without notice
1
Doc. No. MD-1071, Rev. E
/
CAT28LV256
PIN CONFIGURATION
DIP Package (P, L)
PLCC Package (N, G)
N
C
V
C
C
W
E
A
7
A
1
2
A
1
4
A
1
3
A
14
A
12
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
I/O
0
I/O
1
I/O
2
V
SS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
CC
WE
A
13
A
8
A
9
A
11
OE
A
10
CE
I/O
7
I/O
6
I/O
5
I/O
4
I/O
3
4321323130
A
6
A
5
A
4
A
3
A
2
A
1
A
0
NC
I/O
0
5
6
7
8
9
TOP VIEW
29
28
27
26
25
A
8
A
9
A
11
NC
OE
A
10
CE
I/O
7
I/O
6
1024
1123
1222
1321
920
I
/
O
1
I
/
O
2
V
S
S
N
C
I
/
O
3
I
/
O
4
I
/
O
5
28
27
26
25
24
23
22
21
20
19
18
17
16
15
TSOP Top View (8mm X 13.4mm) (H)
OE
A
11
A
9
A
8
A
13
WE
V
CC
A
14
A
12
A
7
A
6
A
5
A
4
A
3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
A
10
CE
I/O
7
I/O
6
I/O
5
I/O
4
I/O
3
GND
I/O
2
I/O
1
I/O
0
A
0
A
1
A
2
PIN FUNCTIONS
Pin Name
A
0
–A
14
I/O
0
–I/O
7
CE
OE
Function
Address Inputs
Data Inputs/Outputs
Chip Enable
Output Enable
Pin Name
WE
V
CC
V
SS
NC
Function
Write Enable
3.0 to 3.6 V Supply
Ground
No Connect
Doc. No. MD-1071, Rev. E
2
© 2009 SCILLC. All rights reserved.
Characteristics subject to change without notice
/