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2024年4月4日发(作者：巧临)

CS5530

24-bit ADC

with

Ultra-low-noise Amplifier

Features & Description



Chopper-stabilized Instrumentation

General Description

The CS5530 is a highly integrated ΔΣ Analog-to-Digital

Converter (ADC) which uses charge-balance techniques

to achieve 24-bit performance. The ADC is optimized for

measuring low-level unipolar or bipolar signals in weigh

scale, process control, scientific, and medical

applications.

To accommodate these applications, the ADC

includes

a very-low-noise, chopper-stabilized instrumentation

amplifier (12nV/√Hz

@0.1Hz) with a gain of 64X. This

device also includes a fourth-order ΔΣ modulator fol-

lowed by a digital filter

which provides twenty selectable

output word rates of 6.25, 7.5, 12.5, 15, 25, 30, 50, 60, 100,

120, 200, 240, 400, 480, 800, 960, 1600, 1920, 3200, and

3840 Sps (MCLK=4.9152MHz).

To ease communication between the ADC and a micro-

controller, the converter includes a simple three-wire se-

rial interface which is SPI and Microwire compatible with

a Schmitt-trigger input on the serial clock (SCLK).

High dynamic range, programmable output rates, and

flexible power supply options make this device an ideal

solution for weigh scale and process control

applications.

ORDERING INFORMATION

See page35.

Amplifier, 64X

• 12 nV/√Hz @ 0.1 Hz (No 1/f noise)

• 1200pA Input Current



Digital Gain Scaling up to 40x



Delta-sigma Analog-to-digital Converter

• Linearity Error: 0.0015% FS

• Noise Free Resolution: Up to 19 bits



Scalable V

REF

Input: Up to Analog Supply



Simple Three-wire Serial Interface

• SPI™ and Microwire™ Compatible

• Schmitt-trigger on Serial Clock (SCLK)



Onboard Offset and Gain Calibration

Registers



Selectable Word Rates: 6.25 to 3,840 Sps



Selectable 50 or 60 Hz Rejection



Power Supply Configurations

• VA+ = +5 V; VA- = 0 V; VD+ = +3 V to +5 V

• VA+ = +2.5 V; VA- = -2.5 V; VD+ = +3 V to +5 V

• VA+ = +3 V; VA- = -3 V; VD+ = +3 V

VA+C1C2VREF+VREF-VD+

AIN1+

AIN1-

64X

DIFFERENTIAL

ORDER ΔΣ

MODULATOR

PROGRAMMABLE

SINC FIR FILTER

SERIAL

INTERFACE

SDI

SDO

SCLK

LATCH

CLOCK

GENERATOR

CALIBRATION

SRAM/CONTROL

LOGIC

VA-A0A1OSC1OSC2DGND

NOV ‘09

DS742F3

CS5530

TABLE OF CONTENTS

TERISTICS AND SPECIFICATIONS .................................................................4

TYPICAL NOISE-FREE RESOLUTION (BITS)........................................................6

5 V 7

3 V 7

ABSOLUTE 8

GENERAL DESCRIPTION ..............................................................................................11

Input ...........................................................................................................11

2.1.1. Analog Input Span ..........................................................................................12

2.1.2. Voltage Noise Density Performance ...........................................................12

2.1.3. No Offset DAC ............................................................................................12

ew of ADC Register Structure and Operating Modes ..................................12

2.2.1. System Initialization ....................................................................................12

2.2.2. Command Register Descriptions ................................................................14

2.2.3. Serial Port Interface ....................................................................................16

2.2.4. Reading/Writing On-Chip Registers ............................................................17

uration Register ...........................................................................................17

2.3.1. Power Consumption ...................................................................................17

2.3.2. System Reset Sequence ............................................................................17

2.3.3. Input Short ..................................................................................................17

2.3.4. Voltage Reference Select ..........................................................................17

2.3.5. Output Latch Pins .......................................................................................18

2.3.6. Filter Rate Select ........................................................................................18

2.3.7. Word Rate Select ........................................................................................18

2.3.8. Unipolar/Bipolar Select ...............................................................................18

2.3.9. Open Circuit Detect ....................................................................................18

2.3.10. Configuration Register Description ...........................................................19

ation ..............................................................................................................21

2.4.1. Calibration Registers ..................................................................................21

2.4.2. Gain Register .............................................................................................21

2.4.3. Offset Register ...........................................................................................21

2.4.4. Performing Calibrations ..............................................................................22

2.4.5. System Calibration ......................................................................................22

2.4.6. Calibration Tips ...........................................................................................22

2.4.7. Limitations in Calibration Range .................................................................23

ming Conversions ........................................................................................23

2.5.1. Single Conversion Mode .............................................................................23

2.5.2. Continuous Conversion Mode ....................................................................24

Multiple ADCs Synchronously .....................................................................25

sion Output Coding ....................................................................................25

2.7.1. Conversion Data Output Descriptions ........................................................26

l Filter ............................................................................................................27

Generator .....................................................................................................28

Supply Arrangements .................................................................................28

g Started .......................................................................................................31

Layout ............................................................................................................31

PIN DESCRIPTIONS ......................................................................................................32

Clock Generator ......................................................................................................32

Control Pins and Serial Data I/O .............................................................................32

Measurement and Reference Inputs ......................................................................33

Power Supply Connections .....................................................................................33

SPECIFICATION DEFINITIONS .....................................................................................33

PACKAGE DRAWINGS ..................................................................................................34

ORDERING INFORMATION ..........................................................................................35

ENVIRONMENTAL, MANUFACTURING, & HANDLING INFORMATION ....................35