2024年4月13日发(作者：帅新儿)
元器件交易网
TLV5620C, TLV5620I
QUADRUPLE 8-BIT DIGITAL-TO-ANALOG CONVERTERS
SLAS110B – JANUARY 1995 – REVISED APRIL 1997
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
Four 8-Bit Voltage Output DACs
3-V Single-Supply Operation
Serial Interface
High-Impedance Reference Inputs
Programmable for 1 or 2 Times Output
Range
Simultaneous Update Facility
Internal Power-On Reset
Low-Power Consumption
Half-Buffered Output
D OR N PACKAGE
(TOP VIEW)
GND
REFA
REFB
REFC
REFD
DATA
CLK
1
2
3
4
5
6
7
14
13
12
11
10
9
8
V
DD
LDAC
DACA
DACB
DACC
DACD
LOAD
applications
Programmable Voltage Sources
Digitally Controlled Amplifiers/Attenuators
Mobile Communications
Automatic Test Equipment
Process Monitoring and Control
Signal Synthesis
description
The TLV5620C and TLV5620I are quadruple 8-bit voltage output digital-to-analog converters (DACs) with
buffered reference inputs (high impedance). The DACs produce an output voltage that ranges between either
one or two times the reference voltages and GND; and, the DACs are monotonic. The device is simple to use,
because it runs from a single supply of 3 V to 3.6 V. A power-on reset function is incorporated to ensure
repeatable start-up conditions.
Digital control of the TLV5620C and TLV5620I is over a simple three-wire serial bus that is CMOS compatible
and easily interfaced to all popular microprocessor and microcontroller devices. The 11-bit command word
comprises eightbits of data, two DAC select bits, and a range bit, the latter allowing selection between the times
1 or times 2 output range. The DAC registers are double buffered, allowing a complete set of new values to be
written to the device, then all DAC outputs update simultaneously through control of LDAC. The digital inputs
feature Schmitt triggers for high noise immunity.
The 14-terminal small-outline (SO) package allows digital control of analog functions in space-critical
applications. The TLV5620C is characterized for operation from 0°C to 70°C. The TLV5620I is characterized
for operation from –40°C to 85°C. The TLV5620C and TLV5620I do not require external trimming.
AVAILABLE OPTIONS
PACKAGE
T
A
0°C to 70°C
–40°C to 85°C
SMALL OUTLINE
(D)
TLV5620CD
TLV5620ID
PLASTIC DIP
(N)
TLV5620CN
TLV5620IN
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright © 1997, Texas Instruments Incorporated
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
•
1
元器件交易网
SLAS110B – JANUARY 1995 – REVISED APRIL 1997
TLV5620C, TLV5620I
QUADRUPLE 8-BIT DIGITAL-TO-ANALOG CONVERTERS
functional block diagram
REFA
2
+
–
8
REFB
3
+
–
8
REFC
4
+
–
8
REFD
5
+
–
8
7
6
8
Serial
Interface
13
LDAC
Power-On
Reset
LatchLatch
8
LatchLatch
8
LatchLatch
8
LatchLatch
8
12
DAC
× 2
+
–
DACA
DAC
× 2
+
–
11
DACB
DAC
× 2
+
–
10
DACC
DAC
× 2
+
–
9
DACD
CLK
DATA
LOAD
Terminal Functions
TERMINAL
NAME
CLK
DACA
DACB
DACC
DACD
DATA
GND
LDAC
LOAD
REFA
REFB
REFC
REFD
V
DD
NO.
7
12
11
10
9
6
1
13
8
2
3
4
5
14
I/O
I
O
O
O
O
I
I
I
I
I
I
I
I
I
DESCRIPTION
Serial interface clock. The input digital data is shifted into the serial interface register on the falling edge of the clock
applied to the CLK terminal.
DAC A analog output
DAC B analog output
DAC C analog output
DAC D analog output
Serial interface digital data input. The digital code for the DAC is clocked into the serial interface register serially.
Each data bit is clocked into the register on the falling edge of the clock signal.
Ground return and reference terminal
Load DAC. When this signal is high, no DAC output updates occur when the input digital data is read into the serial
interface. The DAC outputs are only updated when LDAC is taken from high to low.
Serial interface load control. When the LDAC terminal is low, the falling edge of the LOAD signal latches the digital
data into the output latch and immediately produces the analog voltage at the DAC output terminal.
Reference voltage input to DAC A. This voltage defines the output analog range.
Reference voltage input to DAC B. This voltage defines the analog output range.
Reference voltage input to DAC C. This voltage defines the analog output range.
Reference voltage input to DAC D. This voltage defines the analog output range.
Positive supply voltage
2
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
•
2024年4月13日发(作者：帅新儿)
元器件交易网
TLV5620C, TLV5620I
QUADRUPLE 8-BIT DIGITAL-TO-ANALOG CONVERTERS
SLAS110B – JANUARY 1995 – REVISED APRIL 1997
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
Four 8-Bit Voltage Output DACs
3-V Single-Supply Operation
Serial Interface
High-Impedance Reference Inputs
Programmable for 1 or 2 Times Output
Range
Simultaneous Update Facility
Internal Power-On Reset
Low-Power Consumption
Half-Buffered Output
D OR N PACKAGE
(TOP VIEW)
GND
REFA
REFB
REFC
REFD
DATA
CLK
1
2
3
4
5
6
7
14
13
12
11
10
9
8
V
DD
LDAC
DACA
DACB
DACC
DACD
LOAD
applications
Programmable Voltage Sources
Digitally Controlled Amplifiers/Attenuators
Mobile Communications
Automatic Test Equipment
Process Monitoring and Control
Signal Synthesis
description
The TLV5620C and TLV5620I are quadruple 8-bit voltage output digital-to-analog converters (DACs) with
buffered reference inputs (high impedance). The DACs produce an output voltage that ranges between either
one or two times the reference voltages and GND; and, the DACs are monotonic. The device is simple to use,
because it runs from a single supply of 3 V to 3.6 V. A power-on reset function is incorporated to ensure
repeatable start-up conditions.
Digital control of the TLV5620C and TLV5620I is over a simple three-wire serial bus that is CMOS compatible
and easily interfaced to all popular microprocessor and microcontroller devices. The 11-bit command word
comprises eightbits of data, two DAC select bits, and a range bit, the latter allowing selection between the times
1 or times 2 output range. The DAC registers are double buffered, allowing a complete set of new values to be
written to the device, then all DAC outputs update simultaneously through control of LDAC. The digital inputs
feature Schmitt triggers for high noise immunity.
The 14-terminal small-outline (SO) package allows digital control of analog functions in space-critical
applications. The TLV5620C is characterized for operation from 0°C to 70°C. The TLV5620I is characterized
for operation from –40°C to 85°C. The TLV5620C and TLV5620I do not require external trimming.
AVAILABLE OPTIONS
PACKAGE
T
A
0°C to 70°C
–40°C to 85°C
SMALL OUTLINE
(D)
TLV5620CD
TLV5620ID
PLASTIC DIP
(N)
TLV5620CN
TLV5620IN
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright © 1997, Texas Instruments Incorporated
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
•
1
元器件交易网
SLAS110B – JANUARY 1995 – REVISED APRIL 1997
TLV5620C, TLV5620I
QUADRUPLE 8-BIT DIGITAL-TO-ANALOG CONVERTERS
functional block diagram
REFA
2
+
–
8
REFB
3
+
–
8
REFC
4
+
–
8
REFD
5
+
–
8
7
6
8
Serial
Interface
13
LDAC
Power-On
Reset
LatchLatch
8
LatchLatch
8
LatchLatch
8
LatchLatch
8
12
DAC
× 2
+
–
DACA
DAC
× 2
+
–
11
DACB
DAC
× 2
+
–
10
DACC
DAC
× 2
+
–
9
DACD
CLK
DATA
LOAD
Terminal Functions
TERMINAL
NAME
CLK
DACA
DACB
DACC
DACD
DATA
GND
LDAC
LOAD
REFA
REFB
REFC
REFD
V
DD
NO.
7
12
11
10
9
6
1
13
8
2
3
4
5
14
I/O
I
O
O
O
O
I
I
I
I
I
I
I
I
I
DESCRIPTION
Serial interface clock. The input digital data is shifted into the serial interface register on the falling edge of the clock
applied to the CLK terminal.
DAC A analog output
DAC B analog output
DAC C analog output
DAC D analog output
Serial interface digital data input. The digital code for the DAC is clocked into the serial interface register serially.
Each data bit is clocked into the register on the falling edge of the clock signal.
Ground return and reference terminal
Load DAC. When this signal is high, no DAC output updates occur when the input digital data is read into the serial
interface. The DAC outputs are only updated when LDAC is taken from high to low.
Serial interface load control. When the LDAC terminal is low, the falling edge of the LOAD signal latches the digital
data into the output latch and immediately produces the analog voltage at the DAC output terminal.
Reference voltage input to DAC A. This voltage defines the output analog range.
Reference voltage input to DAC B. This voltage defines the analog output range.
Reference voltage input to DAC C. This voltage defines the analog output range.
Reference voltage input to DAC D. This voltage defines the analog output range.
Positive supply voltage
2
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
•