2024年4月23日发(作者：胡平凡)
元器件交易网
HY62V8100B Series
128Kx8bit CMOS SRAM
Document Title
128K x8 bit 3.3V Low Power CMOS slow SRAM
Revision History
Revision No History Draft Date Remark
10 Initial Revision History Insert Jul.14.2000 Final
11 Change the Notch Location of sTSOP Sep.04.2000 Final
- Left-Top => Left-Center
12 Marking Information Add Dec.04.2000 Final
Revised
- AC Test Condition Add : 5pF Test Load
13 Changed Logo Apr.30.2001 Final
- HYUNDAI -> hynix
- Marking Information Change
This document is a general product description and is subject to change without notice. Hynix Electronics does not assume any
responsibility for use of circuits described. No patent licenses are implied.
Rev 13 / Apr. 2001 Hynix Semiconductor
元器件交易网
HY62V8100B Series
DESCRIPTION
FEATURES
• Fully static operation and Tri-state output
• TTL compatible inputs and outputs
• Battery backup(LL-part)
-. 2.0V(min) data retention
• Standard pin configuration
-. 32 SOP - 525mil
-. 32 TSOP-I - 8X20(Standard and Reversed)
-. 32 sTSOP-I - 8X13.4
(Standard and Reversed)
The HY62V8100B is a high speed, low power and
1M bit CMOS SRAM organized as 131,072 words
by 8bit. The HY62V8100B uses high performance
CMOS process technology and designed for high
speed low power circuit technology. It is
particulary well suited for used in high density low
power system application. This device has a data
retention mode that guarantees data to remain
valid at a minimum power supply voltage of 2.0V.
Product Voltage Speed Operation Standby Current(uA) Temperature
No. (V) (ns) Current/Icc(mA) LL
(°C)
HY62V8100B 3.0~3.6 70/85/100 5 10 0~70
HY62V8100B-E 3.0~3.6 70/85/100 5 15 -25~85(E)
HY62V8100B-I 3.0~3.6 70/85/100 5 15 -40~85(I)
Note 1. Blank : Commercial, E : Extended, I : Industrial
2. Current value is max.
PIN CONNECTION
NC
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O1
I/O2
I/O3
Vss
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
Vcc
A15
CS2
/WE
A13
A8
A9
A11
/OE
A10
/CS1
I/O8
I/O7
I/O6
I/O5
I/O4
A11
A9
A8
A13
/WE
CS2
A15
Vcc
NC
A16
A14
A12
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
/OE
A11
1
A10
A9
2
/CS1
A8
3
DQ8
A13
4
DQ7
/WE
5
DQ6
CS2
6
DQ5
A15
7
DQ4
Vcc
8
9
Vss
NC
10
DQ3
A16
A14
DQ2
A12
11
DQ1
A7
12
13
A0
A6
14
A1
A5
15
A2
A3
A4
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
/O
E
A10
/CS1
DQ8
DQ7
DQ6
DQ5
DQ4
Vss
DQ3
DQ2
DQ1
A0
A1
A3
A2
SOP TSOP-I sTSOP-I
(Standard) (Standard)
PIN DESCRIPTION BLOCK DIAGRAM
A0
Pin Name Pin Function
/CS1 Chip Select 1
CS2 Chip Select 2
/WE Write Enable
/OE Output Enable
A0 ~ A16 Address Inputs
I/O1 ~ I/O8 Data Inputs / Outputs
Vcc Power(3.0V~3.6V)
A16
Vss Ground
/CS1
CS2
/OE
/WE
ROW
DECODER
SENSE AMP
I/O1
MEMORY ARRAY
128K x 8
Rev 13 / Apr. 2001
ADD INPUT
BUFFER
COLUMN
DECODER
DATA I/O
BUFFER
COLUMN
DECODER
WRITE DRIVER
I/O8
2
2024年4月23日发(作者：胡平凡)
元器件交易网
HY62V8100B Series
128Kx8bit CMOS SRAM
Document Title
128K x8 bit 3.3V Low Power CMOS slow SRAM
Revision History
Revision No History Draft Date Remark
10 Initial Revision History Insert Jul.14.2000 Final
11 Change the Notch Location of sTSOP Sep.04.2000 Final
- Left-Top => Left-Center
12 Marking Information Add Dec.04.2000 Final
Revised
- AC Test Condition Add : 5pF Test Load
13 Changed Logo Apr.30.2001 Final
- HYUNDAI -> hynix
- Marking Information Change
This document is a general product description and is subject to change without notice. Hynix Electronics does not assume any
responsibility for use of circuits described. No patent licenses are implied.
Rev 13 / Apr. 2001 Hynix Semiconductor
元器件交易网
HY62V8100B Series
DESCRIPTION
FEATURES
• Fully static operation and Tri-state output
• TTL compatible inputs and outputs
• Battery backup(LL-part)
-. 2.0V(min) data retention
• Standard pin configuration
-. 32 SOP - 525mil
-. 32 TSOP-I - 8X20(Standard and Reversed)
-. 32 sTSOP-I - 8X13.4
(Standard and Reversed)
The HY62V8100B is a high speed, low power and
1M bit CMOS SRAM organized as 131,072 words
by 8bit. The HY62V8100B uses high performance
CMOS process technology and designed for high
speed low power circuit technology. It is
particulary well suited for used in high density low
power system application. This device has a data
retention mode that guarantees data to remain
valid at a minimum power supply voltage of 2.0V.
Product Voltage Speed Operation Standby Current(uA) Temperature
No. (V) (ns) Current/Icc(mA) LL
(°C)
HY62V8100B 3.0~3.6 70/85/100 5 10 0~70
HY62V8100B-E 3.0~3.6 70/85/100 5 15 -25~85(E)
HY62V8100B-I 3.0~3.6 70/85/100 5 15 -40~85(I)
Note 1. Blank : Commercial, E : Extended, I : Industrial
2. Current value is max.
PIN CONNECTION
NC
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O1
I/O2
I/O3
Vss
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
Vcc
A15
CS2
/WE
A13
A8
A9
A11
/OE
A10
/CS1
I/O8
I/O7
I/O6
I/O5
I/O4
A11
A9
A8
A13
/WE
CS2
A15
Vcc
NC
A16
A14
A12
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
/OE
A11
1
A10
A9
2
/CS1
A8
3
DQ8
A13
4
DQ7
/WE
5
DQ6
CS2
6
DQ5
A15
7
DQ4
Vcc
8
9
Vss
NC
10
DQ3
A16
A14
DQ2
A12
11
DQ1
A7
12
13
A0
A6
14
A1
A5
15
A2
A3
A4
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
/O
E
A10
/CS1
DQ8
DQ7
DQ6
DQ5
DQ4
Vss
DQ3
DQ2
DQ1
A0
A1
A3
A2
SOP TSOP-I sTSOP-I
(Standard) (Standard)
PIN DESCRIPTION BLOCK DIAGRAM
A0
Pin Name Pin Function
/CS1 Chip Select 1
CS2 Chip Select 2
/WE Write Enable
/OE Output Enable
A0 ~ A16 Address Inputs
I/O1 ~ I/O8 Data Inputs / Outputs
Vcc Power(3.0V~3.6V)
A16
Vss Ground
/CS1
CS2
/OE
/WE
ROW
DECODER
SENSE AMP
I/O1
MEMORY ARRAY
128K x 8
Rev 13 / Apr. 2001
ADD INPUT
BUFFER
COLUMN
DECODER
DATA I/O
BUFFER
COLUMN
DECODER
WRITE DRIVER
I/O8
2