2024年6月5日发(作者：虎翠桃)
Pinout
144144
LQFPMAP
BGA
48
49
50
J4
H4
J5
Pin NameDefaultALT0ALT1ALT2ALT3ALT4ALT5ALT6ALT7EzPort
PTE27
PTE28
PTA0
DISABLED
DISABLED
JTAG_TCLK/
SWD_CLK/
EZP_CLK
JTAG_TDI/
EZP_DI
TSI0_CH1
PTE27
PTE28
PTA0
UART4_RTS_
b
UART0_CTS_FTM0_CH5
b/
UART0_COL_
b
UART0_RX
UART0_TX
FTM0_CH6
FTM0_CH7
JTAG_TCLK/
SWD_CLK
EZP_CLK
51
52
J6
K6
PTA1
PTA2
TSI0_CH2PTA1
PTA2
JTAG_TDIEZP_DI
JTAG_TDO/TSI0_CH3
TRACE_SWO/
EZP_DO
JTAG_TMS/
SWD_DIO
NMI_b/
EZP_CS_b
DISABLED
VDD
VSS
DISABLED
ADC0_SE10
ADC0_SE11
DISABLED
DISABLED
DISABLED
CMP2_IN0
CMP2_IN1
DISABLED
DISABLED
DISABLED
CMP2_IN0
CMP2_IN1
ADC0_SE10
ADC0_SE11
VDD
VSS
TSI0_CH4
TSI0_CH5
JTAG_TDO/EZP_DO
TRACE_SWO
JTAG_TMS/
SWD_DIO
NMI_b
CMP2_OUTI2S0_TX_
BCLK
JTAG_TRST_
b
EZP_CS_b
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
K7
L7
M8
E7
G7
J7
J8
K8
L8
M9
L9
K9
J9
L10
L11
K10
PTA3
PTA4/
LLWU_P3
PTA5
VDD
VSS
PTA6
PTA7
PTA8
PTA9
PTA10
PTA11
PTA12
PTA13/
LLWU_P4
PTA14
PTA15
PTA16
PTA3
PTA4/
LLWU_P3
PTA5
UART0_RTS_FTM0_CH0
b
FTM0_CH1
USB_CLKINFTM0_CH2
PTA6
PTA7
PTA8
PTA9
PTA10
PTA11
PTA12
PTA13/
LLWU_P4
PTA14
PTA15
PTA16
CAN0_TX
CAN0_RX
SPI0_PCS0
SPI0_SCK
SPI0_SOUT
FTM0_CH3
FTM0_CH4
FTM1_CH0
FTM1_CH1
FTM2_CH0
FTM2_CH1
FTM1_CH0
FTM1_CH1
UART0_TX
UART0_RX
UART0_CTS_
b/
UART0_COL_
b
UART0_RTS_
b
FTM1_QD_
PHA
FTM1_QD_
PHB
FTM2_QD_
PHA
FTM2_QD_
PHB
I2S0_TXD0
I2S0_TX_FS
I2S0_RX_
BCLK
I2S0_RXD0
I2S0_RX_FS
TRACE_
CLKOUT
TRACE_D3
TRACE_D2
TRACE_D1
TRACE_D0
FTM1_QD_
PHA
FTM1_QD_
PHB
I2S0_TXD1
I2S0_RXD1
69
70
71
72
K11
E8
G8
PTA17
VDD
VSS
ADC1_SE17
VDD
VSS
EXTAL0
ADC1_SE17
VDD
VSS
EXTAL0
PTA17SPI0_SINI2S0_MCLK
M12PTA18PTA18FTM0_FLT2FTM_CLKIN0
K20 Sub-Family Data Sheet, Rev. 3, 6/2013.
Freescale Semiconductor, Inc.75
2024年6月5日发(作者：虎翠桃)
Pinout
144144
LQFPMAP
BGA
48
49
50
J4
H4
J5
Pin NameDefaultALT0ALT1ALT2ALT3ALT4ALT5ALT6ALT7EzPort
PTE27
PTE28
PTA0
DISABLED
DISABLED
JTAG_TCLK/
SWD_CLK/
EZP_CLK
JTAG_TDI/
EZP_DI
TSI0_CH1
PTE27
PTE28
PTA0
UART4_RTS_
b
UART0_CTS_FTM0_CH5
b/
UART0_COL_
b
UART0_RX
UART0_TX
FTM0_CH6
FTM0_CH7
JTAG_TCLK/
SWD_CLK
EZP_CLK
51
52
J6
K6
PTA1
PTA2
TSI0_CH2PTA1
PTA2
JTAG_TDIEZP_DI
JTAG_TDO/TSI0_CH3
TRACE_SWO/
EZP_DO
JTAG_TMS/
SWD_DIO
NMI_b/
EZP_CS_b
DISABLED
VDD
VSS
DISABLED
ADC0_SE10
ADC0_SE11
DISABLED
DISABLED
DISABLED
CMP2_IN0
CMP2_IN1
DISABLED
DISABLED
DISABLED
CMP2_IN0
CMP2_IN1
ADC0_SE10
ADC0_SE11
VDD
VSS
TSI0_CH4
TSI0_CH5
JTAG_TDO/EZP_DO
TRACE_SWO
JTAG_TMS/
SWD_DIO
NMI_b
CMP2_OUTI2S0_TX_
BCLK
JTAG_TRST_
b
EZP_CS_b
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
K7
L7
M8
E7
G7
J7
J8
K8
L8
M9
L9
K9
J9
L10
L11
K10
PTA3
PTA4/
LLWU_P3
PTA5
VDD
VSS
PTA6
PTA7
PTA8
PTA9
PTA10
PTA11
PTA12
PTA13/
LLWU_P4
PTA14
PTA15
PTA16
PTA3
PTA4/
LLWU_P3
PTA5
UART0_RTS_FTM0_CH0
b
FTM0_CH1
USB_CLKINFTM0_CH2
PTA6
PTA7
PTA8
PTA9
PTA10
PTA11
PTA12
PTA13/
LLWU_P4
PTA14
PTA15
PTA16
CAN0_TX
CAN0_RX
SPI0_PCS0
SPI0_SCK
SPI0_SOUT
FTM0_CH3
FTM0_CH4
FTM1_CH0
FTM1_CH1
FTM2_CH0
FTM2_CH1
FTM1_CH0
FTM1_CH1
UART0_TX
UART0_RX
UART0_CTS_
b/
UART0_COL_
b
UART0_RTS_
b
FTM1_QD_
PHA
FTM1_QD_
PHB
FTM2_QD_
PHA
FTM2_QD_
PHB
I2S0_TXD0
I2S0_TX_FS
I2S0_RX_
BCLK
I2S0_RXD0
I2S0_RX_FS
TRACE_
CLKOUT
TRACE_D3
TRACE_D2
TRACE_D1
TRACE_D0
FTM1_QD_
PHA
FTM1_QD_
PHB
I2S0_TXD1
I2S0_RXD1
69
70
71
72
K11
E8
G8
PTA17
VDD
VSS
ADC1_SE17
VDD
VSS
EXTAL0
ADC1_SE17
VDD
VSS
EXTAL0
PTA17SPI0_SINI2S0_MCLK
M12PTA18PTA18FTM0_FLT2FTM_CLKIN0
K20 Sub-Family Data Sheet, Rev. 3, 6/2013.
Freescale Semiconductor, Inc.75