2024年2月16日发(作者：况逸云)
元器件交易网4043BC
• CD4044BC Quad 3-STATE NOR R/S Latches • Quad 3-STATE NAND R/S LatchesOctober 1987Revised January 1999CD4043BC • CD4044BCQuad 3-STATE NOR R/S Latches •
Quad 3-STATE NAND R/S LatchesGeneral DescriptionThe CD4043BC are quad cross-couple 3-STATE CMOSNOR latches, and the CD4044BC are quad cross-couple 3-STATE CMOS NAND latches. Each latch has a separate Qoutput and individual SET and RESET inputs. There is acommon 3-STATE ENABLE input for all four latches. Alogic “1” on the ENABLE input connects the latch states tothe Q outputs. A logic “0” on the ENABLE input discon-nects the latch states from the Q outputs resulting in anopen circuit condition on the Q output. The 3-STATE fea-ture allows common bussing of the essWide supply voltage range: 3V to 15VsLow power:100 nW (typ.)sHigh noise immunity:0.45 VDD (typ.)sSeparate SET and RESET inputs for each latchsNOR and NAND configurations3-STATE output with common output enableApplications•Multiple bus storage•Strobed register•Four bits of independent storage with output enable•General digital logic
Ordering Code:Order NumberCD4043BCMCD4043BCNCD4044BCMCD4044BCSJCD4044BCNPackage NumberM16AN16EM16AM16DN16EPackage Description16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” WideDevices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering tion DiagramsPin Assignments for DIP, SOIC and SOPCD4043BCPin Assignments for DIP and SOICCD4044BCTop ViewTop View© 1999 Fairchild Semiconductor
元器件交易网4043BC
•
CD4044BCBlock DiagramsCD4043BCCD4044BCTruth TablesCD4043BCSX0101RX0011E01111QOCNC10∆SX1010CD4044BCRX1100E01111QOCNC10∆∆OC = 3-STATENC = No changeX = Don’t care∆ = Dominated by S = 1 input∆∆ = Dominated by R = 0 2
元器件交易网4043BC
• CD4044BC
Absolute Maximum Ratings(Note 1)(Note 2)Supply Voltage (VDD)Input Voltage (VIN)Storage Temperature Range (TS)Power Dissipation (PD)Dual-In-LineSmall OutlineLead Temperature (TL)(Soldering, 10 seconds)260°C700 mW500 mW−0.5V to +18V−0.5V to VDD +0.5V−65°C to +150°CRecommended Operating
Conditions
(Note 2)Supply Voltage (VDD)Input Voltage (VIN)Operating Temperature Range (TA)CD4043BC, CD4044BC−40°C to +85°CNote 1: “Absolute Maximum Ratings” are those values beyond which thesafety of the device cannot be guaranteed; they are not meant to imply thatthe devices should be operated at these limits. The tables of “Recom-mended Operating Conditions” and “Electrical Characteristics” provide con-ditions for actual device 2: VSS = 0V unless otherwise specified.3.0V to 15V0 to VDD VDC Electrical Characteristics
(Note 2)SymbolIDDParameterQuiescentDevice CurrentVOLLOW LevelOutput VoltageConditionsVDD = 5V, VIN = VDD or VSSVDD = 10V, VIN = VDD or VSSVDD = 15V, VIN = VDD or VSS|IO| ≤ 1 µA, VIL = 0V, VIH = VDDVDD = 5.0VVDD = 10VVDD = 15VVOHHIGH LevelOutput Voltage|IO| ≤ 1 µA, VIL = 0V, VIH = VDDVDD = 5.0VVDD = 10VVDD = 15VVILLOW LevelInput Voltage|IO| ≤ 1 µAVDD = 5.0V, VO = 0.5V or 4.5VVDD = 10V, VO = 1.0V or 9.0VVDD = 15V, VO = 1.5V or 13.5VVIHHIGH LevelInput Voltage|IO| ≤ 1 µAVDD = 5.0V, VO = 0.5V or 4.5VVDD = 5.0V, VO = 1.0V or 9.0VVDD = 15V, VO = 1.5V or 13.5VIOLLOW LevelOutput Current(Note 3)IOHHIGH LevelOutput Current(Note 3)IINInput CurrentVIL = 0V, VIH = VDDVDD = 5.0V, VO = 0.4VVDD = 10V, VO = 0.5VVDD = 15V, VO = 1.5VVIL = 0V, VIH = VDDVDD = 5.0V, VO = 4.6VVDD = 10V, VO = 9.5VVDD = 15V, VO = 13.5VVDD = 15V, VIN = 0VVDD = 15V, VIN = 15VNote 3: IOH and IOL are tested one output at a time.−40°CMinMax2040800.050.050.054.959.9514.951.53.04.03.57.0110.521.33.6−0.52−1.3−3.6−0.30.33.57.0110.441.13.0−0.44−1.1−3.04.959.9514.95Min+25°CTyp0.010.010.020005.010152.254.56.751.53.04.0Max2040800.050.050.05+85°CMinMax1503006000.050.050.054.959.9514.951.53.04.03.57.011UnitsµAµAµAVVVVVVVVVVVVmAmAmAmAmAmA0.882.26.0−0.32−0.8−2.4−0.30.30.360.92.4−0.36−0.9−2.4−1.01.0µAµ
元器件交易网4043BC
•
CD4044BCAC Electrical Characteristics
(Note 4)TA
= 25°C, CL
= 50 pF, RL
= 200k, input tr
= tf = 20 ns, unless otherwise notedSymboltPLH, tPHLParameterPropagation Delay S or R to QVDD = 5.0VVDD = 10VVDD = 15VtPZH, tPHZPropagation Delay Enable to Q (HIGH)VDD = 5.0VVDD = 10VVDD = 15VtPZL, tPLZPropagation Delay Enable to Q (LOW)VDD = 5.0VVDD = 10VVDD = 15VtTHL, tTLHTransition TimeVDD = 5.0VVDD = 10VVDD = 15VtWOMinimum SET or RESET Pulse WidthVDD = 5.0VVDD = 10VVDD = 15VCINInput CapacitanceNote 4: AC Parameters are guaranteed by DC correlated ionsMinTyp.0Max35407.5UnitsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnspFTiming Waveforms
CD4043BCD4044BEnable 4
元器件交易网4043BC
• CD4044BC
Physical Dimensions
inches (millimeters) unless otherwise noted16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow BodyPackage Number M16A16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm WidePackage Number
元器件交易网4043BC
•
CD4044BC
Quad
3-STATE
NOR
R/S
Latches
•
Quad
3-STATE
NAND
R/S
LatchesPhysical Dimensions
inches (millimeters) unless otherwise noted (Continued)16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” WidePackage Number N16ELIFE SUPPORT POLICYFAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORTDEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILDSEMICONDUCTOR CORPORATION. As used herein:2.A critical component in any component of a life support devices or systems are devices or systemsdevice or system whose failure to perform can be rea-which, (a) are intended for surgical implant into thesonably expected to cause the failure of the life supportbody, or (b) support or sustain life, and (c) whose failuredevice or system, or to affect its safety or perform when properly used in accordance withinstructions for use provided in the labeling, can be rea-sonably expected to result in a significant injury to ild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.
2024年2月16日发(作者：况逸云)
元器件交易网4043BC
• CD4044BC Quad 3-STATE NOR R/S Latches • Quad 3-STATE NAND R/S LatchesOctober 1987Revised January 1999CD4043BC • CD4044BCQuad 3-STATE NOR R/S Latches •
Quad 3-STATE NAND R/S LatchesGeneral DescriptionThe CD4043BC are quad cross-couple 3-STATE CMOSNOR latches, and the CD4044BC are quad cross-couple 3-STATE CMOS NAND latches. Each latch has a separate Qoutput and individual SET and RESET inputs. There is acommon 3-STATE ENABLE input for all four latches. Alogic “1” on the ENABLE input connects the latch states tothe Q outputs. A logic “0” on the ENABLE input discon-nects the latch states from the Q outputs resulting in anopen circuit condition on the Q output. The 3-STATE fea-ture allows common bussing of the essWide supply voltage range: 3V to 15VsLow power:100 nW (typ.)sHigh noise immunity:0.45 VDD (typ.)sSeparate SET and RESET inputs for each latchsNOR and NAND configurations3-STATE output with common output enableApplications•Multiple bus storage•Strobed register•Four bits of independent storage with output enable•General digital logic
Ordering Code:Order NumberCD4043BCMCD4043BCNCD4044BCMCD4044BCSJCD4044BCNPackage NumberM16AN16EM16AM16DN16EPackage Description16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” WideDevices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering tion DiagramsPin Assignments for DIP, SOIC and SOPCD4043BCPin Assignments for DIP and SOICCD4044BCTop ViewTop View© 1999 Fairchild Semiconductor
元器件交易网4043BC
•
CD4044BCBlock DiagramsCD4043BCCD4044BCTruth TablesCD4043BCSX0101RX0011E01111QOCNC10∆SX1010CD4044BCRX1100E01111QOCNC10∆∆OC = 3-STATENC = No changeX = Don’t care∆ = Dominated by S = 1 input∆∆ = Dominated by R = 0 2
元器件交易网4043BC
• CD4044BC
Absolute Maximum Ratings(Note 1)(Note 2)Supply Voltage (VDD)Input Voltage (VIN)Storage Temperature Range (TS)Power Dissipation (PD)Dual-In-LineSmall OutlineLead Temperature (TL)(Soldering, 10 seconds)260°C700 mW500 mW−0.5V to +18V−0.5V to VDD +0.5V−65°C to +150°CRecommended Operating
Conditions
(Note 2)Supply Voltage (VDD)Input Voltage (VIN)Operating Temperature Range (TA)CD4043BC, CD4044BC−40°C to +85°CNote 1: “Absolute Maximum Ratings” are those values beyond which thesafety of the device cannot be guaranteed; they are not meant to imply thatthe devices should be operated at these limits. The tables of “Recom-mended Operating Conditions” and “Electrical Characteristics” provide con-ditions for actual device 2: VSS = 0V unless otherwise specified.3.0V to 15V0 to VDD VDC Electrical Characteristics
(Note 2)SymbolIDDParameterQuiescentDevice CurrentVOLLOW LevelOutput VoltageConditionsVDD = 5V, VIN = VDD or VSSVDD = 10V, VIN = VDD or VSSVDD = 15V, VIN = VDD or VSS|IO| ≤ 1 µA, VIL = 0V, VIH = VDDVDD = 5.0VVDD = 10VVDD = 15VVOHHIGH LevelOutput Voltage|IO| ≤ 1 µA, VIL = 0V, VIH = VDDVDD = 5.0VVDD = 10VVDD = 15VVILLOW LevelInput Voltage|IO| ≤ 1 µAVDD = 5.0V, VO = 0.5V or 4.5VVDD = 10V, VO = 1.0V or 9.0VVDD = 15V, VO = 1.5V or 13.5VVIHHIGH LevelInput Voltage|IO| ≤ 1 µAVDD = 5.0V, VO = 0.5V or 4.5VVDD = 5.0V, VO = 1.0V or 9.0VVDD = 15V, VO = 1.5V or 13.5VIOLLOW LevelOutput Current(Note 3)IOHHIGH LevelOutput Current(Note 3)IINInput CurrentVIL = 0V, VIH = VDDVDD = 5.0V, VO = 0.4VVDD = 10V, VO = 0.5VVDD = 15V, VO = 1.5VVIL = 0V, VIH = VDDVDD = 5.0V, VO = 4.6VVDD = 10V, VO = 9.5VVDD = 15V, VO = 13.5VVDD = 15V, VIN = 0VVDD = 15V, VIN = 15VNote 3: IOH and IOL are tested one output at a time.−40°CMinMax2040800.050.050.054.959.9514.951.53.04.03.57.0110.521.33.6−0.52−1.3−3.6−0.30.33.57.0110.441.13.0−0.44−1.1−3.04.959.9514.95Min+25°CTyp0.010.010.020005.010152.254.56.751.53.04.0Max2040800.050.050.05+85°CMinMax1503006000.050.050.054.959.9514.951.53.04.03.57.011UnitsµAµAµAVVVVVVVVVVVVmAmAmAmAmAmA0.882.26.0−0.32−0.8−2.4−0.30.30.360.92.4−0.36−0.9−2.4−1.01.0µAµ
元器件交易网4043BC
•
CD4044BCAC Electrical Characteristics
(Note 4)TA
= 25°C, CL
= 50 pF, RL
= 200k, input tr
= tf = 20 ns, unless otherwise notedSymboltPLH, tPHLParameterPropagation Delay S or R to QVDD = 5.0VVDD = 10VVDD = 15VtPZH, tPHZPropagation Delay Enable to Q (HIGH)VDD = 5.0VVDD = 10VVDD = 15VtPZL, tPLZPropagation Delay Enable to Q (LOW)VDD = 5.0VVDD = 10VVDD = 15VtTHL, tTLHTransition TimeVDD = 5.0VVDD = 10VVDD = 15VtWOMinimum SET or RESET Pulse WidthVDD = 5.0VVDD = 10VVDD = 15VCINInput CapacitanceNote 4: AC Parameters are guaranteed by DC correlated ionsMinTyp.0Max35407.5UnitsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnspFTiming Waveforms
CD4043BCD4044BEnable 4
元器件交易网4043BC
• CD4044BC
Physical Dimensions
inches (millimeters) unless otherwise noted16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow BodyPackage Number M16A16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm WidePackage Number
元器件交易网4043BC
•
CD4044BC
Quad
3-STATE
NOR
R/S
Latches
•
Quad
3-STATE
NAND
R/S
LatchesPhysical Dimensions
inches (millimeters) unless otherwise noted (Continued)16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” WidePackage Number N16ELIFE SUPPORT POLICYFAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORTDEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILDSEMICONDUCTOR CORPORATION. As used herein:2.A critical component in any component of a life support devices or systems are devices or systemsdevice or system whose failure to perform can be rea-which, (a) are intended for surgical implant into thesonably expected to cause the failure of the life supportbody, or (b) support or sustain life, and (c) whose failuredevice or system, or to affect its safety or perform when properly used in accordance withinstructions for use provided in the labeling, can be rea-sonably expected to result in a significant injury to ild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.