MEMORY存储芯片MX25R3235FZBIL0中文规格书-USB迷|专注于互联网分享

2024年2月26日发(作者：敛雨伯)

Status RegisterThe definition of the status register bits is as below:

WIP bit. The Write in Progress (WIP) bit, a volatile bit, indicates whether the device is busy in program/erase/write

status register progress. When WIP bit sets to 1, which means the device is busy in program/erase/write status

register bit. The Write Enable Latch (WEL) bit, a volatile bit, indicates whether the device is set to internal write enable

latch. When WEL bit sets to 1, which means the internal write enable latch is set, the device can accept program/erase/write status register instruction. When WEL bit sets to 0, which means no internal write enable latch; the

device will not accept program/erase/write status register instruction. The program/erase command will be ignored

if it is applied to a protected memory area. To ensure both WIP bit & WEL bit are both set to 0 and available for next

program/erase/operations, WIP bit needs to be confirm to be 0 before polling WEL bit. After WIP bit confirmed, WEL

bit needs to be confirmed as 3, BP2, BP1, BP0 bits. The Block Protect (BP3, BP2, BP1, BP0) bits, non-volatile bits, indicate the protected area (as

defined in

"Table 2. Protected Area Sizes") of the device to against the program/erase instruction without hardware

protection mode being set. To write the Block Protect (BP3, BP2, BP1, BP0) bits requires the Write Status Register (WRSR)

instruction to be executed. Those bits define the protected area of the memory to against Page Program (PP), Sector

Erase (SE), Block Erase (BE/BE32K) and Chip Erase (CE) instructions (only if Block Protect bits (BP3:BP0) set to 0,

the CE instruction can be executed). The BP3, BP2, BP1, BP0 bits are "0" as default, which is bit.

The Quad Enable (QE) bit, non-volatile bit, while it is "0" (factory default), it performs non-Quad and WP#,

RESET#/HOLD# are enable. While QE is "1", it performs Quad I/O mode and WP#, RESET#/HOLD# are disabled.

In the other word, if the system goes into four I/O mode (QE=1), the feature of HPM and RESET/HOLD will be

bit. The Status Register Write Disable (SRWD) bit, non-volatile bit, is operated together with Write Protection

(WP#/SIO2) pin for providing hardware protection mode. The hardware protection mode requires SRWD sets to 1 and

WP#/SIO2 pin signal is low stage. In the hardware protection mode, the Write Status Register (WRSR) instruction is

no longer accepted for execution and the SRWD bit and Block Protect bits (BP3, BP2, BP1, BP0) are read only. The

SRWD bit defaults to be "0".

Status Registerbit7SRWD (status

protect)bit6QE(Quad

Enable)bit5BP3

(level of

protected

block)bit4BP2

(level of

protected

block)bit3BP1

(level of

protected

block)bit2BP0

(level of

protected

block)bit1bit0WELWIP(write enable (write in

latch)progress bit)1=write 1=write

enableoperation0=not write 0=not in write

enableoperationvolatile bitvolatile bit1=Quad

1=status

Enableregister write (note 1)(note 1)(note 1)(note 1)0=not Quad

disableEnableNon-volatile Non-volatile Non-volatile Non-volatile Non-volatile Non-volatile

bitbitbitbitbitbitNote 1: see the "Table 2. Protected Area Sizes".P/N: PM2159Rev. 1.5, September 22, 2016

Configuration RegisterThe Configuration Register is able to change the default status of Flash memory. Flash memory will be configured

after the CR bit is set.

TB bitThe Top/Bottom (TB) bit is a non-volatile OTP bit. The Top/Bottom (TB) bit is used to configure the Block Protect

area by BP bit (BP3, BP2, BP1, BP0), starting from TOP or Bottom of the memory array. The TB bit is defaulted as

“0”, which means Top area protect. When it is set as “1”, the protect area will change to Bottom area of the memory

device. To write the TB bit requires the Write Status Register (WRSR) instruction to be executed.L/H switch bitThe Low Power / High Performance bit is a volatile bit. User can change the value of L/H switch bit to keep Ultra

Low Power mode or High Performance mode. Please check Ordering Information for the L/H Switch default

uration Register - 1bit7bit6DCReserved(Dummy

Cycle)2READ/4READ

Dummy

CycleVolatile bitbit5Reservedbit4Reservedxxxxxxbit3TB

(top/bottom

selected)0=Top area

protect

1=Bottom

area protect

(Default=0)OTPbit2Reservedbit1Reservedbit0ReservedxxxxxxConfiguration Register - 2bit7bit6ReservedReservedxxxxbit5Reservedxxbit4Reservedxxbit3Reservedxxbit2Reservedxxbit1bit0L/H SwitchReserved0 = Ultra Low

power mode

1 = High xperformance

modeVolatile bitxDummy Cycle TableDC2READ4READ0 (default)10 (default)1Numbers of Dummy Cycles48610P/N: PM2159Rev. 1.5, September 22, 2016

10-9. Write Status Register (WRSR)The WRSR instruction is for changing the values of Status Register Bits and Configuration Register Bits. Before

sending WRSR instruction, the Write Enable (WREN) instruction must be decoded and executed to set the Write

Enable Latch (WEL) bit in advance. The WRSR instruction can change the value of Block Protect (BP3, BP2,

BP1, BP0) bits to define the protected area of memory (as shown in "Table 2. Protected Area Sizes"). The WRSR

also can set or reset the Quad enable (QE) bit and set or reset the Status Register Write Disable (SRWD) bit in

accordance with Write Protection (WP#/SIO2) pin signal, but has no effect on bit1(WEL) and bit0 (WIP) of the status

register. The WRSR instruction cannot be executed once the Hardware Protected Mode (HPM) is sequence of issuing WRSR instruction is: CS# goes low→ sending WRSR instruction code→ Status Register

data on SI→CS# goes high.

The CS# must go high exactly at the 8 bits, 16 bits or 24 bits data boundary; otherwise, the instruction will be

rejected and not executed. The self-timed Write Status Register cycle time (tW) is initiated as soon as Chip Select

(CS#) goes high. The Write in Progress (WIP) bit still can be checked during the Write Status Register cycle is in

progress. The WIP sets 1 during the tW timing, and sets 0 when Write Status Register Cycle is completed, and the

Write Enable Latch (WEL) bit is reset. Please note that there is another parameter, "Write Status Register cycle time

for Mode Changing Switching (tWMS)", which is only for the self-timed of Mode Switching (changing L/H switch bit).

For more detail please check "Table 17. AC Characteristics".Figure 14. Write Status Register (WRSR) SequenceCS#Mode 3SCLKMode 0commandStatusRegister In7MSB654321ConfigurationRegister -1 In09ConfigurationRegister -2 In8232228293031SI01hSOHigh-ZP/N: PM2159Rev. 1.5, September 22, 2016

Table 7. Protection ModesModeSoftware protectionmode (SPM)Status register conditionStatus register can be writtenin (WEL bit is set to "1") andthe SRWD, BP0-BP3bits can be changedThe SRWD, BP0-BP3 ofstatus register bits cannot bechangedWP# and SRWD bit statusWP#=1 and SRWD bit=0, orWP#=0 and SRWD bit=0, orWP#=1 and SRWD=1Memory The protected area

cannotbe program or protected area

cannotbe program or re protectionmode (HPM)WP#=0, SRWD bit=1Note:

defined by the values in the Block Protect (BP3, BP2, BP1, BP0) bits of the Status Register, as shown in"Table 2. Protected Area Sizes".P/N: PM2159Rev. 1.5, September 22, 2016

Figure 15. WRSR flowstartWREN commandRDSR commandNoWEL=1?YesWRSR commandWrite status register

dataRDSR commandNoWIP=0?YesRDSR commandRead WEL=0, BP[3:0], QE,

and SRWD dataVerify OK?YesWRSR successfullyNoWRSR failP/N: PM2159Rev. 1.5, September 22, 2016