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KK74HCT240A中文资料

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2024年3月28日发(作者:太叔宛儿)

元器件交易网

TECHNICAL DATA

KK74HCT240A

Octal 3-State Inverting Buffer/Line

Driver/Line Receiver

High-Performance Silicon-Gate CMOS

The KK74HCT240A is identical in pinout to the LS/ALS240. The

KK74HCT240A may be used as a level converter for interfacing TTL or

NMOS outputs to High Speed CMOS inputs.

This octal inverting buffer/line driver/line receiver is designed to be

used with 3-state memory address drivers, clock drivers, and other bus-

oriented systems. The device has inverting outputs and two active-low

output enables.

ORDERING INFORMATION

• TTL/NMOS Compatible Input Levels

KK74HCT240AN P lastic

• Outputs Directly Interface to CMOS, NMOS, and TTL

KK74HCT240ADW SOIC

• Operating Voltage Range: 4.5 to 5.5 V

T

A

= -55° to 125° C for all packages

• Low Input Current: 1.0 µA

PIN ASSIGNMENT

LOGIC DIAGRAM

FUNCTION TABLE

Inputs Outputs

PIN 20=V

CC

PIN 10 = GND

Enable A,

Enable B

A,B YA,YB

L L H

L H L

H X Z

X = don’t care

Z = high impedance

1

元器件交易网

KK74HCT240A

MAXIMUM RATINGS

*

Symbol Parameter

V

CC

V

IN

V

OUT

I

IN

I

OUT

I

CC

P

D

Tstg

T

L

*

Value Unit

-0.5 to +7.0

-1.5 to V

CC

+1.5

-0.5 to V

CC

+0.5

±20

±35

±75

750

500

-65 to +150

260

V

V

V

mA

mA

mA

mW

°C

°C

DC Supply Voltage (Referenced to GND)

DC Input Voltage (Referenced to GND)

DC Output Voltage (Referenced to GND)

DC Input Current, per Pin

DC Output Current, per Pin

DC Supply Current, V

CC

and GND Pins

Power Dissipation in Still Air, Plastic DIP+

SOIC Package+

Storage Temperature

Lead Temperature, 1 mm from Case for 10 Seconds

(Plastic DIP or SOIC Package)

Maximum Ratings are those values beyond which damage to the device may occur.

Functional operation should be restricted to the Recommended Operating Conditions.

+Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C

SOIC Package: : - 7 mW/°C from 65° to 125°C

RECOMMENDED OPERATING CONDITIONS

Symbol Parameter Min Max Unit

V

CC

V

IN

, V

OUT

T

A

t

r

, t

f

This device contains protection circuitry to guard against damage due to high static voltages or electric fields.

However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this

high-impedance circuit. For proper operation, V

IN

and V

OUT

should be constrained to the range GND≤(V

IN

or

V

OUT

)≤V

CC

.

Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V

CC

). Unused

outputs must be left open.

DC Supply Voltage (Referenced to GND)

DC Input Voltage, Output Voltage (Referenced to GND)

Operating Temperature, All Package Types

Input Rise and Fall Time (Figure 1)

4.5

0

-55

0

5.5

V

CC

+125

500

V

V

°C

ns

2

2024年3月28日发(作者:太叔宛儿)

元器件交易网

TECHNICAL DATA

KK74HCT240A

Octal 3-State Inverting Buffer/Line

Driver/Line Receiver

High-Performance Silicon-Gate CMOS

The KK74HCT240A is identical in pinout to the LS/ALS240. The

KK74HCT240A may be used as a level converter for interfacing TTL or

NMOS outputs to High Speed CMOS inputs.

This octal inverting buffer/line driver/line receiver is designed to be

used with 3-state memory address drivers, clock drivers, and other bus-

oriented systems. The device has inverting outputs and two active-low

output enables.

ORDERING INFORMATION

• TTL/NMOS Compatible Input Levels

KK74HCT240AN P lastic

• Outputs Directly Interface to CMOS, NMOS, and TTL

KK74HCT240ADW SOIC

• Operating Voltage Range: 4.5 to 5.5 V

T

A

= -55° to 125° C for all packages

• Low Input Current: 1.0 µA

PIN ASSIGNMENT

LOGIC DIAGRAM

FUNCTION TABLE

Inputs Outputs

PIN 20=V

CC

PIN 10 = GND

Enable A,

Enable B

A,B YA,YB

L L H

L H L

H X Z

X = don’t care

Z = high impedance

1

元器件交易网

KK74HCT240A

MAXIMUM RATINGS

*

Symbol Parameter

V

CC

V

IN

V

OUT

I

IN

I

OUT

I

CC

P

D

Tstg

T

L

*

Value Unit

-0.5 to +7.0

-1.5 to V

CC

+1.5

-0.5 to V

CC

+0.5

±20

±35

±75

750

500

-65 to +150

260

V

V

V

mA

mA

mA

mW

°C

°C

DC Supply Voltage (Referenced to GND)

DC Input Voltage (Referenced to GND)

DC Output Voltage (Referenced to GND)

DC Input Current, per Pin

DC Output Current, per Pin

DC Supply Current, V

CC

and GND Pins

Power Dissipation in Still Air, Plastic DIP+

SOIC Package+

Storage Temperature

Lead Temperature, 1 mm from Case for 10 Seconds

(Plastic DIP or SOIC Package)

Maximum Ratings are those values beyond which damage to the device may occur.

Functional operation should be restricted to the Recommended Operating Conditions.

+Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C

SOIC Package: : - 7 mW/°C from 65° to 125°C

RECOMMENDED OPERATING CONDITIONS

Symbol Parameter Min Max Unit

V

CC

V

IN

, V

OUT

T

A

t

r

, t

f

This device contains protection circuitry to guard against damage due to high static voltages or electric fields.

However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this

high-impedance circuit. For proper operation, V

IN

and V

OUT

should be constrained to the range GND≤(V

IN

or

V

OUT

)≤V

CC

.

Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V

CC

). Unused

outputs must be left open.

DC Supply Voltage (Referenced to GND)

DC Input Voltage, Output Voltage (Referenced to GND)

Operating Temperature, All Package Types

Input Rise and Fall Time (Figure 1)

4.5

0

-55

0

5.5

V

CC

+125

500

V

V

°C

ns

2

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