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2024年3月28日发(作者：诺怀山)

元器件交易网

Preliminary

MXED203

160-Channel OLED Row Driver

FEATURES:

For all Passive-Matrix Organic Light Emitting

Diode (OLED) Displays

•Monochome and Color

•

Small Molecule and Polymer

•

Common-Cathode Row Switching

•

CMOS High Voltage Process: 5V-30V

Display Panel Supply Compatible

•160 Output Channels, Cascadable;

Configurable 144-Output Mode

•150mA Maximum Current Capability per

Channel (two channels maximum active

simultaneously)

•20 Ohm Maximum Row Switch “On”

Resistance

•Token-Based Control; Bidirectional data

transfer; Single- and Dual-Token Modes

•3V to 5.5V logic supply

•Up to 100 kHz Clock Frequency

•Gold-Bumped Die @ 60 micron Output

Pitch

•TCP Package Option

•Compatible with Clare Micronix 100 Series

OLED Column Drivers

•

OVERVIEW:

Clare Micronix’s MXED203 is a row-multiplexed

display driver for OLED panel displays. The

MXED203 directly supports up to 160-row OLED

panel displays, or can be cascaded for controlling

additional rows. The MXED203’s low “on” switch

resistance ensures uniform luminance at rapid row

scan rates. The MXED203 is the second genera-

tion device in Clare’s family of row drivers for OLED

displays.

FUNCTIONAL DESCRIPTION

The MXED203 is capable of sinking current for up to 160 rows (LED cathodes) of an OLED display.

One or two outputs may be active at a time. For displays requiring more than 150mA sink current per

row, multiple MXED203’s may be placed in parallel.

Device settings, such as token direction, number of active rows, dual or single-token mode, and others,

are set by dedicated input pins.

Figure 1 is a block diagram of the MXED203. Each row output has two possible sources: ground, to

turn the LED on, and VOH (Voltage Output High) to turn the LED off. To begin a scan of the rows, the

user inputs a token bit so that it is high at the rising edge of CLK, which is typically provided by the

MXED102 or similar column driver or controller. In “normal mode” (single token), the token may be

entered at either end of the MXED203 row shift register (SRIN or SLIN), depending on the shift direc-

tion selection control “Shift Right” (SHR). The token bit is shifted one row (one channel) per clock cycle

(CLK), during which time only one row maximum is active at a time. In “dual mode” (DUAL), the token

bit is entered at one end and automatically in the center, and again the token bits may be selectively

shifted left or right at the CLK rate; during which time only two rows maximum are active at a time. The

MXED203 may be used for either 160- or 144-row display panels. When the “Select 160” (S160)

15780A

August 20, 2002

元器件交易网

Preliminary

FUNCTIONAL DESCRIPTION - continued

MXED203

control input is low, the MXED203 is set for 144 outputs. When S160 is low, Rows 8 through 151 must

be used. (Note: A lesser number of rows may be used by resetting the MXED202 (RSTB) at any time,

truncating the shift cycle.) Please refer to the table of Token Shift Options.

The MXED203 fully supports column precharge of OLED display panels. During column precharge the

active row output will be high (VOH) from the time CLK occurs until PCB (typically provided by the

column driver) goes high. When PCB goes high, indicating that precharge is completed, the active row

output will go low, allowing the diode to turn on. All inactive row outputs will remain high.

The “off” output voltage, VOH, is connected to the output of an internal op-amp. This op-amp may be

used to generate VOH, or it may be bypassed. If it is bypassed, VOH is tied directly to VMAX, as are

inputs VDRV and INV. If the op-amp is to be used to generate VOH, VDRV is used as the non-inverting

op-amp input, and INV is used as the inverting op-amp input. External resistors are used to set the

gain, and thus VOH. Figure 4 shows the circuit options for generating VOH.

FIGURE 1 - MXED203 BLOCK DIAGRAM

VMAX

DRV

INV

VOH

GND

VCC

RSTB

CLK

PCB

Ropt

S160

DUAL

Timing

Generator

S160

SHR

72/80 Bit Shift Register

SHR

Row Output

Level

Shift

GND

159

VOH

ROW 80

(Only 1 Row

Output is shown)

159

SLIN

SRIN

72/80 Bit Shift Register

VOH

SHR

Row Output

Level

ROW 0