2024年5月11日发(作者：衅沈然)

元器件交易网

µPSD3200FAMILY

FlashProgrammableSystemDevice

with8032MicrocontrollerCore

DATABRIEFING

FEATURESSUMMARY

s

TheµPSD3200FamilycombinesaFlashPSD

architecturewithan8032microcontrollercore

TheµPSD3200FamilyofFlashPSDsfeatures

dualbanksofFlashmemory,SRAM,general

purposeI/Oandprogrammablelogic,supervi-

soryfunctionsandaccessviaUSB,I

2

C,ADC,

DDCandPWMchannels,andanon-board

8032microcontrollercore,withtwoUARTs,

three16-bitTimer/CountersandoneExternal

otherFlashPSDfamilies,the

µPSD3200Familyisalsoin-systemprogram-

mable(ISP)viaaJTAGISPinterface.

Large8KByteSRAMwithbatteryback-up

option

DualbankFlashmemories

–128KByteor256KBytemainFlashmemory

–32KBytesecondaryFlashmemory

s

es

s

s

TQFP52(T)

ContentSecurity

–BlockaccesstoFlashmemory

ProgrammableDecodePLDforflexibleaddress

mappingofallmemories.

High-speedclockstandard8032core(12-cycle)

USBInterface(µPSD3234A-40U6only)

I

2

Cinterfaceforperipheralconnections

FivePulseWidthModulator(PWM)channels

StandaloneDisplayDataChannel(DDC)

SixI/Oportswithupto50I/Opins

3000gatePLDwith16macrocells

Supervisorfunctions

In-SystemProgramming(ISP)viaJTAG

Zero-PowerTechnology

SingleSupplyVoltage

–4.5to5.5V

–3.0to3.6V

TQFP80(U)

s

s

s

s

s

s

s

s

s

s

s

s

June2002

Completedataavailableon

Data-on-DiscCD-ROM

orat

.

1/8

元器件交易网

µPSD3200FAMILY

SUMMARYDESCRIPTION

s

DualbankFlashmemories

–Concurrentoperation,readfrommemoryone

-Appli-

cationProgramming(IAP)forremoteupdates

–Large128KByteor256KBytemainFlash

memoryforapplicationcode,operatingsys-

tems,orbitmapsforgraphicuserinterfaces

–Large32KBytesecondaryFlashmemorydi-

ateexternalEE-

PROMwithsoftwareEEPROMemulation

–SecondaryFlashmemoryislargeenoughfor

sophisticatedcommunicationprotocol(USB)

duringIAPwhilecontinuingcriticalsystem

tasks

s

s

s

–One16-bitPWMunit

StandaloneDisplayDataChannel(DDC)

–Foruseinmonitor,projector,andTVapplica-

tions

–CompliantwithVESAstandardsDDC1and

DDC2B

–EliminateexternalDDCPROM

SixI/Oportswithupto50I/Opins

–MultifunctionI/O:GPIO,DDC,I

2

C,PWM,

PLDI/O,supervisor,andJTAG

–Eliminatesneedforexternallatchesandlogic

s

3000gatePLDwith16macrocells

–Creategluelogic,statemachines,delays,

etc.

–EliminateexternalPALs,PLDs,and74HCxx

–Free

LargeSRAMwithbatteryback-upoption

–8KByteSRAMforRTOS,high-levellanguag-

es,communicationbuffers,andstacks

s

ProgrammableDecodePLDforflexibleaddress

mappingofallmemories

–PlaceindividualFlashandSRAMsectorson

anyaddressboundary

–Built-inpageregisterbreaksrestrictive8032

limitof64KByteaddressspace

–SpecialregisterswapsFlashmemoryseg-

mentsbetween8032“program”spaceand

“data”spaceforefficientIn-ApplicationPro-

gramming

s

Supervisorfunctions

–Generatesresetuponlowvoltageorwatch-

ateexternalsupervisor

device

–ResetInpin

s

In-SystemProgramming(ISP)viaJTAG

–Programentirechipin10-25secondswith

noinvolvementof8032

–Allowsefficientmanufacturing,easyproduct

testing,andJust-In-Timeinventory

–Eliminatesocketsandpre-programmedparts

–ProgramwithFlashLINK

TM

cableandanyPC

s

High-speedclockstandard8032core(12-cycle)

–40MHzoperationat5V,24MHzat3.3V

–TwoUARTswithindependentbaudrate,

three16-bitTimer/CountersandtwoExternal

Interrupts

s

ContentSecurity

–ProgrammableSecurityBitblocksaccessof

deviceprogrammersandreaders

s

USBInterface(µPSD3234A-40U6only)

–SupportsUSB1.1SlowMode(1.5Mbit/s)

–Controlendpoint0andinterruptendpoints1

and2

s

Zero-PowerTechnology

–MemoriesandPLDautomaticallyreach

standbycurrentbetweeninputchanges

s

I

2

Cinterfaceforperipheralconnections

–Capableofmasterorslaveoperation

FivePulseWidthModulator(PWM)channels

–Four8-bitPWMunits

s

Packages

–52-pinTQFP

–80-pinTQFP:allowsaccessto8032address/

data/controlsignalsforconnectingtoexternal

peripherals

s

2/8

2024年5月11日发(作者：衅沈然)

元器件交易网

µPSD3200FAMILY

FlashProgrammableSystemDevice

with8032MicrocontrollerCore

DATABRIEFING

FEATURESSUMMARY

s

TheµPSD3200FamilycombinesaFlashPSD

architecturewithan8032microcontrollercore

TheµPSD3200FamilyofFlashPSDsfeatures

dualbanksofFlashmemory,SRAM,general

purposeI/Oandprogrammablelogic,supervi-

soryfunctionsandaccessviaUSB,I

2

C,ADC,

DDCandPWMchannels,andanon-board

8032microcontrollercore,withtwoUARTs,

three16-bitTimer/CountersandoneExternal

otherFlashPSDfamilies,the

µPSD3200Familyisalsoin-systemprogram-

mable(ISP)viaaJTAGISPinterface.

Large8KByteSRAMwithbatteryback-up

option

DualbankFlashmemories

–128KByteor256KBytemainFlashmemory

–32KBytesecondaryFlashmemory

s

es

s

s

TQFP52(T)

ContentSecurity

–BlockaccesstoFlashmemory

ProgrammableDecodePLDforflexibleaddress

mappingofallmemories.

High-speedclockstandard8032core(12-cycle)

USBInterface(µPSD3234A-40U6only)

I

2

Cinterfaceforperipheralconnections

FivePulseWidthModulator(PWM)channels

StandaloneDisplayDataChannel(DDC)

SixI/Oportswithupto50I/Opins

3000gatePLDwith16macrocells

Supervisorfunctions

In-SystemProgramming(ISP)viaJTAG

Zero-PowerTechnology

SingleSupplyVoltage

–4.5to5.5V

–3.0to3.6V

TQFP80(U)

s

s

s

s

s

s

s

s

s

s

s

s

June2002

Completedataavailableon

Data-on-DiscCD-ROM

orat

.

1/8

元器件交易网

µPSD3200FAMILY

SUMMARYDESCRIPTION

s

DualbankFlashmemories

–Concurrentoperation,readfrommemoryone

-Appli-

cationProgramming(IAP)forremoteupdates

–Large128KByteor256KBytemainFlash

memoryforapplicationcode,operatingsys-

tems,orbitmapsforgraphicuserinterfaces

–Large32KBytesecondaryFlashmemorydi-

ateexternalEE-

PROMwithsoftwareEEPROMemulation

–SecondaryFlashmemoryislargeenoughfor

sophisticatedcommunicationprotocol(USB)

duringIAPwhilecontinuingcriticalsystem

tasks

s

s

s

–One16-bitPWMunit

StandaloneDisplayDataChannel(DDC)

–Foruseinmonitor,projector,andTVapplica-

tions

–CompliantwithVESAstandardsDDC1and

DDC2B

–EliminateexternalDDCPROM

SixI/Oportswithupto50I/Opins

–MultifunctionI/O:GPIO,DDC,I

2

C,PWM,

PLDI/O,supervisor,andJTAG

–Eliminatesneedforexternallatchesandlogic

s

3000gatePLDwith16macrocells

–Creategluelogic,statemachines,delays,

etc.

–EliminateexternalPALs,PLDs,and74HCxx

–Free

LargeSRAMwithbatteryback-upoption

–8KByteSRAMforRTOS,high-levellanguag-

es,communicationbuffers,andstacks

s

ProgrammableDecodePLDforflexibleaddress

mappingofallmemories

–PlaceindividualFlashandSRAMsectorson

anyaddressboundary

–Built-inpageregisterbreaksrestrictive8032

limitof64KByteaddressspace

–SpecialregisterswapsFlashmemoryseg-

mentsbetween8032“program”spaceand

“data”spaceforefficientIn-ApplicationPro-

gramming

s

Supervisorfunctions

–Generatesresetuponlowvoltageorwatch-

ateexternalsupervisor

device

–ResetInpin

s

In-SystemProgramming(ISP)viaJTAG

–Programentirechipin10-25secondswith

noinvolvementof8032

–Allowsefficientmanufacturing,easyproduct

testing,andJust-In-Timeinventory

–Eliminatesocketsandpre-programmedparts

–ProgramwithFlashLINK

TM

cableandanyPC

s

High-speedclockstandard8032core(12-cycle)

–40MHzoperationat5V,24MHzat3.3V

–TwoUARTswithindependentbaudrate,

three16-bitTimer/CountersandtwoExternal

Interrupts

s

ContentSecurity

–ProgrammableSecurityBitblocksaccessof

deviceprogrammersandreaders

s

USBInterface(µPSD3234A-40U6only)

–SupportsUSB1.1SlowMode(1.5Mbit/s)

–Controlendpoint0andinterruptendpoints1

and2

s

Zero-PowerTechnology

–MemoriesandPLDautomaticallyreach

standbycurrentbetweeninputchanges

s

I

2

Cinterfaceforperipheralconnections

–Capableofmasterorslaveoperation

FivePulseWidthModulator(PWM)channels

–Four8-bitPWMunits

s

Packages

–52-pinTQFP

–80-pinTQFP:allowsaccessto8032address/

data/controlsignalsforconnectingtoexternal

peripherals

s

2/8