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2024年9月6日发(作者：薛颐和)

元器件交易网

19-1494; Rev 0; 7/99

Protected RS-232 T

SPI/MICROWIRE-Compatible UART and ±15kV ESD-

ransceivers with Internal Capacitors

General DescriptionFeatures

The MAX3110E/MAX3111E combine a full-featured uni-

versal asynchronous receiver/transmitter (UART) with

oIntegrated RS-232 Transceiver and UART in a

±15kV ESD-protected RS-232 transceivers and inte-

Single 28-Pin Package

grated charge-pump capacitors into a single 28-pin

oSPI/QSPI/MICROWIRE-Compatible µC Interface

package for use in space-, cost-, and power-con-

oInternal Charge-Pump Capacitors—

strained applications. The MAX3110E/MAX3111E also

feature an SPI™/QSPI™/MICROWIRE™-compatible

No External Components Required!

serial interface to save additional board space and

oTrue RS-232 Operation Down to V

= +3V

microcontroller (µC) I/O pins.

(MAX3111E)

A proprietary low-dropout output stage enables the

oESD Protection for RS-232 I/O Pins

2-driver/2-receiver interface to deliver true RS-232 per-

±15kV—Human Body Model

formance down to V

= +3V (+4.5V for MAX3110E)

±8kV—IEC 1000-4-2, Contact Discharge

while consuming only 600µA. The receivers remain

±15kV—IEC 1000-4-2, Air-Gap Discharge

active in a hardware/software-invoked shutdown, allow-

oSingle-Supply Operation

ing external devices to be monitored while consuming

+5V (MAX3110E)

only 10µA. Each device is guaranteed to operate at up

to 230kbps while maintaining true EIA/TIA-232 output

+3.3V (MAX3111E)

voltage levels.

oLow Power

The MAX3110E/MAX3111E’s UART includes a crystal

600µA Supply Current

oscillator and baud-rate generator with software-pro-

10µA Shutdown Supply Current with

grammable divider ratios for all common baud rates

Receiver Interrupt Active

from 300baud to 230kbaud. The UART features an 8-

oGuaranteed 230kbps Data Rate

word-deep receive FIFO that minimizes processor over-

oHardware/Software-Compatible with MAX3100

head and provides a flexible interrupt with four

and MAX3222E

maskable sources. Two control lines (one input and

one output) are included for hardware handshaking.

Ordering Information

The UART and RS-232 functions can be used together

or independently since the two functions share only

PART

TEMP. PIN-V

RANGEPACKAGE(V)

supply and ground connections (the MAX3110E/

MAX3111E are hardware- and software-compatible

MAX3110ECWI

0°C to +70°C28 Wide SO5

with the MAX3100 and MAX3222E).

MAX3110ECNI0°C to +70°C28 Plastic DIP5

________________________Applications

Ordering Information continued at end of data sheet.

Point-of-Sale (POS) Devices

Typical Application Circuit

Handy-Terminals

Telecom/Networking Diagnostic Ports

MAX3110E

MAX3111E

Industrial Front-Panel Interfaces

SPI

RS-232

DB-9

Hand-Held/Battery-Powered Equipment

SCLK

12345

µP

DIN

Pin Configuration appears at end of data sheet.

DOUT

6789

†

4,777,577; 4,797,899; 4,809,152; 4,897,774; 4,999,761; and

Covered by U.S. Patent numbers 4,636,930; 4,679,134;

IRQ

other patents pending.

SPI and QSPI are trademarks of Motorola, Inc.

MICROWIREis a trademark of National Semiconductor Corp.

________________________________________________________________

Maxim Integrated Products

For free samples & the latest literature: , or phone 1-800-998-8800.

For small orders, phone 1-800-835-8769.

MAX3110E/MAX3111E

†

元器件交易网

SPI/MICROWIRE-Compatible UART and ±15kV ESD-

Protected RS-232 Transceivers with Internal Capacitors

ABSOLUTE MAXIMUM RATINGS

to GND (MAX3110E)........................................-0.3V to +6V

to GND (MAX3111E).........................................-0.3V to +4V

V+ to GND (Note 1)..................................................-0.3V to +7V

V- to GND (Note 1)...................................................+0.3V to -7V

V+ to V- (Note 1)..................................................................+13V

Input Voltages to GND

CS, X1, CTS, RX, DIN, -0.3V to (V

+ 0.3V)

T_IN, -0.3V to +6V

±25V

Output Voltage to GND

DOUT, RTS, TX, X2 .................................-0.3V to (V

+ 0.3V)

-0.3V to +6V

T_OUT ...........................................................................±13.2V

-0.3V to (V

+ 0.3V)

TX, 100mA

Short-Circuit Duration

X2, DOUT, IRQ(to V

or GND).............................Continuous

T_OUT (to GND) .....................................................Continuous

Continuous Power Dissipation (T

= +70°C)

28-pin Wide SO (derate 12.5mW/°C above +70°C) ...........1W

28-pin Plastic DIP (derate 14.3mW/°C above +70°C)....1.14W

Operating Temperature Ranges

MAX311_EC_ _ ..................................................0°C to +70°C

MAX311_EE_ _ ................................................-40°C to +85°C

Storage Temperature Range ............................-65°C to +150°C

Lead Temperature (soldering, 10sec).............................+300°C

Note 1:V+ and V- can have maximum magnitudes of 7V, but their absolute difference should not exceed 13V.

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and function-

al operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure

to absolute maximum rating conditions for extended periods may affect device reliability.

ELECTRICAL CHARACTERISTICS—MAX3110E

= +4.5V to +5.5V, T

= T

MIN

to T

MAX

, unless otherwise noted. Typical values are measured for baud rate set to 9600baud at

= +5V, T

= +25°C.) (Note 2)

PARAMETER

Supply Current

Supply Current with Hardware

Shutdown

Supply Current with Hardware

and Software Shutdown

UARTOSCILLATOR INPUT (X1)

Input High Voltage

Input Low Voltage

Input Current

Input Capacitance

Input High Voltage

Input Low Voltage

Input Hysteresis

Input Leakage Current

Input Capacitance

)

RS-232 LOGICINPUTS(T_IN, SHDN)

Input High Voltage

Input Low Voltage

Transmitter Input Hysteresis

Input Leakage Current

IH3

IL3

HYST3

IN3

500

±0.01±1

= 5V2.4

0.8V

µA

IH1

IL1

IN1

IH2

IL2

HYST2

LKG1

IN2

250

±1

0.7V

0.3V

= 0 or 5.5V

SHDNi bit = 0

SHDNi bit = 1

0.7V

0.2V

SYMBOL

CCSHDN(H)

CCSHDN(H+ S)

CONDITIONS

SHDN= V

, no load

SHDN= GND (Note 3)

SHDN= GND, SHDNi bit = 1 (Note 4)

MINTYP

0.6

0.48

MAX

UNITS

µA

DC CHARACTERISTICS (V

= +5V, T

= +25°C)

UARTLOGICINPUTS(DIN, SCLK, CS,CTS, RX

)

_______________________________________________________________________________________

元器件交易网

SPI/MICROWIRE-Compatible UART and ±15kV ESD-

Protected RS-232 Transceivers with Internal Capacitors

ELECTRICAL CHARACTERISTICS—MAX3110E (continued)

= +4.5V to +5.5V, T

= T

MIN

to T

MAX

, unless otherwise noted. Typical values are measured for baud rate set to 9600baud at

= +5V, T

= +25°C.) (Note 2)

PARAMETER

RS-232 RECEIVER INPUTS (R_IN)

Input Voltage Range

Input High Voltage

Input Low Voltage

Input Hysteresis

Input Resistance

IH4

IL4

HYST4

= +25°C

Human Body Model

ESD Protection

RS-232 RECEIVER OUTPUTS (R_OUT)

Output High Voltage

Output Low Voltage

OH1

OL1

SOURCE

= 1mAReceivers disabled

SINK

= 1.6mA

- 0.6±0.05±10

0.4

µAV

IEC 1000-4-2 Air Discharge

IEC 1000-4-2 Contact Discharge

= +25°C, V

= 5V

= +25°C, V

= 5V

500

±15

±8

-25

2.4

0.8

+25V

kΩ

SYMBOLCONDITIONSMINTYPMAXUNITS

MAX3110E/MAX3111E

RS-232 ESDPROTECTION (R_IN, T_OUT)

RS-232 TRANSMITTER OUTPUTS (T_OUT)

Output Voltage Swing3kΩload on all transmitter outputs5±5.4V

Output ResistanceR

= V+ = V- = 0, V

OUT

= ±2V30010MΩ

Output Short-Circuit Current±60mA

Output Leakage CurrentI

LKG2

= 0 or 5.5V, V

OUT

= ±12V,

transmitters disabled

±25

µA

UARTOUTPUTS (DOUT, TX, RTS)

Output Leakage CurrentI

LKG3

DOUT only, CS= V

±1µA

Output High VoltageV

OH2

SOURCE

= 5mA; DOUT, RTS

- 0.5

SOURCE

= 10mA; TX onlyV

- 0.5

Output Low VoltageV

OL2

SINK

= 4mA; DOUT, RTS

0.4

SINK

= 25mA; TX only0.9

Output CapacitanceC

OUT1

5pF

UARTIRQOUTPUTS (IRQ= open drain)

Output Leakage CurrentI

LKG4

IRQ

= 5.5V±1µA

Output Low VoltageV

OL3

SINK

= 4mA0.4V

Output CapacitanceC

OUT2

5pF

UARTACTIMING

CSLow to DOUT Valid

LOAD

= 100pF100ns

CSHigh to DOUT Tri-State

LOAD

= 100pF, R

= 10kΩ100ns

CSto SCLK Setup Time

CSS

100ns

CSto SCLK Hold Time

CSH

0ns

SCLK Fall to DOUT Validt

LOAD

= 100pF100ns

_______________________________________________________________________________________3

元器件交易网

SPI/MICROWIRE-Compatible UART and ±15kV ESD-

Protected RS-232 Transceivers with Internal Capacitors

ELECTRICAL CHARACTERISTICS—MAX3110E (continued)

= +4.5V to +5.5V, T

= T

MIN

to T

MAX

, unless otherwise noted. Typical values are measured for baud rate set to 9600baud at

= +5V, T

= +25°C.) (Note 2)

PARAMETER

DIN to SCLK Setup Time

DIN to SCLK Hold Time

SCLK Period

SCLK High Time

SCLK Low Time

SCLK Rising Edge to CSFalling

CSRising Edge to SCLK Rising

Edge

CS High Pulse Width

Output Rise Time

Output Fall Time

RS-232 ACTIMING

Maximum Data Rate

Receiver Propagation Delay

Transmitter Skew

Receiver Skew

PHL

PLH

PHL

- t

PLH

PHL

- t

PLH

= 5V,

= 3kΩto 7kΩ,

= +25°C,

measured from

+3V to -3V or

-3V to +3V

= 150pF to

1000pF

= 150pF to

2500pF

= 3kΩ, C

= 1000pF,

one transmitter switching

Receiver input to receiver output

= 150pF

(Note 5)

250

150

100

V/µs

430

kbps

SYMBOL

CS0

CS1

CSW

TX, RTS, DOUT; C

= 100pF

TX, RTS, DOUT, IRQ; C

= 100pF

CONDITIONSMIN

100

238

100

200

TYPMAXUNITS

Transition-Region Slew Rate

4_______________________________________________________________________________________

元器件交易网

SPI/MICROWIRE-Compatible UART and ±15kV ESD-

Protected RS-232 Transceivers with Internal Capacitors

ELECTRICAL CHARACTERISTICS—MAX3111E

= +3.0V to +3.6V, V

= T

MIN

to T

MAX

, unless otherwise noted. Typical values are measured for baud rate set to 9600baud at

= +3.3V, T

= +25°C.) (Note 2)

PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS

DC CHARACTERISTICS (V

= 3.3V, T

= +25°C)

Supply CurrentI

SHDN= V

, no load

0.451.4mA

Supply Current with Hardware

Shutdown

CCSHDN(H)

SHDN= GND (Note 3)

0.180.4mA

Supply Current with Hardware

and Software Shutdown

CCSHDN(H+ S)

SHDN= GND SHDNi bit = 1 (Note 4)

120µA

UARTOSCILLATOR INPUT (X1)

Input High VoltageV

IH1

0.7V

Input Low VoltageV

IL1

0.2V

Input CurrentI

SHDNi bit = 025

IN1

= 0 or 3.6V

SHDNi bit = 12

µA

Input CapacitanceC

IN1

5pF

UART LOGICINPUTS(DIN, SCLK, CS, RX

)

Input High VoltageV

IH2

0.7V

Input Low VoltageV

IL2

0.3V

Input HysteresisV

HYST2

165mV

Input Leakage CurrentI

LKG1

±1µA

Input CapacitanceC

IN2

RS-232 LOGICINPUTS(T_IN, SHDN)

Input High VoltageV

IH3

= 3.3V2.0V

Input Low VoltageV

IL3

0.8V

Transmitter Input HysteresisV

HYST3

500mV

Input Leakage CurrentI

IN3

±0.01±1µA

RS-232 RECEIVER INPUTS (R_IN)

Input Voltage Range-25+25V

Input High VoltageV

IH4

= +25°C, V

= 3.3V2.4V

Input Low VoltageV

IL4

= +25°C, V

= 3.3V0.6V

Input HysteresisV

HYST4

500mV

Input ResistanceR

= +25°C357kΩ

RS-232 ESDPROTECTION (R_IN, T_OUT)

Human Body Model±15

ESD Protection

IEC 1000-4-2 Air Discharge±15

IEC 1000-4-2 Contact Discharge±8

_______________________________________________________________________________________5

MAX3110E/MAX3111E

元器件交易网

SPI/MICROWIRE-Compatible UART and ±15kV ESD-

Protected RS-232 Transceivers with Internal Capacitors

ELECTRICAL CHARACTERISTICS—MAX3111E (continued)

= +3.0V to +3.6V, V

= T

MIN

to T

MAX

, unless otherwise noted. Typical values are measured for baud rate set to 9600baud at

= +3.3V, T

= +25°C.) (Note 2)

PARAMETER

Output High Voltage

Output Low Voltage

Output Voltage Swing

Output Resistance

Output Short-Circuit Current

Output Leakage Current

UARTOUTPUTS (DOUT, TX, RTS)

Output Leakage Current

Output High Voltage

Output Low Voltage

Output Capacitance

Output Leakage Current

Output Low Voltage

Output Capacitance

UARTACTIMING

CSLow to DOUT Valid

CSHigh to DOUT Tri-State

CSto SCLK Setup Time

CSto SCLK Hold Time

SCLK Fall to DOUT Valid

DIN to SCLK Setup Time

DIN to SCLK Hold Time

SCLK Period

SCLK High Time

SCLK Low Time

SCLK Rising Edge to CSFalling

CSRising Edge to SCLK Rising

Edge

CSHigh Pulse Width

Output Rise Time

Output Fall Time

CSS

CSH

CS0

CS1

CSW

TX, RTS, DOUT; C

LOAD

= 100pF

TX, RTS, DOUT, IRQ; C

LOAD

= 100pF

LOAD

= 100pF

100

238

100

200

LOAD

= 100pF

LOAD

= 100pF, R

= 10kΩ

100

LKG3

OH2

OL2

OUT1

LKG4

OL3

OUT2

IRQ

= 3.6V

SINK

= 4mA

DOUT only; CS= V

SOURCE

= 5mA; DOUT, RTS

SOURCE

= 10mA, TX only

SINK

= 4mA; DOUT, RTS

SINK

= 25mA, TX only

±1

0.4

- 0.5

0.4

0.9

±1µA

µA

LKG2

= 0 or 3.6V, V

OUT

= ±12V,

transmitters disabled

SYMBOL

OH1

OL1

CONDITION

SOURCE

= 1mA

SINK

= 1.6mA

3kΩload on all transmitter outputs

= V+ = V- = 0, V

OUT

= ±2V

±5

300

±5.4

10M

±60

±25

MIN

- 0.6

0.4

TYPMAXUNITS

Ω

µA

RS-232 RECEIVER OUTPUTS (R_OUT)

RS-232 TRANSMITTER OUTPUTS (T_OUT)

UARTIRQ OUTPUT (IRQ= open drain)

6_______________________________________________________________________________________

元器件交易网

SPI/MICROWIRE-Compatible UART and ±15kV ESD-

Protected RS-232 Transceivers with Internal Capacitors

ELECTRICAL CHARACTERISTICS—MAX3111E (continued)

= +3.0V to +3.6V, V

= T

MIN

to T

MAX

, unless otherwise noted. Typical values are measured for baud rate set to 9600baud at

= +3.3V, T

= +25°C.) (Note 2)

PARAMETER

RS-232 ACTIMING

Maximum Data Rate

Receiver Propagation Delay

Transmitter Skew

Receiver Skew

PHL

PLH

PHL

- t

PLH

PHL

- t

PLH

= 3.3V,

= 3kΩto 7kΩ,

= +25°C,

measured from

+3V to -3V or

-3V to +3V

= 150pF to

1000pF

= 150pF to

2500pF

= 3kΩ, C

= 1000pF,

one-transmitter switching

Receiver input to receiver output

= 150pF

(Note 5)

250

150

200

100

V/µs

430

kbps

SYMBOLCONDITIONSMINTYPMAXUNITS

MAX3110E/MAX3111E

Transition-Region Slew Rate

Note 2:All currents into the device are positive; all currents out of the device are negative. All voltages are referred to device

ground unless otherwise noted.

Note 3:I

CCSHDN(H)

represents a hardware-only shutdown. In hardware shutdown, the UART is in normal operation and the charge

pumps for the RS-232 transmitters are shut down.

Note 4:I

CCSHDN(H+S)

represents a simultaneous software and hardware shutdown in which the UART and charge pumps are

shut down.

Note 5:Transmitter skew is measured at the transmitter zero cross points.

_______________________________________________________________________________________7

元器件交易网

SPI/MICROWIRE-Compatible UART and ±15kV ESD-

Protected RS-232 Transceivers with Internal Capacitors

Typical Operating Characteristics

= +25°C, unless otherwise noted.)

UART SUPPLY CURRENT vs. TEMPERATURE

UART SHUTDOWN CURRENT

vs. TEMPERATURE

1.8432MHz CRYSTAL

UART SUPPLY CURRENT

vs. BAUD RATE

1.8432MHz

CRYSTAL

+5V

TRANSMITTING

1000

900

800

(

)

700

600

500

400

300

200

100

-40

1.8432MHz CRYSTAL

TRANSMITTING AT 115.2kbps

(

)

400

350

(

)

300

250

200

150

100

MAX3110E

+3V

TRANSMITTING

MAX3111E

+5V

STANDBY

MAX3111E, V

= +3.3V

MAX3110E, V

= +5V

MAX3110E, V

= +5V

MAX3111E, V

= +3.3V

+3V

STANDBY

100k1M

-20

-40-20

TEMPERATURE (°C)

100

1000

10k

BAUD RATE (bps)

TEMPERATURE (°C)

UART SUPPLY CURRENT vs.

EXTERNAL CLOCK FREQUENCY

MAX3110E

TX, RTS, DOUT OUTPUT CURRENT

vs. OUTPUT LOW VOLTAGE (V

= +5V)

MAX3111E

TX, RTS, DOUT OUTPUT CURRENT

vs. OUTPUT LOW VOLTAGE (V

= +3.3V)

(

)

DOUT

RTS

700

600

(

)

500

400

300

200

100

0123

EXTERNAL CLOCK FREQUENCY (MHz)

MAX3111E

= +3.3V

MAX3110E

= +5V

(

)

DOUT

RTS

00.10.20.30.40.50.60.7

0.8

0.91.0

VOLTAGE (V)

00.10.20.30.40.50.60.7

0.8

0.91.0

VOLTAGE (V)

RS-232 TRANSMITTER OUTPUT VOLTAGE

vs. LOAD CAPACITANCE

RS-232 TRANSCEIVER SUPPLY CURRENT

vs. LOAD CAPACITANCE

RS-232 TRANSMITTER SLEW RATE

vs. LOAD CAPACITANCE

(

)

+SLEW

-SLEW

TRANSMITTER 1 AT 250kbps

3kΩ + C

10.0

(

)

7.5

5.0

2.5

-2.5

-5.0

-7.5

-10.0

TRANSMITTER 1 AT 250kbps

TRANSMITTER 2 AT 15.6kbps

3kΩ + C

OUT+

(

)

TRANSMITTER 1 AT DATA RATE

TRANSMITTER 2 AT DATA RATE

3kΩ + C

250kbps

120kbps

OUT-

10005000

20kbps

40005000

040005000

LOAD CAPACITANCE (pF)

8_______________________________________________________________________________________

元器件交易网

Protected RS-232 T

SPI/MICROWIRE-Compatible UART and ±15kV ESD-

ransceivers with Internal Capacitors

Pin Description

PINNAMEFUNCTION

1R2INRS-232 Receiver Input 2

2R2OUTRS-232 Receiver Output 2, TTL/CMOS

3T2INRS-232 Transmitter lnput 2, TTL/CMOS

4T1INRS-232 Transmitter lnput 1, TTL/CMOS

5R1OUTRS-232 Receiver Output 1, TTL/CMOS

6R1INRS-232 Receiver Input 1

7T1OUTRS-232 Transmitter Output 1

Positive Supply Voltage

9X2

UART Crystal Connection. Leave X2 unconnected when using an external CMOS clock. See the

Crystals,

Oscillators, and Ceramic Resonators

section.

10X1

UART Crystal Connection. X1 also serves as an external CMOS clock input. See the

Crystals, Oscillators,

and Ceramic Resonators

section.

CTS

UART Clear-to-Send Active-Low Input. Read via the CTS bit.

RTS

UART Request-to-Send Active-Low Output. Controlled by the RTS bit. Also used to control the driver enable

in RS-485 networks.

13RX

UART Asynchronous Serial-Data (receiver) Input. The serial information received from the RS-232 receiver.

A transition on RX while in shutdown generates an interrupt (Table 1).

14TXUART Asynchronous Serial-Data (transmitter) Output

15DINSPI/MICROWIRESerial-Data Input. Schmitt-trigger Input.

16DOUT

SPI/MICROWIRESerial-Data Output. High impedance when CSis high.

17SCLKSPI/MICROWIRESerial-Clock Input. Schmitt-trigger input.

UART Active-Low Chip-Select Input. DOUT goes high impedance when CSis high. IRQ, TX, and RTSare

always active. Schmitt-trigger input.

IRQ

UART Active-Low Interrupt Output. Open-drain interrupt output to microprocessor.

SHDN

Hardware Shutdown Input. Drive SHDN low to shut down the RS-232 transmitters and charge pump. Drive

high for normal operation.

21V+

+5.5V generated by the internal charge pump. Do not make any connection to this terminal.

22C1+

Positive terminal of the internal voltage-doubler charge-pump capacitor. Do not make any connection to

this terminal.

23C1-

Negative terminal of the internal voltage-doubler charge-pump capacitor. Do not make any connection to

this terminal.

24C2+

Positive terminal of internal inverting charge-pump capacitor. Do not make any connection to this terminal.

25C2-

Negative terminal of internal inverting charge-pump capacitor. Do not make any connection to this terminal.

26V-

-5.5V generated by the internal charge pump. Do not make any connection to this terminal.

27GNDGround

28T2OUTRS-232 Transmitter Output 2

_______________________________________________________________________________________9

MAX3110E/MAX3111E

元器件交易网

SPI/MICROWIRE-Compatible UART and ±15kV ESD-

Protected RS-232 Transceivers with Internal Capacitors

T2IN

T2OUT

T1IN

T1OUT

R2OUT

R2IN

R1OUT

C1+

INTERNAL

C1-

C2+

INTERNAL

C2-

PrRX BUFFER

CHARGE

PUMP

INTERNAL

R1IN

V+

GND

V-

SHDN

MAX3110E/MAX3111E

RX FIFO

INTERRUPT

LOGIC

IRQ

RX SHIFT REGISTER

BAUD-RATE

GENERATOR

DOUT

SPI

INTERFACE

SCLK

TX SHIFT REGISTER

TX BUFFER

I/O

CTS

RTS

DIN

Figure 1. MAX3110E/MAX3111E Functional Diagram

Detailed Description

The MAX3110E/MAX3111E contain an SPI/QSPI/MICROWIRE-

compatible UART and an RS-232 transceiver with two

drivers and two receivers. The UART is compatible with

SPI and QSPI for CPOL = 0 and CPHA = 0. The UART

supports data rates up to 230kbaud for standard UART

bit streams as well as IrDA and includes an 8-word

receive FIFO. Also included is a 9-bit-address recogni-

tion interrupt.

The RS-232 transceiver has electrostatic discharge

(ESD) protection on the transmitter outputs and the

receiver inputs. The internal charge-pump capacitors

minimize the number of external components required.

The RS-232 transceivers meet EIA/TIA-232 specifica-

tions for V

down to the minimum supply voltage and

are guaranteed to operate for data rates up to 250kbps.

The UART and RS-232 functions operate as one device

or independently since the two functions share only

supply and ground connections.

UART

The universal asynchronous receiver transmitter

(UART) interfaces the SPI/QSPI/MICROWIRE-compati-

ble synchronous serial data from a microprocessor (µP)

to asynchronous, serial-data communication ports (RS-

232, IrDA). Figure 1 shows the MAX3110E/MAX3111E

functional diagram. Included in the UART function is an

SPI/QSPI/MICROWIREinterface, a baud-rate generator,

and an interrupt generator.

______________________________________________________________________________________

元器件交易网

Protected RS-232 T

SPI/MICROWIRE-Compatible UART and ±15kV ESD-

ransceivers with Internal Capacitors

SPI Interface

edge. Figure 3 shows the detailed serial timing specifi-

The MAX3110E/MAX3111E are compatible with SPI,

cations for the synchronous SPI port.

QSPI (CPOL = 0, CPHA = 0), and MICROWIREserial-

interface standards (Figure 2). The MAX3110E/

Only 16-bit words are expected. If CSgoes high in the

MAX3111E have a unique full-duplex-only architecture

middle of a transmission (any time before the 16th bit),

that expects a 16-bit word for DIN and simultaneously

the sequence is aborted (i.e., data does not get written

produces a 16-bit word for DOUT regardless of which

to individual registers). Most operations, such as the

read/write register is used. The DIN stream is moni-

clearing of internal registers, are executed only on CS’s

tored for its first two bits to tell the UART the type of

rising edge. Every time CSgoes low, a new 16-bit

data transfer being executed (see the

Write

stream is expected. An example of using the Write

Configuration Register

Read Configuration Register

Configuration Register is shown in Figure 4.

Write Data Register

, and

Read Data Registe

r sections).

Table 1 describes the bits located in the Write Config-

DIN (MOSI) is latched on SCLK’s rising edge. DOUT

uration, Read Configuration, Write Data, and Read

(MISO) should be read into the µP on SCLK’s rising

Data Registers. This table also describes whether the

edge. The first bit (bit 15) of DOUT transitions on CS’s

bit is a read or a write bit and the power-on reset state

falling edge, and bits 14–0 transition on SCLK’s falling

(POR) of the bits. Figure 5 shows an example of parity

and word-length control.

DIN

MSB141312111LSB

DOUT

MSB141312111LSB

SCLK

COMPATIBLE

(CPOL = 0, CPHA = 0)

WITH MAX3110E/MAX3111E

SCLK

(CPOL = 0, CPHA = 1)

SCLK

NOT COMPATIBLE

(CPOL = 1, CPHA = 0)

WITH MAX3110E/MAX3111E

SCLK

(CPOL = 1, CPHA = 1)

Figure 2. Compatible CPOL and CPHA Timing Modes

• • •

CSS

CSH

CS1

CSO

SCLK

• • •

DIN

• • •

DOUT

• • •

Figure 3. Detailed Serial Timing Specifications for the Synchronous SPI Port

______________________________________________________________________________________11

MAX3110E/MAX3111E

元器件交易网

SPI/MICROWIRE-Compatible UART and ±15kV ESD-

Protected RS-232 Transceivers with Internal Capacitors

DATA

UPDATED

SCLK

DIN

11FENSHDNTMRMPMRAMIRSTPELB3B2B1B0

DOUT

RT00

Figure 4. Write Configuration Register Example

PE = 0, L = 0

IDLE

STARTD0D1D2D3D4D5D6D7STOPSTOPIDLE

PE = 0, L = 1

IDLE

STARTD0D1D2D3D4D5D6STOPSTOPIDLE

PE = 1, L = 0

IDLE

STARTD0D1D2D3D4D5D6D7PtSTOPSTOPIDLE

PE = 1, L = 1

IDLE

TIME

STARTD0D1D2D3D4D5D6Pt

STOPSTOP

IDLE

SECOND STOP BIT IS OMITTED IF ST = 0.

Figure 5. Parity and Word-Length Control

12______________________________________________________________________________________

元器件交易网

Protected RS-232 T

SPI/MICROWIRE-Compatible UART and ±15kV ESD-

ransceivers with Internal Capacitors

Table 1. Bit Descriptions

BITBITPOR

NAMETYPESTATE

DESCRIPTION

B0–B3write0000Baud-Rate Divisor Select Bits. Sets the baud clock’s value (Table 6).

B0–B3read0000Baud-Rate Divisor Select Bits. Reads the 4-bit baud clock value assigned to these registers.

CTSread

Clear-to-Send-Input. Records the state of the CTSpin (CTS bit = 0 implies CTSpin = logic

change

high).

D0t–D7twriteXXXXXXXX

Transmit-Buffer Register. Eight data bits written into the transmit-buffer register. D7t is ignored

when L = 1.

D0r–D7rread00000000

Eight data bits read from the receive FIFO or the receive-buffer register. When L = 1, D7r is

always 0.

FEN

write

FIFO Enable. Enables the receive FIFO when FEN= 0. When FEN= 1, FIFO is disabled.

FEN

read

FIFO-Enable Readback. FEN’s state is read.

IRwrite0Enables the IrDA timing mode when IR = 1.

IRread0Reads the value of the IR bit.

Lwrite0

Bit to set the word length of the transmitted or received data. L = 0 results in 8-bit words

(9-bit words if PE = 1) (see Figure 5). L = 1 results in 7-bit words (8-bit words if PE = 1).

Lread0Reads the value of the L bit.

Transmit-Parity Bit. This bit is treated as an extra bit that is transmitted if PE = 1. In 9-bit net-

PtwriteXworks, the MAX3110E/MAX3111E do not calculate parity. If PE = 0, then this bit (Pt) is ignored

in transmit mode (see the

9-Bit Networks

section).

Receive-Parity Bit. This bit is the extra bit received if PE = 1. Therefore, PE = 1 results in 9-bit

PrreadXtransmissions (L = 0). If PE = 0, then Pr is set to 0. Pr is stored in the FIFO with the receive data

(see the

9-Bit Networks

section).

Parity-Enable Bit. Appends the Pt bit to the transmitted data when PE = 1, and sends the Pt bit

PEwrite0

as written. No parity bit is transmitted when PE = 0. With PE = 1, an extra bit is expected to be

received. This data is put into the Pr register. Pr = 0 when PE = 0. The MAX3110E/MAX3111E

do not calculate parity.

PEread0Reads the value of the Parity-Enable bit.

write0

Mask for Pr bit. IRQis asserted if PM= 1 and Pr = 1 (Table 7).

Reads the value of the PMbit (Table 7).

Receive Bit or FIFO Not Empty Flag. R = 1 means new data is available to be read or is being

Rread0

read from the receive register or FIFO. If performing a Read Data or Write Data operation, the R

bit will clear on the falling edge of SCLK's 16th pulse if no new data is available.

write0

Mask for R bit. IRQis asserted if RM= 1 and R = 1 (Table 7).

Reads the value of the RMbit (Table 7).

RAM

write0

Mask for RA/FE bit. IRQis asserted if RAM= 1 and RA/FE = 1 (Table 7).

RAM

Reads the value of the RAMbit (Table 7).

RTSwrite0

Request-to-Send Bit. Controls the state of the RTSoutput. This bit is reset on power-up (RTS

bit = 0 sets the RTSpin = logic high).

______________________________________________________________________________________13

MAX3110E/MAX3111E

元器件交易网

SPI/MICROWIRE-Compatible UART and ±15kV ESD-

Protected RS-232 Transceivers with Internal Capacitors

Table 1. Bit Descriptions (continued)

BIT

NAME

BIT

TYPE

POR

STATE

DESCRIPTION

Receiver-Activity/Framing-Error Bit. In shutdown mode, this is the RA bit. In normal operation,

this is the FE bit. In shutdown mode, a transition on RX sets RA = 1. In normal mode, a fram-

ing error sets FE = 1. A framing error occurs if a zero is received when the first stop bit is

expected. FE is set when a framing error occurs, and cleared upon receipt of the next proper-

ly framed character independent of the FIFO being enabled. When the device wakes up, it is

likely that a framing error will occur. This error is cleared with a WriteConfiguration. The FE bit

is not cleared on a ReadDataoperation. When an FE is encountered, the UART resets itself

to the state where it is looking for a start bit.

Software-Shutdown Bit. Enter software shutdown with a WriteConfiguration where SHDNi = 1.

Software shutdown takes effect after CSgoes high, and causes the oscillator to stop as soon

as the transmitter becomes idle. Software shutdown also clears R, T, RA/FE, D0r–D7r,

D0t–D7t, Pr, Pt, and all data in the receive FIFO. RTS and CTS can be read and updated

while in shutdown. Exit software shutdown with a WriteConfiguration where SHDNi = 0. The

oscillator restarts typically within 50ms of CSgoing high. RTS and CTS are unaffected. Refer

to the

Pin Description

for hardware shutdown (SHDNinput).

Shutdown Read-Back Bit. The ReadConfiguration register outputs SHDNo = 1 when the

UART is in shutdown. Note that this bit is not sent until the current byte in the transmitter is

sent (T = 1). This tells the processor when it may shut down the RS-485/RS-422 driver. This bit

is also set immediately when the device is shut down through the SHDNpin.

Transmit-Stop Bit. One stop bit will be transmitted when ST = 0. Two stop bits will be transmit-

ted when ST = 1. The receiver only requires one stop bit.

Reads the value of the ST bit.

Transmit-Buffer-Empty Flag. T = 1 means that the transmit buffer is empty and ready to

accept another data word.

Transmit-Enable Bit. If TE= 1, then only the RTSpin is updated on CS’s rising edge. The con-

tents of RTS, Pt, and D0t–D7t transmit on CS’s rising edge when TE= 0.

Mask for T Bit. IRQis asserted if TM= 1 and T = 1 (Table 7).

Reads the value of the TMbit (Table 7).

RA/FEread0

SHDNiwrite0

SHDNoread0

write

read

write

read

Notice to High-Level Programmers:The UART follows

the SPI convention of providing a bidirectional data path

for writes and reads. Whenever the data is written, data

is also read back. This speeds operation over the SPI

bus, and the UART needs this speed advantage when

operating at high baud rates. In most high-level lan-

guages, such as C, there are commands for writing and

reading stream I/O devices such as the console or serial

port. In C specifically, there is a “PUTCHAR” command

that transmits a character and a “GETCHAR” command

that receives a character. If programmers were to write

direct write and read commands in C with no underlying

driver code, they would notice that a PUTCHAR com-

mand is really a PUTGETCHAR command. These C

commands assume some form of BIOS-level support for

these commands. The proper way to implement these

commands is to write driver code, usually in the form of

an assembly-language interrupt-service routine and a

callable routine used by high-level routines. This driver

handles the interrupts and manages the receive and

transmit buffers for the MAX3110E/MAX3111E. When a

PUTCHAR executes, this driver is called and it safely

buffers any characters received when the current

character is transmitted. When a GETCHAR executes, it

checks its own receive buffer before getting data from

the UART. See the C-language

Outline of a MAX3110E/

MAX3111E Software Driver

in Listing 1, which appears at

the end of this data sheet.

Listing 1 is a C-language outline of an interrupt-driven

software driver that interfaces to a MAX3110E/

MAX3111E, providing an intermediate layer between

the bit-manipulation subroutine and the familiar

PUTCHAR/GETCHARsubroutines.

The user must supply code for managing the transmit

and receive queues as well as the low-level hardware

interface itself. The interrupt control hardware must be

initialized before this driver is called.

______________________________________________________________________________________

元器件交易网

Protected RS-232 T

SPI/MICROWIRE-Compatible UART and ±15kV ESD-

ransceivers with Internal Capacitors

Write Configuration Register (D15, D14 = 1, 1)

tion mode. Bits 13–1 of the DIN word should be zeros,

Configure the UART by writing a 16-bit word to the write

and bit 0 is the test bit to put the UART in test mode

configuration register, which programs the baud rate,

(see the

Test Mode

section). Table 3 shows the bit

data word length, parity enable, and enable of the 8-

assignment for the read configuration register.

word receive FIFO. In this mode, bits 15 and 14 of the

DIN configuration word are both required to be 1 in

Test Mode

order to enable the write configuration mode. Bits 13–0

The device enters a test mode if bit 0 of the DIN config-

of the DIN configuration word set the configuration of

uration word equals one when doing a read configura-

the UART. Table 2 shows the bit assignment for the

tion. In this mode, if CS= 0, the RTSpin transmits a

write configuration register. The write configuration reg-

clock that is 16-times the baud rate. The TX pin is low

ister allows selection between normal UART timing and

as long as CSremains low while in test mode. Table 3

IrDA timing, provides shutdown control, and contains

shows the bit assignment for the read configuration

four interrupt mask bits.

Using the write configuration register clears the receive

FIFO and the R, T, RA/FE, D0r–D7r, D0t–D7t, Pr, and Pt

Write Data Register (D15, D14 = 1, 0)

registers. RTS and CTS remain unchanged. The new

Use the write data register for transmitting to the TX-

configuration is valid on CS’s rising edge if the transmit

buffer and receiving from the RX buffer (and RX FIFO

buffer is empty (T = 1) and transmission is over. If the

when enabled). When using this register, the DIN and

latest transmission has not been completed (T = 0), the

DOUT write data words are used simultaneously, and

registers are updated when the transmission is over.

bits 13–11 for both the DIN and DOUT write data words

are meaningless zeros. The DIN write data word con-

The write configuration register bits (FEN, SHDNi, IR,

tains the data that is being transmitted, and the DOUT

ST, PE, L, B3–B0) take effect after the current transmis-

write data word contains the data that is being received

sion is over. The mask bits (TM, RM, PM, RAM) take

from the RX FIFO. Table 4 shows the bit assignment for

effect immediately after SCLK’s 16th rising edge.

the write data mode. To change the RTSpin’s output

Bits 15 and 14 of the DOUT write configuration (R and

state without transmitting data, set the TEbit high. If

T) are sent out of the MAX3110E/MAX3111E along with

performing a write data operation, the R bit will clear on

14 trailing zeros. The use of the R and T bits is optional,

the falling edge of SCLK’s 16th clock pulse if no new

but ignore the 14 trailing zeros.

data is available.

Warning!The UART requires stable crystal oscillator

Read Data Register (D15, D14 = 0, 0)

operation before configuration (typically ~25ms after

Use the read data register for receiving data from the

power-up). Upon power-up, compare the write configu-

RX FIFO. When using this register, bits 15 and 14 of

ration bits with the read configuration bits in a software

DIN are both required to be 0. Bits 13–0 of the DIN

loop until both match. This ensures that the oscillator is

read-data word should be zeros. Table 5 shows the bit

stable and that the UART is configured correctly.

assignments for the read data mode. Reading data

Read Configuration Mode (D15, D14 = 0, 1)

clears the R bit and interrupt IRQ. If performing a read

The read configuration mode is used to read back the

data operation, the R bit will clear on the falling edge of

last configuration written to the UART. In this mode, bits

SCLKs 16th clock pulse if no new data is available.

15 and 14 of the DIN configuration word are required to

be 0 and 1, respectively, to enable the read configura-

______________________________________________________________________________________15

MAX3110E/MAX3111E

元器件交易网

SPI/MICROWIRE-Compatible UART and ±15kV ESD-

Protected RS-232 Transceivers with Internal Capacitors

Table 2. WriteConfiguration (D15, D14 = 1, 1)

BIT

DIN

DOUT

FEN

SHDNi

RAM

D15 is present at DOUT on CS’s falling edge. Consecutive bits are clocked out on SCLK’s falling edge.

Notes:

bit 15: DOUT

R = 1, Data is available to be read or is being read from the

receive register or FIFO.

R = 0, Receive register and FIFO are empty.

bit 14: DOUT

T = 1, Transmit buffer is empty.

T = 0, Transmit buffer is full.

bits 13–0: DOUT

Zeros

bits 15, 14: DIN

1,1 = Write Configuration

bit 13: DIN

FEN= 0, FIFO is enabled.

FEN = 1, FIFO is disabled.

bit 12: DIN

SHDNi = 1, Enter software shutdown.

SHDNi = 0, Exit software shutdown.

bit 11: DIN

TM= 1, Transmit buffer empty interrupt is enabled.

TM= 0, Transmit buffer empty interrupt is disabled.

bit 10: DIN

RM= 1, Data available in the receive register or FIFO interrupt

is enabled.

RM= 0, Data available in the receive register or FIFO interrupt

is disabled.

bit 9: DIN

PM= 1, Parity bit high received interrupt is enabled.

PM= 0, Parity bit received interrupt is disabled.

bit 8: DIN

RAM= 1, Receiver-activity (shutdown mode)/Framing-error

(normal operation) interrupt is enabled.

RAM= 0, Receiver-activity (shutdown mode)/Framing-error

(normal operation) interrupt is disabled.

bit 7: DIN

IR = 1, IrDA mode is enabled.

IR = 0, IrDA mode is disabled.

bit 6: DIN

ST = 1, Transmit two stop-bits.

ST = 0, Transmit one stop-bit.

bit 5: DIN

PE = 1, Parity is enabled for both transmit (state of Pt) and

receive.

PE = 0, Parity is disabled for both transmit and receive.

bit 4: DIN

L = 1, 7-bit words (8-bit words if PE = 1)

L = 0, 8-bit words (9-bit words if PE = 1)

bits 3–0: DIN

B3–B0 = XXXX, Baud-Rate Divisor Select Bits (see Table 6)

16______________________________________________________________________________________

元器件交易网

Protected RS-232 T

SPI/MICROWIRE-Compatible UART and ±15kV ESD-

ransceivers with Internal Capacitors

Table 3. ReadConfiguration (D15, D14 = 0, 1)

BIT

DIN000TEST

DOUTRT

FEN

SHDNo

TMRMPMRAM

IRSTPELB3B2B1B0

D15 is present at DOUT on CS’s falling edge. Consecutive bits are clocked out on SCLK’s falling edge.

Notes:

bit 15, 14: DIN

bit 15: DOUT

0,1 = Read Configuration

R = 1, Data is available to be read or is being read from the

receive register or FIFO.

bits 13–1: DIN

R = 0, Receive register and FIFO are empty.

Zeros

bit 14: DOUT

bit 0: DIN

T = 1, Transmit buffer is empty.

If TEST = 1 and CS= 0, then RTS=16xBaudCLK

T = 0, Transmit buffer is full.

TEST = 0, Disables test mode

bit 13: DOUT

FEN= 0, FIFO is enabled.

FEN= 1, FIFO is disabled.

bit 12: DOUT

SHDNo = 1, Software shutdown is enabled.

SHDNo = 0, Software shutdown is disabled.

bit 11: DOUT

TM= 1, Transmit buffer empty interrupt is enabled.

TM= 0, Transmit buffer empty interrupt is disabled.

bit 10: DOUT

is enabled.

= 1, Data available in the receive register or FIFO interrupt

is disabled.

= 0, Data available in the receive register or FIFO interrupt

bit 9: DOUT

PM= 1, Parity bit high received interrupt is enabled.

PM= 0, Parity bit received interrupt is disabled.

bit 8: DOUT

RAM

(normal operation) interrupt is enabled.

= 1, Receiver-activity (shutdown mode)/Framing-error

RAM

(normal operation) interrupt is disabled.

= 0, Receiver-activity (shutdown mode)/Framing-error

bit 7: DOUT

IR = 1, IrDA mode is enabled.

IR = 0, IrDA mode is disabled.

bit 6: DOUT

ST = 1, Transmit two stop-bits.

ST = 0, Transmit one stop-bit.

bit 5: DOUT

PE = 1, Parity is enabled for both transmit (state of Pt) and

receive.

PE = 0, Parity is disabled for both transmit and receive.

bit 4: DOUT

L = 1, 7-bit words (8-bit words if PE = 1)

L = 0, 8-bit words (9-bit words if PE = 1)

bits 3–0: DOUT

B3–B0 = XXXX Baud-Rate Divisor Select Bits (see Table 6)

______________________________________________________________________________________17

MAX3110E/MAX3111E

元器件交易网

SPI/MICROWIRE-Compatible UART and ±15kV ESD-

Protected RS-232 Transceivers with Internal Capacitors

Table 4. WriteData (D15, D14 = 1, 0)

BIT

DIN

DOUT

RA/FE

RTS

CTS

D7t

D7r

D6t

D6r

D5t

D5r

D4t

D4r

D3t

D3r

D2t

D2r

D1t

D1r

D0t

D0r

D15 is present at DOUT on CS’s falling edge. Consecutive bits are clocked out on SCLK’s falling edge.

Notes:

bit 15: DOUT

R = 1, Data is available to be read or is being read from the

receive register or FIFO.

R = 0, Receive register and FIFO are empty.

bit 14: DOUT

T = 1, Transmit buffer is empty.

T = 0, Transmit buffer is full.

bits 13–11: DOUT

Zeros

bit 10: DOUT

RA/FE = Receive-Activity (Uart shutdown)/Framing-Error

(Normal Operation) bit

bit 9: DOUT

CTS = CTSinput state. If CTS = 0, then CTS= 1 and vice versa.

bit 8: DOUT

Pr = Received Parity Bit. This is only valid if PE = 1.

bits 7–0: DOUT

D7t–D0t = Received Data Bits. D7r = 0 for L = 1.

bits 15, 14: DIN

1, 0 = Write Data

bits 13–11: DIN

Zeros

bit 10: DIN

TE= 1, Disables transmit and only RTSwill be updated.

TE= 0, Enables transmit.

bit 9: DIN

RTS = 1, Configures RTS= 0 (logic low).

RTS = 0, Configures RTS= 1 (logic high).

bit 8: DIN

Pt = 1, Transmit parity bit is high. If PE = 1, a high parity bit will

be transmitted. If PE = 0, then no parity bit will be transmitted.

Pt = 0, Transmit parity bit is low. If PE = 1, a low parity bit will be

transmitted. If PE = 0, then no parity bit will be transmitted.

bits 7–0: DIN

D7t–D0t = Transmitting Data Bits. D7t is ignored when L = 1.

18______________________________________________________________________________________

元器件交易网

Protected RS-232 T

SPI/MICROWIRE-Compatible UART and ±15kV ESD-

ransceivers with Internal Capacitors

Table 5. ReadData (D15, D14 = 0, 0)

BIT

DIN0000

DOUTRT

00RA/FECTSPrD7rD6rD5rD4rD3rD2rD1rD0r

D15 is present at DOUT on CS’s falling edge. Consecutive bits are clocked out on SCLK’s falling edge.

Notes:

bits 15, 14: DIN

bits 15: DOUT

0, 0 = Read Data

R = 1, Data is available to be read or is being read from the

bits 13–0: DIN

receive register or FIFO.

Zeros

R = 0, Receive register and FIFO are empty.

bit 14: DOUT

T = 1, Transmit buffer is empty.

T = 0, Transmit buffer is full.

bits 13–11: DOUT

Zeros

bit 10: DOUT

RA/FE = Receive-Activity (UARTshutdown)/Framing-Error

(Normal Operation) Bit

bit 9: DOUT

CTS = CTSinput state. If CTS = 0, then CTS= 1 and vice versa.

bit 8: DOUT

Pr = Received parity bit. This is only valid if PE = 1.

bits 7–0: DOUT

D7t–D0t = Received Data Bits. D7r = 0 for L = 1.

______________________________________________________________________________________19

MAX3110E/MAX3111E

元器件交易网

SPI/MICROWIRE-Compatible UART and ±15kV ESD-

Protected RS-232 Transceivers with Internal Capacitors

Baud-Rate Generator

The baud-rate generator determines the rate at which

the transmitter and receiver operate. Bits B3–B0 in the

write configuration register determine the baud-rate

divisor (BRD), which divides the X1 oscillator frequen-

cy. The on-board oscillator operates with either a

1.8432MHz or a 3.6864MHz crystal or is driven at X1

with a 45% to 55% duty-cycle square wave. Table6

shows baud-rate divisors for given input codes as well

as the baud rate for 1.8432MHz and 3.684MHz crystals.

The generator’s clock is 16-times the baud rate.

Interrupt Sources and Masks

Using the Read Data or Write Data register clears the

interrupt IRQ,assuming the conditions that initiated the

interrupt no longer exist. Table 7 gives the details for

each interrupt source. Figure 6 shows the functional

diagram for the interrupt sources and mask blocks.

Following are two examples of setting up an IRQ for the

MAX3110E/MAX3111E:

Example 1.

Set up only the transmit buffer-empty inter-

rupt. Send the 16-bit word below into DIN of the

MAX3110E/MAX3111E using the Write Configuration

MAX3111E for 9600bps, 8-bit words, no parity, and one

stop bit with a 1.8432MHz crystal.

binary 1110

HEX C80A

Table 6. Baud-Rate Selection*

BAUD

B2B1B0

0**

DIVISION

RATIO

128

192

384

BAUD

RATE

OSC

1.8432MHz)

115.2k**

57.6k

28.8k

14.4k

7200

3600

1800

900

38.4k

19.2k

9600

4800

2400

1200

600

300

BAUD

RATE

OSC

3.6864MHz)

230.4k**

115.2k

57.6k

28.8k

14.4k

7200

3600

1800

76.8k

38.4k

19.2k

9600

4800

2400

1200

600

*Standard baud rates shown in bold

**Default baud rate

Example 2.

Set up only the data-available (or data-

being-read) interrupt.

Send the 16-bit word below into DIN of the

MAX3110E/MAX3111E using the Write Configuration

MAX3111E for 9600bps, 8-bit words, no parity, and one

stop bit with a 1.8432MHz crystal.

binary 1110

HEX C40A

NEW DATA AVAILABLE

DATA READ

RM MASK

TRANSMIT BUFFER EMPTY

DATA READ

TM MASK

IRQ

PE = 1 AND RECEIVED

PARITY BIT = 1

PE = 0 OR RECEIVED

PM MASK

PARITY BIT = 0

TRANSITION ON RX

SHUTDOWN

RAM MASK

FRAMING ERROR

SHUTDOWN

RAM MASK

Receive FIFO

The MAX3110E/MAX3111E contain an 8-word receive

FIFO for data received by the UART to minimize

processor overhead. Using the UART-software shut-

down clears the receive FIFO. Upon power-up, the

receive FIFO is enabled. To disable the receive FIFO,

set the FENbit high when writing to the Write

Configuration register. To check whether the FIFO is

enabled or disabled, read back the FENbit using the

Read Configuration.

Figure 6. Functional Diagram for Interrupt Sources and Mask

Blocks

20______________________________________________________________________________________

元器件交易网

Protected RS-232 T

SPI/MICROWIRE-Compatible UART and ±15kV ESD-

ransceivers with Internal Capacitors

Table 7. Interrupt Sources and Masks—Bit Descriptions

BITMASKMEANING

NAMEBITWHEN SET

DESCRIPTION

The Pr bit reflects the value in the word currently in the receive-buffer register

(oldest data available). The Pr bit is set when parity is enabled (PE = 1) and the

Received parity bit = 1

received parity bit is 1. The Pr bit is cleared either when parity is not enabled (PE

= 0) or when parity is enabled and the received bit is 0. An interrupt is issued

based on the oldest Pr value in the receiver FIFO. The oldest Pr value is the next

value read by a Read Data operation.

The R bit is set when new data is available to be read or when data is being read

Data available

from the receive register/FIFO. FIFO is cleared when all data has been read. An

interrupt is asserted as long as R = 1 and RM= 1.

This is the RA (RX-transition) bit in shutdown, and the framing-error (FE) bit in

operating mode. RA is set if there has been a transition on RX since entering

Transition on RX when

shutdown. RA is cleared when the MAX3110E/MAX3111E exits shutdown. IRQis

RA/FE

RAM

in shutdown; framing

asserted when RA is set and RAM= 1.

error when not in

shutdown

FE is determined solely by the currently received data and is not stored in FIFO.

The FE bit is set if a zero is received when the first stop bit is expected. FE is

cleared upon receipt of the next properly framed character. IRQis asserted

when FE is set and RAM= 1.

The T bit is set when the transmit buffer is ready to accept data. IRQis asserted

low if TM= 1 and the transmit buffer becomes empty. This source is cleared on

Transmit buffer is

empty

the rising edge of SCLK’s 16th clock pulse when using a Read Data or Write

Data operation. CS’s rising edge during a Read Data operation. Although the

interrupt is cleared, poll T to determine transmit-buffer status.

UART Software Shutdown

CSgoes high, the oscillator typically takes about 25ms

When in software shutdown, the UART’s oscillator turns

to stabilize. Configure the UART after the oscillator has

off to reduce power dissipation. The UART enters shut-

stabilized by using a write configuration that clears all

down by a software command (SHDNi bit = 1). The

registers but RTS and CTS. If a framing error occurs,

software shutdown is entered upon completing the

you may have not waited long enough for the oscillator

transmission of the data in both the Transmit register

to stabilize.

and the Transmit-Buffer register. The SHDNo bit is set

when the UART enters shutdown. The microcontroller

The hardware shutdown affects only the RS-232 trans-

(µC) monitors the SHDNo bit to determine when the

ceiver, and the software shutdown affects only the

UART is shut down and then shuts down the

UART. See the

RS-232 Transceiver Hardware

RS-232 transceivers.

Shutdown

section.

Software shutdown clears the receive FIFO, R, RA/FE,

Dual Charge-Pump Voltage Converter

D0r–D7r, Pr, and Pt registers and sets the T bit high.

The internal power supply consists of a regulated dual

Configuration bits (RM, TM, PM, RAM, IR, ST, PE, L,

charge pump that provides output voltages of +5.5V

B0–B3, and RTS) are programmable when SHDNo = 1

(doubling charge pump) and -5.5V (inverting charge

and CTS is also readable. Although RA is reset upon

pump), using a +3.3V supply (MAX3111E) or a +5V sup-

entering shutdown, it goes high when any transitions

ply (MAX3110E). The charge pump operates in discontin-

are detected on the RX pin. This allows the UART to

uous mode; if the output voltages are less than 5.5V, the

monitor activity on the receiver when in shutdown.

charge pump is enabled, and if the output voltages

When taking the part out of software shutdown (SHDNi

exceed 5.5V, the charge pump is disabled. Each charge

= 0), the oscillator turns on when CSgoes high. After

pump includes internal flying capacitors and reservoir

capacitors to generate the V+ and V- supplies.

______________________________________________________________________________________21

MAX3110E/MAX3111E

元器件交易网

SPI/MICROWIRE-Compatible UART and ±15kV ESD-

Protected RS-232 Transceivers with Internal Capacitors

RS-232 Transmitters

The transmitters are inverting-level translators that con-

vert CMOS-logic levels to ±5.0V EIA/TIA-232 levels. The

transmitters guarantee a 230kbps data rate with worst-

case loads of 3kΩin parallel with 1000pF, providing

compatibility with PC-to-PC communication software

(such as LapLink™). Transmitters can be paralleled

because the outputs are forced into a high-impedance

state when the device is in hardware shutdown

(SHDN= GND). The MAX3110E/MAX3111E permit the

outputs to be driven up to ±12V while in shutdown.

The transmitter inputs do not have pull-up resistors.

Connect unused inputs to GND or V

5V/div

SHDN

T2OUT

2V/div

T1OUT

= 3.3V

s/div

RS-232 Receivers

The receivers convert RS-232 signals to CMOS-logic

output levels. The MAX3110E/MAX3111E receivers

have inverting outputs and are always active, even

when the part is in hardware (or software) shutdown.

Figure 7. MAX3111E Transmitter Outputs Exiting Shutdown or

Powering Up

RS-232 Transceiver Hardware Shutdown

Supply current falls to I

CCSHDN(H)

when in hardware

shutdown mode (SHDN= low). When shut down, the

device’s charge pumps are turned off, V+ is pulled

down to V

, V- is pulled to ground, and the transmitter

outputs are disabled (high impedance). The time

required to exit shutdown is typically 100µs, as shown

in Figure 7. Connect SHDNto V

if the shutdown

mode is not used. The UART software shutdown does

not affect the RS-232 transceiver.

ESD Test Conditions

ESD performance depends on a variety of conditions.

Contact Maxim’s Quality Assurance (QA) group for a

reliability report that documents test setup, methodolo-

gy, and results.

Human Body Model

Figure 8a shows the Human Body Model, and Figure

8b shows the current waveform it generates when dis-

charged into a low impedance. This model consists of a

100pF capacitor charged to the ESD voltage of inter-

est, which is then discharged into the test device

through a 1.5kΩresistor.

±15kV ESD Protection

As with all Maxim devices, ESD-protection structures

are incorporated on all pins to protect against electro-

static discharges encountered during handling and

assembly. The driver outputs and receiver inputs of the

MAX3110E/MAX3111E have extra protection against

static electricity. Maxim’s engineers have developed

state-of-the-art structures to protect these pins against

ESD of ±15kV without damage. The ESD structures

withstand high ESD in all states: normal operation, shut-

down, and powered down. After an ESD event, the

MAX3110E/MAX3111E keep working without latchup,

whereas competing RS-232 products can latch and

must be powered down to remove latchup.

ESD protection is tested in various ways; the transmitter

outputs and receiver inputs devices are characterized

for protection to the following limits:

•±15kV using the Human Body Model

•±8kV using the Contact-Discharge Method specified

in IEC 1000-4-2

•±15kV using the Air-Gap Methodspecified in IEC

1000-4-2

IEC 1000-4-2

The IEC 1000-4-2 standard covers ESD testing and

performance of finished equipment; it does not specifi-

cally refer to integrated circuits. The MAX3110E/

MAX3111E help you design equipment that meets

Level 4 (the highest level) of IEC 1000-4-2 without the

need for additional ESD-protection components.

The major difference between tests done using the

Human Body Model and IEC1000-4-2 is higher peak

current in IEC 1000-4-2, because series resistance is

lower in the IEC 1000-4-2 model. Hence, the ESD that

withstands voltage measured to IEC 1000-4-2 is gener-

ally lower than that measured using the Human Body

Model. Figure 9a shows the IEC 1000-4-2 model, and

Figure 9b shows the current waveform for the ±8kV

IEC 1000-4-2 Level 4 ESD contact-discharge test.

LapLink is a trademark of Traveling Software.

______________________________________________________________________________________

元器件交易网

Protected RS-232 T

SPI/MICROWIRE-Compatible UART and ±15kV ESD-

ransceivers with Internal Capacitors

1500Ω

CHARGE-CURRENT

DISCHARGE

100%

PEAK-TO-PEAK RINGING

LIMIT RESISTOR

RESISTANCE

90%

(NOT DRAWN TO SCALE)

HIGH-

DEVICE

AMPERES

VOLTAGE

STORAGE

100pFCAPACITOR

UNDER

TEST

36.8%

SOURCE

10%

TIME

CURRENT WAVEFORM

Figure 8a. Human Body ESD Test Model

Figure 8b. Human Body Model Current Waveform

100%

90%

50M to 100M330

Ω

CHARGE-CURRENT

DISCHARGE

LIMIT RESISTOR

RESISTANCE

HIGH-

VOLTAGE

CSTORAGE

DEVICE

150pF

CAPACITOR

UNDER

TEST

SOURCE

10%

= 0.7ns to 1ns

30ns

60ns

Figure 9a. IEC 1000-4-2 ESD Test Model

Figure 9b. IEC 1000-4-2 ESD Generator Current Waveform

The air-gap test involves approaching the device with a

charged probe. The contact-discharge method connects

Applications Information

the probe to the device before the probe is energized.

Crystals, Oscillators, and

Machine Model

Ceramic Resonators

The Machine Model for ESD tests all pins using a

The MAX3110E/MAX3111E include an oscillator circuit

200pF storage capacitor and zero discharge resis-

derived from an external crystal oscillator for baud-rate

tance. Its objective is to emulate the stress caused by

generation. For standard baud rates, use a 1.8432MHz

contact that occurs with handling and assembly during

or 3.6864MHz crystal. The 1.8432MHz crystal results

manufacturing. Of course, all pins require this protec-

in lower operating current; however, the 3.6864MHz

tion during manufacturing, not just RS-232 inputs and

crystal may be more readily available in surface

outputs. Therefore, after PC board assembly, the

mount.

Machine Model is less relevant to I/O ports.

______________________________________________________________________________________23

MAX3110E/MAX3111E

元器件交易网

SPI/MICROWIRE-Compatible UART and ±15kV ESD-

Protected RS-232 Transceivers with Internal Capacitors

Ceramic resonators are low-cost alternatives to crystals

and operate similarly, although the Q and accuracy are

lower. Some ceramic resonators are available with inte-

gral load capacitors, which can further reduce cost. The

tradeoff between crystals and ceramic resonators is in

initial-frequency accuracy and temperature drift. Keep

the total error in the baud-rate generator below 1% for

reliable operation with other systems. This is accom-

plished easily with a crystal and, in most cases, is

achieved with ceramic resonators. Table 8 lists different

types of crystals and resonators and their suppliers.

The MAX3110E/MAX3111E’soscillator supports paral-

lel-resonant mode crystals and ceramic resonators or

can be driven from an external clock source. Internally,

the oscillator consists of an inverting amplifier with its

input, X1, tied to its output, X2, by a bias network that

self-biases the inverter at approximately V

/2. The

external feedback circuit, usually a crystal from X2 to X1,

provides 180°of phase shift, causing the circuit to oscil-

late. As shown in the

Standard Application Circuit,

the

crystal or resonator is connected between X1 and X2,

with the load capacitance for the crystal being the

series combination of C1 and C2. For example, for a

1.8432MHz crystal with a specified load capacitance of

11pF, use capacitors of 22pF on either side of the crystal

to ground. Series-resonant mode crystals have a slight

frequency error, typically oscillating 0.03% higher than

specified series-resonant frequency when operated in

parallel mode.

Note:It is very important to keep crystal, resonator, and

load-capacitor leads and traces as short and direct as

possible. Make the X1 and X2 trace lengths and ground

tracks short, with no intervening traces. This helps mini-

mize parasitic capacitance and noise pickup in the

oscillator, and reduces EMI. Minimize capacitive load-

ing on X2 to minimize supply current. The MAX3110E/

MAX3111E’s X1 input can be driven directly by an

external CMOS clock source. The trip level is approxi-

mately equal to V

/2. Make no connection to X2 in this

mode. If a TTL or non-CMOS clock source is used, AC-

couple it with a 10nF capacitor to X1. A 2V peak-to-

peak swing on the input is required for reliable

operation.

RS-232 Transmitter Outputs

Exiting Shutdown

Figure 7 shows two RS-232 transmitter outputs exiting

shutdown mode. As they become active, the two trans-

mitter outputs are shown going to opposite RS-232 lev-

els (one transmitter input is high; the other is low). Each

transmitter is loaded with 3kΩin parallel with 2500pF.

The transmitter outputs display no ringing or undesir-

able transients as they come out of shutdown. Note that

the transmitters are enabled only when the magnitude

of V- exceeds approximately 3V.

Table 8. Component and Supplier List

DESCRIPTION

Through-Hole Crystal

(HC-49/U)

Through-Hole

Ceramic Resonator

Through-Hole Crystal

(HC-49/US)

SMT Crystal

SMT Ceramic

Resonator

FREQUENCY

(MHz)

1.8432

3.6864

TYPICAL

C1, C2 (pF)

None

(integral)

SUPPLIER

ECS International, Inc.

Murata North America

ECS International, Inc.

AVX/Kyocera

PART

NUMBER

ECS-18-13-1

CSA1.84MG

ECS-36-18-4

ECS-36-20-5P

PBRC-3.68B

PHONE

NUMBER

913-782-7787

800-831-9172

913-782-7787

803-448-9411

24______________________________________________________________________________________

元器件交易网

Protected RS-232 T

SPI/MICROWIRE-Compatible UART and ±15kV ESD-

ransceivers with Internal Capacitors

High Data RatesInterconnection with 3.3V and 5V Logic

The MAX3110E/MAX3111E maintain the RS-232 ±5.0VThe MAX3110E/MAX3111E can directly interface with

minimum transmitter output-voltage specification evenvarious 3.3V and 5V logic families, including ACT and

at the highest guaranteed data rate. Figure 10 shows aHCT CMOS. See Table 9 for more information on possi-

transmitter loopback test circuit. Figure 11 shows able combinations of interconnections.

loopback test result at 120kbps, and Figure 12 shows

the same test at 250kbps. For Figure 11, both transmit-

Typical Applications

ters are driven simultaneously at 120kbps into an RS-

The MAX3110E/MAX3111E each contain a UART, two

232 receiver in parallel with 1000pF. For Figure 12, a

RS-232 drivers, and two RS-232 receivers in one pack-

single transmitter is driven at 250kbps, and both trans-

age. The standard RS-232 typical operating circuit is

mitters are loaded with an RS-232 receiver in parallel

shown in Figure 13.

with 1000pF.

0.1µF

T1IN

5V/div

C1+

V+

C1-

T1OUT

5V/div

C2+

MAX3110E

V-

MAX3111E

C2-

R1OUT

5V/div

T_ IN

T_ OUT

2µs/div

R_ OUT

R_ IN

= 3.3V (MAX3111E), V

= 5.0V (MAX3110E)

1000pF

Figure 12. Loopback Test Result at 250kbps

SHDN

GND

232 ACTIVE

232 SHUTDOWN

SHDN

Figure 10. Loopback Test Circuit

100k

V+

IRQ

V-

µP

DIN

C1+

DOUT

MAX3110E

C1-

T1IN

5V/div

SCLK

MAX3111E

C2+

C2-

T1INT1OUT

5V/div

RTS

T1OUT

T2IN

T2OUT

RS-232 I/O

5V/div

R1OUT

R1IN

R1OUT

CTS

R2OUT

R2IN

2µs/div

GND

= 3.3V (MAX3111E), V

= 5.0V (MAX3110E)

Figure 11. Loopback Test Result at 120kbps

Figure 13. RS-232 Typical Operating Circuit

______________________________________________________________________________________25

MAX3110E/MAX3111E

元器件交易网

SPI/MICROWIRE-Compatible UART and ±15kV ESD-

Protected RS-232 Transceivers with Internal Capacitors

Table 9. Logic-Family Compatibility with

Various Supply Voltages

LOGIC

POWER-SUPPLY

VOLTAGE

(V)

(MAX3110E)

3.3

(MAX3111E)

SUPPLY

VOLTAGE

(V)

COMPATIBILITY

An IR and RS-232 typical operating circuit is shown in

Figure 14. Since the MAX3110E/MAX3111E’s internal

UART has IrDA capability, a standard IR transceiver

(the MAX3120) can be used to provide the IrDA com-

munication. The two-driver/two-receiver RS-232 trans-

ceiver can be used with a software UART to provide

RS-232 communication.

Compatible with all

TTL and CMOS fami-

lies

Compatible with all

CMOS families

Compatible with ACT

and HCT CMOS, and

with AC, HC, or

CD4000 CMOS

9-Bit Networks

The MAX3110E/MAX3111E support a common multi-

drop communication technique referred to as 9-bit

mode. In this mode, the parity bit is set to indicate a

message that contains a header with a destination

address. The MAX3110E/MAX3111E’s parity mask can

be set to generate interrupts for this condition.

Operating a network in this mode reduces the process-

ing overhead of all nodes by enabling the slave con-

trollers to ignore most message traffic. This relieves the

remote processor to handle more useful tasks.

3.3

232 ACTIVE

SHDN

232 SHUTDOWN

100k

IRQ

DIN

DOUT

SCLK

UART

IrDA

MODE

RXD

MAX3120

TXD

IrDA

I/O

µP

MAX3110E

MAX3111E

T1OUT

R1IN

RS-232 I/O

NON-IrDA

UART

T1IN

R1OUT

CTS

RTS

R2OUT

T2IN

C1+

C1-

GND

R2IN

T2OUT

V+

V-

C2+

C2-

Figure 14. IR and RS-232 Typical Operating Circuit

26______________________________________________________________________________________

元器件交易网

Protected RS-232 T

SPI/MICROWIRE-Compatible UART and ±15kV ESD-

ransceivers with Internal Capacitors

In 9-bit mode, the MAX3110E/MAX3111E is set up with

eight bits plus parity. The parity bit in all normal mes-

sages is clear but is set in an address-type message.

NORMAL UART

The MAX3110E/MAX3111E’s parity-interrupt mask gen-

101001101

erates an interrupt on high parity when enabled. When

the master sends an address message with the parity

IrDA

bit set, all MAX3110E/MAX3111E nodes issue an inter-

rupt. All nodes then retrieve the received byte to com-

pare to their assigned address. Once addressed, the

IrDA

node continues to process each received byte. If the

node was not addressed, it ignores all message traffic

until a new address is sent out by the master.

NORMAL

The parity/9th-bit interrupt is controlled only by the data

in the receive register and is not affected by data in the

FIFO, so the most effective use of the parity/9th-bit

DATA BITS

interrupt is with FIFO disabled. With the FIFO disabled,

UART FRAME

received non-address words can be ignored and not

even read from the UART. For more detailed informa-

Figure 15. IrDA Timing

tion on 9-bit mode, refer to the MAX3100 data sheet.

SIR IrDA Mode

Layout and Power-Supply

The MAX3110E/MAX3111E’s IrDA mode can be used

_____________________Considerations

to communicate with other IrDA SIR-compatible

The MAX3110E/MAX3111E require basic layout tech-

devices or to reduce power consumption in opto-isolat-

niques and fundamental power supply considerations.

ed applications.

The minimum requirements include: (1) placing a 1µF

In IrDA mode, a bit period is shortened to 3/16 of a

ceramic bypass capacitor as close as possible to V

baud period (1.61µs at 115,200 baud). A data zero is

preferably right next to the V

lead or on the opposite

transmitted as a pulse of light (TX pin = logic low, RX

side of the PCB directly below the V

lead; (2) using

pin = logic high), as shown in Figure 15.

an internal ground plane within the PCB, returning all

In receive mode, the RX signal’s sampling is done

circuit grounds to this ground plane, or using a ‘star’

halfway into the transmission of a high level. The sam-

ground technique where all circuit grounds are

pling is done once (instead of three times, as in normal

returned to a common ground point at the ‘GND’ lead

mode). The MAX3110E/MAX3111E ignore pulses short-

of the IC; 3) ensuring that the power source to the IC

er than approximately 1/16 of the baud period. The

has a low inductive path and is high-frequency

IrDA device that is communicating with the MAX3110E/

bypassed to absorb ESD events with significant

MAX3111E must be set to transmit pulses at 3/16 of the

changes in the supply voltage.

baud period. For compatibility with other IrDA devices,

set the format to 8-bit data, one stop, no parity. For

more detailed information on SIR IrDA mode, refer to

the MAX3100 data sheet.

______________________________________________________________________________________27

MAX3110E/MAX3111E

元器件交易网

SPI/MICROWIRE-Compatible UART and ±15kV ESD-

Protected RS-232 Transceivers with Internal Capacitors

Listing 1. Outline for a MAX3110E/MAX3111E Software Driver

This is a C-language outline of an interrupt-driven software driver that interfaces

to a MAX3110E/MAX3111E, providing an intermediate layer between the bit-manipulation

subroutine and the familiar PutChar / GetChar subroutines.

User must supply code for managing the transmit and receive queues, as well as the

low-level hardware interface itself. The interrupt control hardware must be

initialized before this driver is called.

char is an 8 bit character. int is a 16 bit unsigned integer.

& is the bitwise Boolean AND operator. | is the bitwise Boolean OR operator.

/* High level interface routine to put a character to the MAX3110E/MAX3111E. */

PutChar ( char c )

{

EnQueue ( txqueue, c );

/* enable the transmit-buffer-empty interrupt */

config = config | 0x0800; /* set the TM bit */

config = config | 0xC000; /* set bits 15 and 14 */

MAX3110E/MAX3111E ( config );

}

/* High level interface routine to get a character from the MAX3110E/MAX3111E.

** Wait for a character to be received, if necessary.

char GetChar ( )

{

while ( IsQueueEmpty ( rxqueue ) )

/* wait for data to be received */ ;

return DeQueue ( rxqueue );

}

/* Configure the MAX3110E/MAX3111E with the specified baud rate. */

ConfigureMAX3110E/MAX3111E ( int baud_rate_index )

{

baud_rate_index = baud_rate_index & 0x000F; /* restrict to a 4 bit field */

config = 0xC400 + baud_rate_index; /* enable received data interrupt */

MAX3110E/MAX3111E ( config );

}

/* private variable that stores the configuration settings for the MAX3110E/MAX3111E

int config;

/* Low level communication routine between the computer and the MAX3110E/MAX3111E.

** This is a PRIVATE routine to be used only within the driver software.

int MAX3110E/MAX3111E ( int mosi )

{

int miso;

/* this is interface-specific.

** Transmit 16 bits of master-out, slave-in data, MSB first,

** while simultaneously receiving 16 bits of master-in, slave-out data.

** If and SPI hardware interface is available, use (CPOL=0,CPHA=0) mode.

** Lacking specialized hardware, just set and clear I/O bits to generate

** the waveform in figures 2 and 3 in the MAX3110E/MAX311E data sheet.

return miso; /* return 16 bits of master-in, slave-out data, MSB first */

}

28______________________________________________________________________________________

元器件交易网

Protected RS-232 T

SPI/MICROWIRE-Compatible UART and ±15kV ESD-

ransceivers with Internal Capacitors

Listing 1. Outline for a MAX3110E/MAX3111E Software Driver (continued)

/* This driver needs a txqueue transmit-data queue and a rxqueue receive-data queue.

** These can be ring buffers or any other kind of first-in, first-out data queue.

EnQueue ( queue , char )

char DeQueue ( queue )

true/false IsQueueEmpty ( queue )

/* Interrupt service routine called when the MAX3110EMAX3111E’s INT pin falls to a

low level.

** This is a PRIVATE routine to be used only within the driver software.

ServiceMAX3110E/MAX3111Eint ( )

{

int rxdata;

int txdata;

char c;

/* issue a READ DATA command to discover the cause of the interrupt */

rxdata = MAX3110E/MAX3111E ( 0 );

if ( rxdata & 0x8000 )/* the R bit = 1 */

{

c = rxdata & 0x00FF; /* get the received character data */

EnQueue ( rxqueue, c );

}

if ( rxdata & 0x4000 ) /* the T bit = 1 */

{

if ( IsQueueEmpty ( txqueue ) )

{

/* mask the transmit-buffer-empty interrupt */

config = config & ~ 0x0800; /* clear the TM bit */

config = config | 0xC000; /* set bits 15 and 14 */

MAX3110E/MAX3111E ( config );

}

else /* transmit some data */

{

/* issue a WRITE DATA command */

txdata = DeQueue ( txqueue );

c = txdata & 0x00FF; /* get the transmit character */

MAX3110E/MAX3111E ( 0x8000 | c );

}

} /* end of ServiceMAX3110E/MAX3111Eint */

______________________________________________________________________________________29

MAX3110E/MAX3111E

元器件交易网

SPI/MICROWIRE-Compatible UART and ±15kV ESD-

Protected RS-232 Transceivers with Internal Capacitors

Ordering Information

PARTTEMP. RANGE

PIN-

PACKAGE

28 Wide SO

28 Plastic DIP

28 Wide SO

28 Plastic DIP

28 Wide SO

28 Plastic DIP

(V)

3.3

Chip Information

TRANSISTOR COUNT: 7977

MAX3110EEWI-40°C to +85°C

MAX3110EENI-40°C to +85°C

MAX3111ECWI

0°C to +70°C

MAX3111ECNI0°C to +70°C

MAX3111EEWI-40°C to +85°C

MAX3111EENI-40°C to +85°C

Pin Configuration

TOP VIEW

R2IN

R2OUT

T2IN

T1IN

R1OUT

R1IN

T1OUT

CTS

RTS

28T2OUT

27GND

26V-

25C2-

24C2+

MAX3110E

MAX3111E

23C1-

22C1+

21V+

20SHDN

19IRQ

18CS

17SCLK

16DOUT

DIN

Narrow DIP/Wide SO

30______________________________________________________________________________________

元器件交易网

Protected RS-232 T

SPI/MICROWIRE-Compatible UART and ±15kV ESD-

ransceivers with Internal Capacitors

Package Information

______________________________________________________________________________________31

MAX3110E/MAX3111E

元器件交易网

SPI/MICROWIRE-Compatible UART and ±15kV ESD-

Protected RS-232 Transceivers with Internal Capacitors

Package Information (continued)

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are

implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.

____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600